From cdc1aff17f1b72d112f508450f2d103b6b955b74 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Wed, 12 Nov 2025 18:24:35 +0000 Subject: [PATCH] perf arm_spe: Introduce data processing macro for SVE operations Introduce the ARM_SPE_OP_DP (data processing) macro as associated information for SVE operations. For SVE register access, only ARM_SPE_OP_SVE is set; for SVE data processing, both ARM_SPE_OP_SVE and ARM_SPE_OP_DP are set together. Signed-off-by: Leo Yan Reviewed-by: Ian Rogers Reviewed-by: James Clark Signed-off-by: Namhyung Kim --- tools/perf/util/arm-spe-decoder/arm-spe-decoder.c | 4 ++-- tools/perf/util/arm-spe-decoder/arm-spe-decoder.h | 4 ++-- tools/perf/util/arm-spe.c | 5 +---- 3 files changed, 5 insertions(+), 8 deletions(-) diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c index 847c29385bea8..6974f594f37c9 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c +++ b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c @@ -201,12 +201,12 @@ static int arm_spe_read_record(struct arm_spe_decoder *decoder) else decoder->record.op |= ARM_SPE_OP_LD; if (SPE_OP_PKT_LDST_SUBCLASS_SVE_SME_REG(payload)) - decoder->record.op |= ARM_SPE_OP_SVE_LDST; + decoder->record.op |= ARM_SPE_OP_SVE; break; case SPE_OP_PKT_HDR_CLASS_OTHER: decoder->record.op |= ARM_SPE_OP_OTHER; if (SPE_OP_PKT_OTHER_SUBCLASS_SVE(payload)) - decoder->record.op |= ARM_SPE_OP_SVE_OTHER; + decoder->record.op |= ARM_SPE_OP_SVE | ARM_SPE_OP_DP; break; case SPE_OP_PKT_HDR_CLASS_BR_ERET: decoder->record.op |= ARM_SPE_OP_BRANCH_ERET; diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h index b555e2cc1dc36..acab6d11096b1 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h +++ b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h @@ -43,8 +43,7 @@ enum arm_spe_2nd_op_ldst { ARM_SPE_OP_UNSPEC_REG = 1 << 9, ARM_SPE_OP_NV_SYSREG = 1 << 10, ARM_SPE_OP_SIMD_FP = 1 << 11, - ARM_SPE_OP_SVE_OTHER = 1 << 12, - ARM_SPE_OP_SVE_LDST = 1 << 13, + ARM_SPE_OP_SVE = 1 << 12, /* Assisted information for memory / SIMD */ ARM_SPE_OP_LD = 1 << 20, @@ -52,6 +51,7 @@ enum arm_spe_2nd_op_ldst { ARM_SPE_OP_ATOMIC = 1 << 22, ARM_SPE_OP_EXCL = 1 << 23, ARM_SPE_OP_AR = 1 << 24, + ARM_SPE_OP_DP = 1 << 25, /* Data processing */ }; enum arm_spe_2nd_op_branch { diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index 614ce032f87e4..881257d395870 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -346,10 +346,7 @@ static struct simd_flags arm_spe__synth_simd_flags(const struct arm_spe_record * { struct simd_flags simd_flags = {}; - if ((record->op & ARM_SPE_OP_LDST) && (record->op & ARM_SPE_OP_SVE_LDST)) - simd_flags.arch |= SIMD_OP_FLAGS_ARCH_SVE; - - if ((record->op & ARM_SPE_OP_OTHER) && (record->op & ARM_SPE_OP_SVE_OTHER)) + if (record->op & ARM_SPE_OP_SVE) simd_flags.arch |= SIMD_OP_FLAGS_ARCH_SVE; if (record->type & ARM_SPE_SVE_PARTIAL_PRED) -- 2.47.3