From cf9e6560fa03d6c26b97ad16b96cbc38ceb8997b Mon Sep 17 00:00:00 2001 From: Siddhesh Poyarekar Date: Fri, 11 Sep 2020 09:18:07 +0530 Subject: [PATCH] [Morello] Loads and stores with alternate base These are loads that use a capability base register in A64 and 64-bit integer register in C64. This patch implements LDAR, LDARB, STLR and STLRB. gas/ChangeLog: 2020-10-20 Siddhesh Poyarekar * config/tc-aarch64.c (parse_operands): Add Wt. * testsuite/gas/aarch64/morello_ldst-c64.d: Add tests. * testsuite/gas/aarch64/morello_ldst.d: Likewise. * testsuite/gas/aarch64/morello_ldst.s: Likewise. include/ChangeLog: 2020-10-20 Siddhesh Poyarekar * opcode/aarch64.h (aarch64_opnd): Add Wt. opcodes/ChangeLog: 2020-10-20 Siddhesh Poyarekar * aarch64-opc.c (get_altbase_reg_name): New function. (aarch64_print_operand): Use it. Add Wt. * aarch64-tbl.h (QL2_A64C_W_CAPADDR): New macro. (aarch64_opcode_table): Add instructions. (AARCH64_OPERANDS): New operand. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. --- gas/ChangeLog | 7 +++++++ gas/config/tc-aarch64.c | 4 ++++ gas/testsuite/gas/aarch64/morello_ldst-c64.d | 12 ++++++++++++ gas/testsuite/gas/aarch64/morello_ldst.d | 12 ++++++++++++ gas/testsuite/gas/aarch64/morello_ldst.s | 18 ++++++++++++++++++ include/ChangeLog | 4 ++++ include/opcode/aarch64.h | 2 ++ opcodes/ChangeLog | 11 +++++++++++ opcodes/aarch64-opc.c | 14 +++++++++++++- opcodes/aarch64-tbl.h | 15 +++++++++++++++ 10 files changed, 98 insertions(+), 1 deletion(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index 1f85fddd081..725661c7554 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,10 @@ +2020-10-20 Siddhesh Poyarekar + + * config/tc-aarch64.c (parse_operands): Add Wt. + * testsuite/gas/aarch64/morello_ldst-c64.d: Add tests. + * testsuite/gas/aarch64/morello_ldst.d: Likewise. + * testsuite/gas/aarch64/morello_ldst.s: Likewise. + 2020-10-20 Siddhesh Poyarekar * config/tc-aarch64.c (parse_operands, fix_insn): Add diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index e0ee563c66c..abe88e354cb 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -6444,6 +6444,10 @@ parse_operands (char *str, const aarch64_opcode *opcode) switch (operands[i]) { + case AARCH64_OPND_Wt: + po_int_reg_or_fail (REG_TYPE_R_32); + break; + case AARCH64_OPND_Rd: case AARCH64_OPND_Rn: case AARCH64_OPND_Rm: diff --git a/gas/testsuite/gas/aarch64/morello_ldst-c64.d b/gas/testsuite/gas/aarch64/morello_ldst-c64.d index cfc65036043..a200110fbb4 100644 --- a/gas/testsuite/gas/aarch64/morello_ldst-c64.d +++ b/gas/testsuite/gas/aarch64/morello_ldst-c64.d @@ -214,3 +214,15 @@ Disassembly of section \.text: .*: c2c413e2 ldpbr c2, \[csp\] .*: c2c43042 ldpblr c2, \[c2\] .*: c2c41042 ldpbr c2, \[c2\] +.*: 425f7d82 ldar c2, \[x12\] +.*: 421f7d82 stlr c2, \[x12\] +.*: 425f7fe2 ldar c2, \[sp\] +.*: 421f7fe2 stlr c2, \[sp\] +.*: 427f7d82 ldarb w2, \[x12\] +.*: 427ffd82 ldar w2, \[x12\] +.*: 423f7d82 stlrb w2, \[x12\] +.*: 423ffd82 stlr w2, \[x12\] +.*: 427f7fe2 ldarb w2, \[sp\] +.*: 427fffe2 ldar w2, \[sp\] +.*: 423f7fe2 stlrb w2, \[sp\] +.*: 423fffe2 stlr w2, \[sp\] diff --git a/gas/testsuite/gas/aarch64/morello_ldst.d b/gas/testsuite/gas/aarch64/morello_ldst.d index 49a57a68c3b..70c1c59cd0f 100644 --- a/gas/testsuite/gas/aarch64/morello_ldst.d +++ b/gas/testsuite/gas/aarch64/morello_ldst.d @@ -213,3 +213,15 @@ Disassembly of section \.text: .*: c2c413e2 ldpbr c2, \[csp\] .*: c2c43042 ldpblr c2, \[c2\] .*: c2c41042 ldpbr c2, \[c2\] +.*: 425f7ea2 ldar c2, \[c21\] +.*: 421f7ea2 stlr c2, \[c21\] +.*: 425f7fe2 ldar c2, \[csp\] +.*: 421f7fe2 stlr c2, \[csp\] +.*: 427f7ea2 ldarb w2, \[c21\] +.*: 427ffea2 ldar w2, \[c21\] +.*: 423f7ea2 stlrb w2, \[c21\] +.*: 423ffea2 stlr w2, \[c21\] +.*: 427f7fe2 ldarb w2, \[csp\] +.*: 427fffe2 ldar w2, \[csp\] +.*: 423f7fe2 stlrb w2, \[csp\] +.*: 423fffe2 stlr w2, \[csp\] diff --git a/gas/testsuite/gas/aarch64/morello_ldst.s b/gas/testsuite/gas/aarch64/morello_ldst.s index 6de19b0e6a1..98db4907c3d 100644 --- a/gas/testsuite/gas/aarch64/morello_ldst.s +++ b/gas/testsuite/gas/aarch64/morello_ldst.s @@ -163,3 +163,21 @@ morello_branch_load c2 .endm morello_branch_load2 csp morello_branch_load2 c2 + +// Alternate base loads and stores. + + .macro morello_ldst_alt_base ct, cnsp + .irp op,ldar, stlr + \op \ct, [\cnsp] + .endr + .endm +morello_ldst_alt_base c2, ALTVAREG +morello_ldst_alt_base c2, ALTSP + + .macro morello_ldst_alt_basew wt, cnsp + .irp op, ldarb, ldar, stlrb, stlr + \op \wt, [\cnsp] + .endr + .endm +morello_ldst_alt_basew w2, ALTVAREG +morello_ldst_alt_basew w2, ALTSP diff --git a/include/ChangeLog b/include/ChangeLog index 710db31c272..937e34f7b99 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,7 @@ +2020-10-20 Siddhesh Poyarekar + + * opcode/aarch64.h (aarch64_opnd): Add Wt. + 2020-10-20 Siddhesh Poyarekar * opcode/aarch64.h (aarch64_opnd): Add A64C_ADDR_SIMM9. diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 4366b2a2d68..b55d459f9e3 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -252,6 +252,8 @@ enum aarch64_opnd AARCH64_OPND_Rn, /* Integer register as source. */ AARCH64_OPND_Rm, /* Integer register as source. */ AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */ + AARCH64_OPND_Wt, /* 32-bit integer register used in ld/st + instructions. */ AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */ AARCH64_OPND_Rt_LS64, /* Integer register used in LS64 instructions. */ AARCH64_OPND_Rt_SP, /* Integer Rt or SP used in STG instructions. */ diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 5cdc946836c..4fd084b8ac2 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,14 @@ +2020-10-20 Siddhesh Poyarekar + + * aarch64-opc.c (get_altbase_reg_name): New function. + (aarch64_print_operand): Use it. Add Wt. + * aarch64-tbl.h (QL2_A64C_W_CAPADDR): New macro. + (aarch64_opcode_table): Add instructions. + (AARCH64_OPERANDS): New operand. + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Regenerate. + * aarch64-opc-2.c: Regenerate. + 2020-10-20 Siddhesh Poyarekar * aarch64-asm.c (aarch64_ins_addr_simm): Support scaling. diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index e8d4f7451a3..1fcabb39df6 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -3119,6 +3119,17 @@ get_cap_reg_name (int regno, int sp_reg_p) return int_reg[has_zr][2][regno]; } +static inline const char * +get_altbase_reg_name (aarch64_feature_set features, int regno, int sp_reg_p, + const aarch64_opcode *opcode) +{ + if (AARCH64_CPU_HAS_FEATURE(features, AARCH64_FEATURE_C64) + && opcode->iclass != br_capaddr) + return get_64bit_int_reg_name (regno, sp_reg_p); + else + return get_cap_reg_name (regno, sp_reg_p); +} + static inline const char * get_base_reg_name (aarch64_feature_set features, int regno, int sp_reg_p) { @@ -3433,6 +3444,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_Rn: case AARCH64_OPND_Rm: case AARCH64_OPND_Rt: + case AARCH64_OPND_Wt: case AARCH64_OPND_Rt2: case AARCH64_OPND_Rs: case AARCH64_OPND_Ra: @@ -3927,7 +3939,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_CAPADDR_SIMPLE: snprintf (buf, size, "[%s]", - get_cap_reg_name (opnd->addr.base_regno, 1)); + get_altbase_reg_name (features, opnd->addr.base_regno, 1, opcode)); break; case AARCH64_OPND_ADDR_SIMPLE: diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 5cb8d9ee2ec..e782777f5b5 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2427,6 +2427,12 @@ QLF2(CA, S_Q), \ } +/* LDAR Wt, [] */ +#define QL2_A64C_W_CAPADDR \ +{ \ + QLF2(W, S_S), \ +} + /* LDAPR Ct, [] */ #define QL2_A64C_CA_ADDR \ { \ @@ -4232,6 +4238,14 @@ const struct aarch64_opcode aarch64_opcode_table[] = A64C_INSN ("swpal", 0xa2e08000, 0xffe0fc00, a64c, 0, OP3 (Cas, Cat, ADDR_SIMPLE), QL3_A64C_CA_CA_ADDR, 0), A64C_INSN ("swpl", 0xa2608000, 0xffe0fc00, a64c, 0, OP3 (Cas, Cat, ADDR_SIMPLE), QL3_A64C_CA_CA_ADDR, 0), + /* Load/stores with alternate base, i.e. [] in A64 mode and [] in C64 mode. */ + A64C_INSN ("ldar", 0x425f7c00, 0xfffffc00, ldstexcl, 0, OP2 (Cat, CAPADDR_SIMPLE), QL2_A64C_CA_CAPADDR, 0), + A64C_INSN ("ldar", 0x427ffc00, 0xfffffc00, ldstexcl, 0, OP2 (Wt, CAPADDR_SIMPLE), QL2_A64C_W_CAPADDR, 0), + A64C_INSN ("ldarb", 0x427f7c00, 0xfffffc00, ldstexcl, 0, OP2 (Wt, CAPADDR_SIMPLE), QL2_A64C_W_CAPADDR, 0), + A64C_INSN ("stlr", 0x421f7c00, 0xfffffc00, ldstexcl, 0, OP2 (Cat, CAPADDR_SIMPLE), QL2_A64C_CA_ADDR, 0), + A64C_INSN ("stlr", 0x423ffc00, 0xfffffc00, ldstexcl, 0, OP2 (Wt, CAPADDR_SIMPLE), QL2_A64C_W_CAPADDR, 0), + A64C_INSN ("stlrb", 0x423f7c00, 0xfffffc00, ldstexcl, 0, OP2 (Wt, CAPADDR_SIMPLE), QL2_A64C_W_CAPADDR, 0), + A64C_INSN ("ret", 0xc2c25000, 0xfffffc1f, a64c, 0, OP1 (Can), QL1_A64C_CA, F_OPD0_OPT | F_DEFAULT (30)), A64C_INSN ("retr", 0xc2c25003, 0xfffffc1f, a64c, 0, OP1 (Can), QL1_A64C_CA, 0), A64C_INSN ("rets", 0xc2c25002, 0xfffffc1f, a64c, 0, OP1 (Can), QL1_A64C_CA, 0), @@ -5697,6 +5711,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = Y(INT_REG, regno, "Rn", 0, F(FLD_Rn), "an integer register") \ Y(INT_REG, regno, "Rm", 0, F(FLD_Rm), "an integer register") \ Y(INT_REG, regno, "Rt", 0, F(FLD_Rt), "an integer register") \ + Y(INT_REG, regno, "Wt", 0, F(FLD_Rt), "a 32-bit integer register") \ Y(INT_REG, regno, "Rt2", 0, F(FLD_Rt2), "an integer register") \ Y(INT_REG, regno, "Rt_LS64", 0, F(FLD_Rt), "an integer register") \ Y(INT_REG, regno, "Rt_SP", OPD_F_MAYBE_SP, F(FLD_Rt), \ -- 2.47.2