From cfdab86f20f6e77d9c8bf982989f78ef975c7611 Mon Sep 17 00:00:00 2001 From: Robin Dapp Date: Thu, 12 Dec 2024 10:33:28 +0100 Subject: [PATCH] RISC-V: Emit vector shift pattern for const_vector [PR117353]. In PR117353 and PR117878 we expand a const vector during reload. For this we use an unpredicated left shift. Normally an insn like this is split but as we introduce it late and cannot create pseudos anymore it remains unpredicated and is not recognized by the vsetvl pass (where we expect all insns to be in predicated RVV format). This patch directly emits a predicated shift instead. We could distinguish between !lra_in_progress and lra_in_progress and emit an unpredicated shift in the former case but we're not very likely to optimize it anyway so it doesn't seem worth it. PR target/117353 PR target/117878 gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_const_vector): Use predicated instead of simple shift. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr117353.c: New test. --- gcc/config/riscv/riscv-v.cc | 8 +++-- .../gcc.target/riscv/rvv/autovec/pr117353.c | 29 +++++++++++++++++++ 2 files changed, 34 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117353.c diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 47bc0255aa38..2530fd9c9799 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1439,9 +1439,11 @@ expand_const_vector (rtx target, rtx src) rtx shift_count = gen_int_mode (exact_log2 (builder.npatterns ()), builder.inner_mode ()); - rtx tmp1 = expand_simple_binop (builder.mode (), LSHIFTRT, - vid, shift_count, NULL_RTX, - false, OPTAB_DIRECT); + rtx tmp1 = gen_reg_rtx (builder.mode ()); + rtx shift_ops[] = {tmp1, vid, shift_count}; + emit_vlmax_insn (code_for_pred_scalar + (LSHIFTRT, builder.mode ()), BINARY_OP, + shift_ops); /* Step 3: Generate tmp2 = tmp1 * step.  */ rtx tmp2 = gen_reg_rtx (builder.mode ()); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117353.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117353.c new file mode 100644 index 000000000000..135a00194c9d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117353.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gcv_zvl256b -mabi=lp64d" } */ + +int *b; + +inline void c (char *d, int e) +{ + d[0] = 0; + d[1] = e; +} + +void f (); + +void h () +{ + for (;;) + { + char *a; + long g = 8; + while (g) + { + c (a, *b); + b++; + a += 2; + g--; + } + f (); + } +} -- 2.47.2