From cffa413f1c94d8da45b31dd958bfeaa72329991b Mon Sep 17 00:00:00 2001 From: Ankit Nautiyal Date: Sat, 22 Nov 2025 11:06:51 +0530 Subject: [PATCH] drm/i915/dp: Restrict max source rate for WCL to HBR3 WCL supports a maximum of HBR3 8.1 Gbps for both eDP/DP. Limit the max source rate to HBR3 for WCL. v2: Move the check inside mtl_max_source_rate(). (Suraj) Bspec:74286 Signed-off-by: Ankit Nautiyal Reviewed-by: Suraj Kandpal Link: https://patch.msgid.link/20251122053651.759389-1-ankit.k.nautiyal@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 441995486745..c27e9186a754 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -520,7 +520,8 @@ static int mtl_max_source_rate(struct intel_dp *intel_dp) struct intel_display *display = to_intel_display(intel_dp); struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; - if (intel_encoder_is_c10phy(encoder)) + if (intel_encoder_is_c10phy(encoder) || + display->platform.pantherlake_wildcatlake) return 810000; if (DISPLAY_VERx100(display) == 1401) -- 2.47.3