From d700b2a440518b087af2808b7db9ab091ed53a4a Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Thu, 29 Jan 2026 12:12:04 -0500 Subject: [PATCH] net: phy: dp83867: Program TX FIFO for all interfaces All supported interfaces use the TX FIFO register at least some of the time, so there's no point in checking the interface. Retain the check for the RX FIFO level since it is only used by SGMII. Signed-off-by: Sean Anderson Link: https://patch.msgid.link/20260129171205.3868605-2-sean.anderson@linux.dev Signed-off-by: Jakub Kicinski --- drivers/net/phy/dp83867.c | 31 ++++++++++++++----------------- 1 file changed, 14 insertions(+), 17 deletions(-) diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 5f5de01c41e19..7e16e92994579 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -744,27 +744,24 @@ static int dp83867_config_init(struct phy_device *phydev) */ phy_disable_eee(phydev); - if (phy_interface_is_rgmii(phydev) || - phydev->interface == PHY_INTERFACE_MODE_SGMII) { - val = phy_read(phydev, MII_DP83867_PHYCTRL); - if (val < 0) - return val; - - val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK; - val |= (dp83867->tx_fifo_depth << - DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT); + val = phy_read(phydev, MII_DP83867_PHYCTRL); + if (val < 0) + return val; - if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { - val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK; - val |= (dp83867->rx_fifo_depth << - DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT); - } + val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK; + val |= (dp83867->tx_fifo_depth << + DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT); - ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); - if (ret) - return ret; + if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { + val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK; + val |= (dp83867->rx_fifo_depth << + DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT); } + ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); + if (ret) + return ret; + if (phy_interface_is_rgmii(phydev)) { val = phy_read(phydev, MII_DP83867_PHYCTRL); if (val < 0) -- 2.47.3