From d88d5bedb502eed6f439838b1e6148942a9232b7 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Barnab=C3=A1s=20Cz=C3=A9m=C3=A1n?= Date: Mon, 17 Nov 2025 17:57:06 +0100 Subject: [PATCH] dt-bindings: clock: qcom: Add MSM8940 Global Clock Controller MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Add devicetree bindings for the global clock controller on Qualcomm MSM8940 platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Barnabás Czémán Link: https://lore.kernel.org/r/20251117-gcc-msm8940-sdm439-v2-1-4af57c8bc7eb@mainlining.org Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/clock/qcom,gcc-msm8953.yaml | 5 +++-- include/dt-bindings/clock/qcom,gcc-msm8917.h | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml index f2e37f439d28b..68fcd0d6492f4 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/qcom,gcc-msm8953.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Global Clock & Reset Controller on MSM8953 +title: Qualcomm Global Clock & Reset Controller on MSM8937, MSM8940 and MSM8953 maintainers: - Adam Skladowski @@ -13,7 +13,7 @@ maintainers: description: | Qualcomm global clock control module provides the clocks, resets and power - domains on MSM8937 or MSM8953. + domains on MSM8937, MSM8940 or MSM8953. See also:: include/dt-bindings/clock/qcom,gcc-msm8917.h @@ -23,6 +23,7 @@ properties: compatible: enum: - qcom,gcc-msm8937 + - qcom,gcc-msm8940 - qcom,gcc-msm8953 clocks: diff --git a/include/dt-bindings/clock/qcom,gcc-msm8917.h b/include/dt-bindings/clock/qcom,gcc-msm8917.h index 4265460bfb303..c592682d5ba78 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8917.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8917.h @@ -187,6 +187,7 @@ #define MSM8937_GCC_MDSS_PCLK1_CLK 179 #define MSM8937_GCC_OXILI_AON_CLK 180 #define MSM8937_GCC_OXILI_TIMER_CLK 181 +#define MSM8940_GCC_IPA_TBU_CLK 182 /* GCC block resets */ #define GCC_CAMSS_MICRO_BCR 0 -- 2.47.3