From db267b0d1dcabd09d9064093383e38f2596345a4 Mon Sep 17 00:00:00 2001 From: Pan Li Date: Fri, 27 Jun 2025 11:35:18 +0800 Subject: [PATCH] RISC-V: Reconcile the existing test due to cost model change The cost model change will make the default cost of vx to 2, thus reconcile the asm check for this change. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c: Update the asm check due to cost model change. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c: Diito. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c: Ditto. Signed-off-by: Pan Li --- .../riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c | 2 +- .../riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c | 2 +- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c index 2261872e3de..b32907afcbb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c @@ -6,5 +6,5 @@ DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint16_t, uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ /* { dg-final { scan-assembler-times {vnsrl\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c index 4250567686a..344080cb93a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c @@ -6,5 +6,5 @@ DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint32_t, uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ /* { dg-final { scan-assembler-times {vnsrl\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c index 656aad70165..492c3168216 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c @@ -6,5 +6,5 @@ DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint8_t, uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ /* { dg-final { scan-assembler-times {vnsrl\.wi} 1 } } */ -- 2.47.2