From dcbbb1266043d1d7ca1f129d2ca58a6ce8e04cbb Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 20 May 2026 12:51:41 +0100 Subject: [PATCH] arm64: dts: renesas: r9a07g054: Add max-frequency to SDHI nodes Add the max-frequency property set to 133333333 Hz (133.33 MHz) to both SDHI0 and SDHI1 MMC controller nodes in the RZ/V2L (r9a07g054) device tree, increasing performance by ca. 33%. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260520115144.60067-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 587fab0ceb3fa..f689996b58085 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -1182,6 +1182,7 @@ <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>, <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; + max-frequency = <133333333>; resets = <&cpg R9A07G054_SDHI0_IXRST>; power-domains = <&cpg>; status = "disabled"; @@ -1198,6 +1199,7 @@ <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>, <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; + max-frequency = <133333333>; resets = <&cpg R9A07G054_SDHI1_IXRST>; power-domains = <&cpg>; status = "disabled"; -- 2.47.3