From dd9d8c61ccff0e3409b0bff702444f3d31684e9e Mon Sep 17 00:00:00 2001 From: Sridevi Arvindekar Date: Thu, 30 May 2024 15:23:15 -0400 Subject: [PATCH] drm/amd/display: Minor cleanup for DCN401 cursor related code Move pipe_ctx variables to start of the function and add a helpful comment Co-authored-by: Sridevi Arvindekar Reviewed-by: Ilya Bakoulin Acked-by: Zaeem Mohamed Signed-off-by: Sridevi Arvindekar Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 5 +++++ drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 7 +++++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index 0d58c9d439c6f..d60941495fd38 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -2800,6 +2800,11 @@ void dcn20_reset_back_end_for_pipe( if (i == dc->res_pool->pipe_count) return; +/* + * In case of a dangling plane, setting this to NULL unconditionally + * causes failures during reset hw ctx where, if stream is NULL, + * it is expected that the pipe_ctx pointers to pipes and plane are NULL. + */ pipe_ctx->stream = NULL; DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 776ec8963cabb..fe0bb6147e369 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -1099,6 +1099,8 @@ void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx) int prev_odm_offset = 0; int next_odm_width = 0; int next_odm_offset = 0; + struct pipe_ctx *next_odm_pipe = NULL; + struct pipe_ctx *prev_odm_pipe = NULL; int x_pos = pos_cpy.x; int y_pos = pos_cpy.y; @@ -1110,6 +1112,7 @@ void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx) } } + /** * DCN4 moved cursor composition after Scaler, so in HW it is in * recout space and for HW Cursor position programming need to @@ -1157,8 +1160,8 @@ void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx) * next/prev_odm_offset is to account for scaled modes that have underscan */ if (odm_combine_on) { - struct pipe_ctx *next_odm_pipe = pipe_ctx->next_odm_pipe; - struct pipe_ctx *prev_odm_pipe = pipe_ctx->prev_odm_pipe; + next_odm_pipe = pipe_ctx->next_odm_pipe; + prev_odm_pipe = pipe_ctx->prev_odm_pipe; while (next_odm_pipe != NULL) { next_odm_width += next_odm_pipe->plane_res.scl_data.recout.width; -- 2.39.5