From de3ca363811a3974e4398ecdb1db2274efd61a1c Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Wed, 4 Sep 2024 21:34:31 -0600 Subject: [PATCH] [PATCH] RISC-V: Make the setCC/REE tests robust to instruction selection These tests were checking that the output of the setCC instruction was bit flipped, but it looks like they're really designed to test that redundant sign extension elimination fires on conditionals from function inputs. Jeff just posed a patch to clean this code up with trips up on the arbitrary xori/snez instruction selection decision changing, so let's just robustify the tests. gcc/testsuite/ChangeLog: * gcc.target/riscv/sge.c: Adjust regex to match the input. * gcc.target/riscv/sgeu.c: Likewise. * gcc.target/riscv/sle.c: Likewise. * gcc.target/riscv/sleu.c: Likewise. --- gcc/testsuite/gcc.target/riscv/sge.c | 2 +- gcc/testsuite/gcc.target/riscv/sgeu.c | 2 +- gcc/testsuite/gcc.target/riscv/sle.c | 2 +- gcc/testsuite/gcc.target/riscv/sleu.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/sge.c b/gcc/testsuite/gcc.target/riscv/sge.c index 5f7e7ae82db0..70f934c4d0f1 100644 --- a/gcc/testsuite/gcc.target/riscv/sge.c +++ b/gcc/testsuite/gcc.target/riscv/sge.c @@ -8,5 +8,5 @@ sge (int x, int y) return x >= y; } -/* { dg-final { scan-assembler "\\sxori\\sa0,a0,1\n\\sret\n" } } */ +/* { dg-final { scan-assembler "slt\\sa0,a0,a1" } } */ /* { dg-final { scan-assembler-not "andi|sext\\.w" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sgeu.c b/gcc/testsuite/gcc.target/riscv/sgeu.c index 234b9aa52bd0..0ff21cfe5e01 100644 --- a/gcc/testsuite/gcc.target/riscv/sgeu.c +++ b/gcc/testsuite/gcc.target/riscv/sgeu.c @@ -8,5 +8,5 @@ sgeu (unsigned int x, unsigned int y) return x >= y; } -/* { dg-final { scan-assembler "\\sxori\\sa0,a0,1\n\\sret\n" } } */ +/* { dg-final { scan-assembler "sltu\\sa0,a0,a1" } } */ /* { dg-final { scan-assembler-not "andi|sext\\.w" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sle.c b/gcc/testsuite/gcc.target/riscv/sle.c index 3259c1915988..770840d0564f 100644 --- a/gcc/testsuite/gcc.target/riscv/sle.c +++ b/gcc/testsuite/gcc.target/riscv/sle.c @@ -8,5 +8,5 @@ sle (int x, int y) return x <= y; } -/* { dg-final { scan-assembler "\\sxori\\sa0,a0,1\n\\sret\n" } } */ +/* { dg-final { scan-assembler "sgt\\sa0,a0,a1" } } */ /* { dg-final { scan-assembler-not "andi|sext\\.w" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sleu.c b/gcc/testsuite/gcc.target/riscv/sleu.c index 301b8c32eb74..ae00ccc20678 100644 --- a/gcc/testsuite/gcc.target/riscv/sleu.c +++ b/gcc/testsuite/gcc.target/riscv/sleu.c @@ -8,5 +8,5 @@ sleu (unsigned int x, unsigned int y) return x <= y; } -/* { dg-final { scan-assembler "\\sxori\\sa0,a0,1\n\\sret\n" } } */ +/* { dg-final { scan-assembler "sgtu\\sa0,a0,a1"} } */ /* { dg-final { scan-assembler-not "andi|sext\\.w" } } */ -- 2.47.2