From deb3a4ae5dc04616dff893de074de0797594c98e Mon Sep 17 00:00:00 2001 From: Jeff Law Date: Sat, 18 Jan 2025 13:44:33 -0700 Subject: [PATCH] [RISC-V][PR target/116308] Fix generation of initial RTL for atomics While this wasn't originally marked as a regression, it almost certainly is given that older versions of GCC would have used libatomic and would not have ICE'd on this code. Basically this is another case where we directly used simplify_gen_subreg when we should have used gen_lowpart. When I fixed a similar bug a while back I noted the code in question as needing another looksie. I think at that time my brain saw the mixed modes (SI & QI) and locked up. But the QI stuff is just the shift count, not some deeper issue. So fixing is trivial. We just replace the simplify_gen_subreg with a gen_lowpart and get on with our lives. Tested on rv64 and rv32 in my tester. Waiting on pre-commit testing for final verdict. PR target/116308 gcc/ * config/riscv/riscv.cc (riscv_lshift_subword): Use gen_lowpart rather than simplify_gen_subreg. gcc/testsuite/ * gcc.target/riscv/pr116308.c: New test. --- gcc/config/riscv/riscv.cc | 4 +--- gcc/testsuite/gcc.target/riscv/pr116308.c | 9 +++++++++ 2 files changed, 10 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr116308.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 9a1db2d2b38..f5e672bb7f5 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -11963,9 +11963,7 @@ riscv_lshift_subword (machine_mode mode, rtx value, rtx shift, rtx *shifted_value) { rtx value_reg = gen_reg_rtx (SImode); - emit_move_insn (value_reg, simplify_gen_subreg (SImode, value, - mode, 0)); - + emit_move_insn (value_reg, gen_lowpart (SImode, value)); emit_move_insn (*shifted_value, gen_rtx_ASHIFT (SImode, value_reg, gen_lowpart (QImode, shift))); } diff --git a/gcc/testsuite/gcc.target/riscv/pr116308.c b/gcc/testsuite/gcc.target/riscv/pr116308.c new file mode 100644 index 00000000000..241df14bd92 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr116308.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-Ofast -march=rv64gc -mabi=lp64d" { target rv64 } } */ +/* { dg-options "-Ofast -march=rv32gc -mabi=ilp32" { target rv32 } } */ + +_Float16 test__Float16_post_inc() +{ + _Atomic _Float16 n; + return n++; +} -- 2.47.2