From ded97005b2baf6669c102d92f87b5d622136ad18 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Wed, 24 Sep 2025 18:32:54 +0200 Subject: [PATCH] target/arm: Trace vCPU reset call MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.c | 2 ++ target/arm/trace-events | 1 + 2 files changed, 3 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f8e6749ff99..30e29fd3153 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -227,6 +227,8 @@ static void arm_cpu_reset_hold(Object *obj, ResetType type) ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); CPUARMState *env = &cpu->env; + trace_arm_cpu_reset(arm_cpu_mp_affinity(cpu)); + if (acc->parent_phases.hold) { acc->parent_phases.hold(obj, type); } diff --git a/target/arm/trace-events b/target/arm/trace-events index badff2b2e46..72a2c7d0969 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -15,6 +15,7 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_irq: timer %d irqstate %d" kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova = 0x%"PRIx64" is translated into 0x%"PRIx64 # cpu.c +arm_cpu_reset(uint64_t mp_aff) "cpu %" PRIu64 arm_emulate_firmware_reset(uint64_t mp_aff, unsigned target_el) "cpu %" PRIu64 " @EL%u" # arm-powerctl.c -- 2.47.3