From e002c9e3ff9dfb5bccd601cd7674ba3908c71ba1 Mon Sep 17 00:00:00 2001 From: Sasha Levin Date: Sat, 20 Jan 2024 19:19:15 -0500 Subject: [PATCH] Fixes for 6.1 Signed-off-by: Sasha Levin --- ...-fix-information-leak-in-sec_attest_.patch | 39 ++ ...r-extended-error-log-status-when-ras.patch | 48 +++ ...it-avoid-u32-multiplication-overflow.patch | 40 ++ ...x-the-fractional-clock-divider-flags.patch | 40 ++ ...-for-error-while-searching-for-backl.patch | 54 +++ ...add-clamp-in-scarlett2_mixer_ctl_put.patch | 39 ++ ...dd-missing-error-check-to-scarlett2_.patch | 44 ++ ...sing-error-check-to-scarlett2_.patch-19676 | 42 ++ ...add-missing-error-checks-to-_ctl_get.patch | 356 ++++++++++++++++ ...llow-passing-any-output-to-line_out_.patch | 83 ++++ ...nci-always-select-config_cpu_arm926t.patch | 39 ++ ...q8064-correct-xoadc-register-address.patch | 40 ++ ...ts-qcom-sdx65-correct-spmi-node-name.patch | 39 ++ ...n-t-mix-scmi-and-non-scmi-board-comp.patch | 86 ++++ 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100644 queue-6.1/x86-lib-fix-overflow-when-counting-digits.patch create mode 100644 queue-6.1/x86-mce-inject-clear-test-status-value.patch diff --git a/queue-6.1/accel-habanalabs-fix-information-leak-in-sec_attest_.patch b/queue-6.1/accel-habanalabs-fix-information-leak-in-sec_attest_.patch new file mode 100644 index 00000000000..de7393fbe34 --- /dev/null +++ b/queue-6.1/accel-habanalabs-fix-information-leak-in-sec_attest_.patch @@ -0,0 +1,39 @@ +From c66f32c1eb34e487cf50713954e6957684ad14db Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 8 Dec 2023 21:00:59 +0800 +Subject: accel/habanalabs: fix information leak in sec_attest_info() + +From: Xingyuan Mo + +[ Upstream commit a9f07790a4b2250f0140e9a61c7f842fd9b618c7 ] + +This function may copy the pad0 field of struct hl_info_sec_attest to user +mode which has not been initialized, resulting in leakage of kernel heap +data to user mode. To prevent this, use kzalloc() to allocate and zero out +the buffer, which can also eliminate other uninitialized holes, if any. + +Fixes: 0c88760f8f5e ("habanalabs/gaudi2: add secured attestation info uapi") +Signed-off-by: Xingyuan Mo +Reviewed-by: Oded Gabbay +Signed-off-by: Oded Gabbay +Signed-off-by: Sasha Levin +--- + drivers/misc/habanalabs/common/habanalabs_ioctl.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/misc/habanalabs/common/habanalabs_ioctl.c b/drivers/misc/habanalabs/common/habanalabs_ioctl.c +index 43afe40966e5..1ea1ae34b7a7 100644 +--- a/drivers/misc/habanalabs/common/habanalabs_ioctl.c ++++ b/drivers/misc/habanalabs/common/habanalabs_ioctl.c +@@ -677,7 +677,7 @@ static int sec_attest_info(struct hl_fpriv *hpriv, struct hl_info_args *args) + if (!sec_attest_info) + return -ENOMEM; + +- info = kmalloc(sizeof(*info), GFP_KERNEL); ++ info = kzalloc(sizeof(*info), GFP_KERNEL); + if (!info) { + rc = -ENOMEM; + goto free_sec_attest_info; +-- +2.43.0 + diff --git a/queue-6.1/acpi-extlog-clear-extended-error-log-status-when-ras.patch b/queue-6.1/acpi-extlog-clear-extended-error-log-status-when-ras.patch new file mode 100644 index 00000000000..2a802c1a9fb --- /dev/null +++ b/queue-6.1/acpi-extlog-clear-extended-error-log-status-when-ras.patch @@ -0,0 +1,48 @@ +From f8f83becf9a7de35400db88a6b12b16a66d6bb36 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 12 Dec 2023 13:22:39 -0800 +Subject: ACPI: extlog: Clear Extended Error Log status when RAS_CEC handled + the error + +From: Tony Luck + +[ Upstream commit 38c872a9e96f72f2947affc0526cc05659367d3d ] + +When both CONFIG_RAS_CEC and CONFIG_ACPI_EXTLOG are enabled, Linux does +not clear the status word of the BIOS supplied error record for corrected +errors. This may prevent logging of subsequent uncorrected errors. + +Fix by clearing the status. + +Fixes: 23ba710a0864 ("x86/mce: Fix all mce notifiers to update the mce->kflags bitmask") +Reported-by: Erwin Tsaur +Signed-off-by: Tony Luck +Signed-off-by: Rafael J. Wysocki +Signed-off-by: Sasha Levin +--- + drivers/acpi/acpi_extlog.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/drivers/acpi/acpi_extlog.c b/drivers/acpi/acpi_extlog.c +index e648158368a7..088db2356998 100644 +--- a/drivers/acpi/acpi_extlog.c ++++ b/drivers/acpi/acpi_extlog.c +@@ -145,9 +145,14 @@ static int extlog_print(struct notifier_block *nb, unsigned long val, + static u32 err_seq; + + estatus = extlog_elog_entry_check(cpu, bank); +- if (estatus == NULL || (mce->kflags & MCE_HANDLED_CEC)) ++ if (!estatus) + return NOTIFY_DONE; + ++ if (mce->kflags & MCE_HANDLED_CEC) { ++ estatus->block_status = 0; ++ return NOTIFY_DONE; ++ } ++ + memcpy(elog_buf, (void *)estatus, ELOG_ENTRY_LEN); + /* clear record status to enable BIOS to update it again */ + estatus->block_status = 0; +-- +2.43.0 + diff --git a/queue-6.1/acpi-lpit-avoid-u32-multiplication-overflow.patch b/queue-6.1/acpi-lpit-avoid-u32-multiplication-overflow.patch new file mode 100644 index 00000000000..eae4c93bd2b --- /dev/null +++ b/queue-6.1/acpi-lpit-avoid-u32-multiplication-overflow.patch @@ -0,0 +1,40 @@ +From bde0e973b6481f25907d34033be2f0b975eb8794 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 9 Nov 2023 21:08:59 +0300 +Subject: ACPI: LPIT: Avoid u32 multiplication overflow + +From: Nikita Kiryushin + +[ Upstream commit 56d2eeda87995245300836ee4dbd13b002311782 ] + +In lpit_update_residency() there is a possibility of overflow +in multiplication, if tsc_khz is large enough (> UINT_MAX/1000). + +Change multiplication to mul_u32_u32(). + +Found by Linux Verification Center (linuxtesting.org) with SVACE. + +Fixes: eeb2d80d502a ("ACPI / LPIT: Add Low Power Idle Table (LPIT) support") +Signed-off-by: Nikita Kiryushin +Signed-off-by: Rafael J. Wysocki +Signed-off-by: Sasha Levin +--- + drivers/acpi/acpi_lpit.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/acpi/acpi_lpit.c b/drivers/acpi/acpi_lpit.c +index 50540d4d4948..2c015ecf7185 100644 +--- a/drivers/acpi/acpi_lpit.c ++++ b/drivers/acpi/acpi_lpit.c +@@ -98,7 +98,7 @@ static void lpit_update_residency(struct lpit_residency_info *info, + struct acpi_lpit_native *lpit_native) + { + info->frequency = lpit_native->counter_frequency ? +- lpit_native->counter_frequency : tsc_khz * 1000; ++ lpit_native->counter_frequency : mul_u32_u32(tsc_khz, 1000U); + if (!info->frequency) + info->frequency = 1; + +-- +2.43.0 + diff --git a/queue-6.1/acpi-lpss-fix-the-fractional-clock-divider-flags.patch b/queue-6.1/acpi-lpss-fix-the-fractional-clock-divider-flags.patch new file mode 100644 index 00000000000..fe91c47e6f7 --- /dev/null +++ b/queue-6.1/acpi-lpss-fix-the-fractional-clock-divider-flags.patch @@ -0,0 +1,40 @@ +From 49e1257b2dddb3b6d28324fcf6dfede98e2bd297 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 11 Dec 2023 13:14:29 +0200 +Subject: ACPI: LPSS: Fix the fractional clock divider flags + +From: Andy Shevchenko + +[ Upstream commit 3ebccf1d1ca74bbb78e6f8c38d1d172e468d91f8 ] + +The conversion to CLK_FRAC_DIVIDER_POWER_OF_TWO_PS uses wrong flags +in the parameters and hence miscalculates the values in the clock +divider. Fix this by applying the flag to the proper parameter. + +Fixes: 82f53f9ee577 ("clk: fractional-divider: Introduce POWER_OF_TWO_PS flag") +Reported-by: Alex Vinarskis +Signed-off-by: Andy Shevchenko +Signed-off-by: Rafael J. Wysocki +Signed-off-by: Sasha Levin +--- + drivers/acpi/acpi_lpss.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c +index f08ffa75f4a7..8b44743945c8 100644 +--- a/drivers/acpi/acpi_lpss.c ++++ b/drivers/acpi/acpi_lpss.c +@@ -450,8 +450,9 @@ static int register_device_clock(struct acpi_device *adev, + if (!clk_name) + return -ENOMEM; + clk = clk_register_fractional_divider(NULL, clk_name, parent, ++ 0, prv_base, 1, 15, 16, 15, + CLK_FRAC_DIVIDER_POWER_OF_TWO_PS, +- prv_base, 1, 15, 16, 15, 0, NULL); ++ NULL); + parent = clk_name; + + clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); +-- +2.43.0 + diff --git a/queue-6.1/acpi-video-check-for-error-while-searching-for-backl.patch b/queue-6.1/acpi-video-check-for-error-while-searching-for-backl.patch new file mode 100644 index 00000000000..7a81d050654 --- /dev/null +++ b/queue-6.1/acpi-video-check-for-error-while-searching-for-backl.patch @@ -0,0 +1,54 @@ +From 203673a86a0389221cbea7dfffe45d9d867c1475 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 9 Nov 2023 16:49:25 +0300 +Subject: ACPI: video: check for error while searching for backlight device + parent + +From: Nikita Kiryushin + +[ Upstream commit ccd45faf4973746c4f30ea41eec864e5cf191099 ] + +If acpi_get_parent() called in acpi_video_dev_register_backlight() +fails, for example, because acpi_ut_acquire_mutex() fails inside +acpi_get_parent), this can lead to incorrect (uninitialized) +acpi_parent handle being passed to acpi_get_pci_dev() for detecting +the parent pci device. + +Check acpi_get_parent() result and set parent device only in case of success. + +Found by Linux Verification Center (linuxtesting.org) with SVACE. + +Fixes: 9661e92c10a9 ("acpi: tie ACPI backlight devices to PCI devices if possible") +Signed-off-by: Nikita Kiryushin +Signed-off-by: Rafael J. Wysocki +Signed-off-by: Sasha Levin +--- + drivers/acpi/acpi_video.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/drivers/acpi/acpi_video.c b/drivers/acpi/acpi_video.c +index ed318485eb19..f7852fb75ab3 100644 +--- a/drivers/acpi/acpi_video.c ++++ b/drivers/acpi/acpi_video.c +@@ -1726,12 +1726,12 @@ static void acpi_video_dev_register_backlight(struct acpi_video_device *device) + return; + count++; + +- acpi_get_parent(device->dev->handle, &acpi_parent); +- +- pdev = acpi_get_pci_dev(acpi_parent); +- if (pdev) { +- parent = &pdev->dev; +- pci_dev_put(pdev); ++ if (ACPI_SUCCESS(acpi_get_parent(device->dev->handle, &acpi_parent))) { ++ pdev = acpi_get_pci_dev(acpi_parent); ++ if (pdev) { ++ parent = &pdev->dev; ++ pci_dev_put(pdev); ++ } + } + + memset(&props, 0, sizeof(struct backlight_properties)); +-- +2.43.0 + diff --git a/queue-6.1/alsa-scarlett2-add-clamp-in-scarlett2_mixer_ctl_put.patch b/queue-6.1/alsa-scarlett2-add-clamp-in-scarlett2_mixer_ctl_put.patch new file mode 100644 index 00000000000..7c95f247e0f --- /dev/null +++ b/queue-6.1/alsa-scarlett2-add-clamp-in-scarlett2_mixer_ctl_put.patch @@ -0,0 +1,39 @@ +From 38182237da551d54642f340665cc917571180d29 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 20 Dec 2023 04:07:52 +1030 +Subject: ALSA: scarlett2: Add clamp() in scarlett2_mixer_ctl_put() + +From: Geoffrey D. Bennett + +[ Upstream commit 04f8f053252b86c7583895c962d66747ecdc61b7 ] + +Ensure the value passed to scarlett2_mixer_ctl_put() is between 0 and +SCARLETT2_MIXER_MAX_VALUE so we don't attempt to access outside +scarlett2_mixer_values[]. + +Signed-off-by: Geoffrey D. Bennett +Fixes: 9e4d5c1be21f ("ALSA: usb-audio: Scarlett Gen 2 mixer interface") +Link: https://lore.kernel.org/r/3b19fb3da641b587749b85fe1daa1b4e696c0c1b.1703001053.git.g@b4.vu +Signed-off-by: Takashi Iwai +Signed-off-by: Sasha Levin +--- + sound/usb/mixer_scarlett_gen2.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/sound/usb/mixer_scarlett_gen2.c b/sound/usb/mixer_scarlett_gen2.c +index eedac43eee7d..1bcb05c73e0a 100644 +--- a/sound/usb/mixer_scarlett_gen2.c ++++ b/sound/usb/mixer_scarlett_gen2.c +@@ -3361,7 +3361,8 @@ static int scarlett2_mixer_ctl_put(struct snd_kcontrol *kctl, + mutex_lock(&private->data_mutex); + + oval = private->mix[index]; +- val = ucontrol->value.integer.value[0]; ++ val = clamp(ucontrol->value.integer.value[0], ++ 0L, (long)SCARLETT2_MIXER_MAX_VALUE); + num_mixer_in = port_count[SCARLETT2_PORT_TYPE_MIX][SCARLETT2_PORT_OUT]; + mix_num = index / num_mixer_in; + +-- +2.43.0 + diff --git a/queue-6.1/alsa-scarlett2-add-missing-error-check-to-scarlett2_.patch b/queue-6.1/alsa-scarlett2-add-missing-error-check-to-scarlett2_.patch new file mode 100644 index 00000000000..9a5883d4a7c --- /dev/null +++ b/queue-6.1/alsa-scarlett2-add-missing-error-check-to-scarlett2_.patch @@ -0,0 +1,44 @@ +From d65271161757590e7f5a69cc907f2c30ad594144 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 20 Dec 2023 04:07:00 +1030 +Subject: ALSA: scarlett2: Add missing error check to scarlett2_config_save() + +From: Geoffrey D. Bennett + +[ Upstream commit 5f6ff6931a1c0065a55448108940371e1ac8075f ] + +scarlett2_config_save() was ignoring the return value from +scarlett2_usb(). As this function is not called from user-space we +can't return the error, so call usb_audio_err() instead. + +Signed-off-by: Geoffrey D. Bennett +Fixes: 9e4d5c1be21f ("ALSA: usb-audio: Scarlett Gen 2 mixer interface") +Link: https://lore.kernel.org/r/bf0a15332d852d7825fa6da87d2a0d9c0b702053.1703001053.git.g@b4.vu +Signed-off-by: Takashi Iwai +Signed-off-by: Sasha Levin +--- + sound/usb/mixer_scarlett_gen2.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +diff --git a/sound/usb/mixer_scarlett_gen2.c b/sound/usb/mixer_scarlett_gen2.c +index 9d11bb08667e..3da0d3167ebf 100644 +--- a/sound/usb/mixer_scarlett_gen2.c ++++ b/sound/usb/mixer_scarlett_gen2.c +@@ -1337,9 +1337,11 @@ static void scarlett2_config_save(struct usb_mixer_interface *mixer) + { + __le32 req = cpu_to_le32(SCARLETT2_USB_CONFIG_SAVE); + +- scarlett2_usb(mixer, SCARLETT2_USB_DATA_CMD, +- &req, sizeof(u32), +- NULL, 0); ++ int err = scarlett2_usb(mixer, SCARLETT2_USB_DATA_CMD, ++ &req, sizeof(u32), ++ NULL, 0); ++ if (err < 0) ++ usb_audio_err(mixer->chip, "config save failed: %d\n", err); + } + + /* Delayed work to save config */ +-- +2.43.0 + diff --git a/queue-6.1/alsa-scarlett2-add-missing-error-check-to-scarlett2_.patch-19676 b/queue-6.1/alsa-scarlett2-add-missing-error-check-to-scarlett2_.patch-19676 new file mode 100644 index 00000000000..e548e01f485 --- /dev/null +++ b/queue-6.1/alsa-scarlett2-add-missing-error-check-to-scarlett2_.patch-19676 @@ -0,0 +1,42 @@ +From 8c9c83bf9cbbc4014870bedf3ecb2238f461bf45 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 20 Dec 2023 04:07:21 +1030 +Subject: ALSA: scarlett2: Add missing error check to + scarlett2_usb_set_config() + +From: Geoffrey D. Bennett + +[ Upstream commit ca459dfa7d4ed9098fcf13e410963be6ae9b6bf3 ] + +scarlett2_usb_set_config() calls scarlett2_usb_get() but was not +checking the result. Return the error if it fails rather than +continuing with an invalid value. + +Signed-off-by: Geoffrey D. Bennett +Fixes: 9e15fae6c51a ("ALSA: usb-audio: scarlett2: Allow bit-level access to config") +Link: https://lore.kernel.org/r/def110c5c31dbdf0a7414d258838a0a31c0fab67.1703001053.git.g@b4.vu +Signed-off-by: Takashi Iwai +Signed-off-by: Sasha Levin +--- + sound/usb/mixer_scarlett_gen2.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/sound/usb/mixer_scarlett_gen2.c b/sound/usb/mixer_scarlett_gen2.c +index 3da0d3167ebf..94704581865b 100644 +--- a/sound/usb/mixer_scarlett_gen2.c ++++ b/sound/usb/mixer_scarlett_gen2.c +@@ -1390,7 +1390,10 @@ static int scarlett2_usb_set_config( + size = 1; + offset = config_item->offset; + +- scarlett2_usb_get(mixer, offset, &tmp, 1); ++ err = scarlett2_usb_get(mixer, offset, &tmp, 1); ++ if (err < 0) ++ return err; ++ + if (value) + tmp |= (1 << index); + else +-- +2.43.0 + diff --git a/queue-6.1/alsa-scarlett2-add-missing-error-checks-to-_ctl_get.patch b/queue-6.1/alsa-scarlett2-add-missing-error-checks-to-_ctl_get.patch new file mode 100644 index 00000000000..86a35ab6979 --- /dev/null +++ b/queue-6.1/alsa-scarlett2-add-missing-error-checks-to-_ctl_get.patch @@ -0,0 +1,356 @@ +From 70910fa5e8280ba21a3d8fcdf1d27206b1197a0d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 20 Dec 2023 04:07:37 +1030 +Subject: ALSA: scarlett2: Add missing error checks to *_ctl_get() + +From: Geoffrey D. Bennett + +[ Upstream commit 50603a67daef161c78c814580d57f7f0be57167e ] + +The *_ctl_get() functions which call scarlett2_update_*() were not +checking the return value. Fix to check the return value and pass to +the caller. + +Signed-off-by: Geoffrey D. Bennett +Fixes: 9e4d5c1be21f ("ALSA: usb-audio: Scarlett Gen 2 mixer interface") +Link: https://lore.kernel.org/r/32a5fdc83b05fa74e0fcdd672fbf71d75c5f0a6d.1703001053.git.g@b4.vu +Signed-off-by: Takashi Iwai +Signed-off-by: Sasha Levin +--- + sound/usb/mixer_scarlett_gen2.c | 182 +++++++++++++++++++++++--------- + 1 file changed, 130 insertions(+), 52 deletions(-) + +diff --git a/sound/usb/mixer_scarlett_gen2.c b/sound/usb/mixer_scarlett_gen2.c +index f8a2ba479b7c..eedac43eee7d 100644 +--- a/sound/usb/mixer_scarlett_gen2.c ++++ b/sound/usb/mixer_scarlett_gen2.c +@@ -1798,14 +1798,20 @@ static int scarlett2_sync_ctl_get(struct snd_kcontrol *kctl, + struct usb_mixer_elem_info *elem = kctl->private_data; + struct usb_mixer_interface *mixer = elem->head.mixer; + struct scarlett2_data *private = mixer->private_data; ++ int err = 0; + + mutex_lock(&private->data_mutex); +- if (private->sync_updated) +- scarlett2_update_sync(mixer); ++ ++ if (private->sync_updated) { ++ err = scarlett2_update_sync(mixer); ++ if (err < 0) ++ goto unlock; ++ } + ucontrol->value.enumerated.item[0] = private->sync; +- mutex_unlock(&private->data_mutex); + +- return 0; ++unlock: ++ mutex_unlock(&private->data_mutex); ++ return err; + } + + static const struct snd_kcontrol_new scarlett2_sync_ctl = { +@@ -1888,14 +1894,20 @@ static int scarlett2_master_volume_ctl_get(struct snd_kcontrol *kctl, + struct usb_mixer_elem_info *elem = kctl->private_data; + struct usb_mixer_interface *mixer = elem->head.mixer; + struct scarlett2_data *private = mixer->private_data; ++ int err = 0; + + mutex_lock(&private->data_mutex); +- if (private->vol_updated) +- scarlett2_update_volumes(mixer); +- mutex_unlock(&private->data_mutex); + ++ if (private->vol_updated) { ++ err = scarlett2_update_volumes(mixer); ++ if (err < 0) ++ goto unlock; ++ } + ucontrol->value.integer.value[0] = private->master_vol; +- return 0; ++ ++unlock: ++ mutex_unlock(&private->data_mutex); ++ return err; + } + + static int line_out_remap(struct scarlett2_data *private, int index) +@@ -1921,14 +1933,20 @@ static int scarlett2_volume_ctl_get(struct snd_kcontrol *kctl, + struct usb_mixer_interface *mixer = elem->head.mixer; + struct scarlett2_data *private = mixer->private_data; + int index = line_out_remap(private, elem->control); ++ int err = 0; + + mutex_lock(&private->data_mutex); +- if (private->vol_updated) +- scarlett2_update_volumes(mixer); +- mutex_unlock(&private->data_mutex); + ++ if (private->vol_updated) { ++ err = scarlett2_update_volumes(mixer); ++ if (err < 0) ++ goto unlock; ++ } + ucontrol->value.integer.value[0] = private->vol[index]; +- return 0; ++ ++unlock: ++ mutex_unlock(&private->data_mutex); ++ return err; + } + + static int scarlett2_volume_ctl_put(struct snd_kcontrol *kctl, +@@ -1995,14 +2013,20 @@ static int scarlett2_mute_ctl_get(struct snd_kcontrol *kctl, + struct usb_mixer_interface *mixer = elem->head.mixer; + struct scarlett2_data *private = mixer->private_data; + int index = line_out_remap(private, elem->control); ++ int err = 0; + + mutex_lock(&private->data_mutex); +- if (private->vol_updated) +- scarlett2_update_volumes(mixer); +- mutex_unlock(&private->data_mutex); + ++ if (private->vol_updated) { ++ err = scarlett2_update_volumes(mixer); ++ if (err < 0) ++ goto unlock; ++ } + ucontrol->value.integer.value[0] = private->mute_switch[index]; +- return 0; ++ ++unlock: ++ mutex_unlock(&private->data_mutex); ++ return err; + } + + static int scarlett2_mute_ctl_put(struct snd_kcontrol *kctl, +@@ -2248,14 +2272,20 @@ static int scarlett2_level_enum_ctl_get(struct snd_kcontrol *kctl, + const struct scarlett2_device_info *info = private->info; + + int index = elem->control + info->level_input_first; ++ int err = 0; + + mutex_lock(&private->data_mutex); +- if (private->input_other_updated) +- scarlett2_update_input_other(mixer); ++ ++ if (private->input_other_updated) { ++ err = scarlett2_update_input_other(mixer); ++ if (err < 0) ++ goto unlock; ++ } + ucontrol->value.enumerated.item[0] = private->level_switch[index]; +- mutex_unlock(&private->data_mutex); + +- return 0; ++unlock: ++ mutex_unlock(&private->data_mutex); ++ return err; + } + + static int scarlett2_level_enum_ctl_put(struct snd_kcontrol *kctl, +@@ -2306,15 +2336,21 @@ static int scarlett2_pad_ctl_get(struct snd_kcontrol *kctl, + struct usb_mixer_elem_info *elem = kctl->private_data; + struct usb_mixer_interface *mixer = elem->head.mixer; + struct scarlett2_data *private = mixer->private_data; ++ int err = 0; + + mutex_lock(&private->data_mutex); +- if (private->input_other_updated) +- scarlett2_update_input_other(mixer); ++ ++ if (private->input_other_updated) { ++ err = scarlett2_update_input_other(mixer); ++ if (err < 0) ++ goto unlock; ++ } + ucontrol->value.integer.value[0] = + private->pad_switch[elem->control]; +- mutex_unlock(&private->data_mutex); + +- return 0; ++unlock: ++ mutex_unlock(&private->data_mutex); ++ return err; + } + + static int scarlett2_pad_ctl_put(struct snd_kcontrol *kctl, +@@ -2364,14 +2400,20 @@ static int scarlett2_air_ctl_get(struct snd_kcontrol *kctl, + struct usb_mixer_elem_info *elem = kctl->private_data; + struct usb_mixer_interface *mixer = elem->head.mixer; + struct scarlett2_data *private = mixer->private_data; ++ int err = 0; + + mutex_lock(&private->data_mutex); +- if (private->input_other_updated) +- scarlett2_update_input_other(mixer); ++ ++ if (private->input_other_updated) { ++ err = scarlett2_update_input_other(mixer); ++ if (err < 0) ++ goto unlock; ++ } + ucontrol->value.integer.value[0] = private->air_switch[elem->control]; +- mutex_unlock(&private->data_mutex); + +- return 0; ++unlock: ++ mutex_unlock(&private->data_mutex); ++ return err; + } + + static int scarlett2_air_ctl_put(struct snd_kcontrol *kctl, +@@ -2421,15 +2463,21 @@ static int scarlett2_phantom_ctl_get(struct snd_kcontrol *kctl, + struct usb_mixer_elem_info *elem = kctl->private_data; + struct usb_mixer_interface *mixer = elem->head.mixer; + struct scarlett2_data *private = mixer->private_data; ++ int err = 0; + + mutex_lock(&private->data_mutex); +- if (private->input_other_updated) +- scarlett2_update_input_other(mixer); ++ ++ if (private->input_other_updated) { ++ err = scarlett2_update_input_other(mixer); ++ if (err < 0) ++ goto unlock; ++ } + ucontrol->value.integer.value[0] = + private->phantom_switch[elem->control]; +- mutex_unlock(&private->data_mutex); + +- return 0; ++unlock: ++ mutex_unlock(&private->data_mutex); ++ return err; + } + + static int scarlett2_phantom_ctl_put(struct snd_kcontrol *kctl, +@@ -2601,14 +2649,20 @@ static int scarlett2_direct_monitor_ctl_get( + struct usb_mixer_elem_info *elem = kctl->private_data; + struct usb_mixer_interface *mixer = elem->head.mixer; + struct scarlett2_data *private = elem->head.mixer->private_data; ++ int err = 0; + + mutex_lock(&private->data_mutex); +- if (private->monitor_other_updated) +- scarlett2_update_monitor_other(mixer); ++ ++ if (private->monitor_other_updated) { ++ err = scarlett2_update_monitor_other(mixer); ++ if (err < 0) ++ goto unlock; ++ } + ucontrol->value.enumerated.item[0] = private->direct_monitor_switch; +- mutex_unlock(&private->data_mutex); + +- return 0; ++unlock: ++ mutex_unlock(&private->data_mutex); ++ return err; + } + + static int scarlett2_direct_monitor_ctl_put( +@@ -2708,14 +2762,20 @@ static int scarlett2_speaker_switch_enum_ctl_get( + struct usb_mixer_elem_info *elem = kctl->private_data; + struct usb_mixer_interface *mixer = elem->head.mixer; + struct scarlett2_data *private = mixer->private_data; ++ int err = 0; + + mutex_lock(&private->data_mutex); +- if (private->monitor_other_updated) +- scarlett2_update_monitor_other(mixer); ++ ++ if (private->monitor_other_updated) { ++ err = scarlett2_update_monitor_other(mixer); ++ if (err < 0) ++ goto unlock; ++ } + ucontrol->value.enumerated.item[0] = private->speaker_switching_switch; +- mutex_unlock(&private->data_mutex); + +- return 0; ++unlock: ++ mutex_unlock(&private->data_mutex); ++ return err; + } + + /* when speaker switching gets enabled, switch the main/alt speakers +@@ -2863,14 +2923,20 @@ static int scarlett2_talkback_enum_ctl_get( + struct usb_mixer_elem_info *elem = kctl->private_data; + struct usb_mixer_interface *mixer = elem->head.mixer; + struct scarlett2_data *private = mixer->private_data; ++ int err = 0; + + mutex_lock(&private->data_mutex); +- if (private->monitor_other_updated) +- scarlett2_update_monitor_other(mixer); ++ ++ if (private->monitor_other_updated) { ++ err = scarlett2_update_monitor_other(mixer); ++ if (err < 0) ++ goto unlock; ++ } + ucontrol->value.enumerated.item[0] = private->talkback_switch; +- mutex_unlock(&private->data_mutex); + +- return 0; ++unlock: ++ mutex_unlock(&private->data_mutex); ++ return err; + } + + static int scarlett2_talkback_enum_ctl_put( +@@ -3018,14 +3084,20 @@ static int scarlett2_dim_mute_ctl_get(struct snd_kcontrol *kctl, + struct usb_mixer_elem_info *elem = kctl->private_data; + struct usb_mixer_interface *mixer = elem->head.mixer; + struct scarlett2_data *private = mixer->private_data; ++ int err = 0; + + mutex_lock(&private->data_mutex); +- if (private->vol_updated) +- scarlett2_update_volumes(mixer); +- mutex_unlock(&private->data_mutex); + ++ if (private->vol_updated) { ++ err = scarlett2_update_volumes(mixer); ++ if (err < 0) ++ goto unlock; ++ } + ucontrol->value.integer.value[0] = private->dim_mute[elem->control]; +- return 0; ++ ++unlock: ++ mutex_unlock(&private->data_mutex); ++ return err; + } + + static int scarlett2_dim_mute_ctl_put(struct snd_kcontrol *kctl, +@@ -3396,14 +3468,20 @@ static int scarlett2_mux_src_enum_ctl_get(struct snd_kcontrol *kctl, + struct usb_mixer_interface *mixer = elem->head.mixer; + struct scarlett2_data *private = mixer->private_data; + int index = line_out_remap(private, elem->control); ++ int err = 0; + + mutex_lock(&private->data_mutex); +- if (private->mux_updated) +- scarlett2_usb_get_mux(mixer); ++ ++ if (private->mux_updated) { ++ err = scarlett2_usb_get_mux(mixer); ++ if (err < 0) ++ goto unlock; ++ } + ucontrol->value.enumerated.item[0] = private->mux[index]; +- mutex_unlock(&private->data_mutex); + +- return 0; ++unlock: ++ mutex_unlock(&private->data_mutex); ++ return err; + } + + static int scarlett2_mux_src_enum_ctl_put(struct snd_kcontrol *kctl, +-- +2.43.0 + diff --git a/queue-6.1/alsa-scarlett2-allow-passing-any-output-to-line_out_.patch b/queue-6.1/alsa-scarlett2-allow-passing-any-output-to-line_out_.patch new file mode 100644 index 00000000000..817e9daf78e --- /dev/null +++ b/queue-6.1/alsa-scarlett2-allow-passing-any-output-to-line_out_.patch @@ -0,0 +1,83 @@ +From 454e0b637e40f747c3d3739570d8e661c3613faa Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 27 Oct 2023 04:36:16 +1030 +Subject: ALSA: scarlett2: Allow passing any output to line_out_remap() + +From: Geoffrey D. Bennett + +[ Upstream commit 2190b9aea4eb92ccf3176e35c17c959e40f1a81b ] + +Line outputs 3 & 4 on the Gen 3 18i8 are internally the analogue 7 and +8 outputs, and this renumbering is hidden from the user by +line_out_remap(). By allowing higher values (representing non-analogue +outputs) to be passed to line_out_remap(), repeated code from +scarlett2_mux_src_enum_ctl_get() and scarlett2_mux_src_enum_ctl_put() +can be removed. + +Signed-off-by: Geoffrey D. Bennett +Link: https://lore.kernel.org/r/3b70267931f5994628ab27306c73cddd17b93c8f.1698342632.git.g@b4.vu +Signed-off-by: Takashi Iwai +Stable-dep-of: 50603a67daef ("ALSA: scarlett2: Add missing error checks to *_ctl_get()") +Signed-off-by: Sasha Levin +--- + sound/usb/mixer_scarlett_gen2.c | 25 +++++++++---------------- + 1 file changed, 9 insertions(+), 16 deletions(-) + +diff --git a/sound/usb/mixer_scarlett_gen2.c b/sound/usb/mixer_scarlett_gen2.c +index 94704581865b..f8a2ba479b7c 100644 +--- a/sound/usb/mixer_scarlett_gen2.c ++++ b/sound/usb/mixer_scarlett_gen2.c +@@ -1901,9 +1901,16 @@ static int scarlett2_master_volume_ctl_get(struct snd_kcontrol *kctl, + static int line_out_remap(struct scarlett2_data *private, int index) + { + const struct scarlett2_device_info *info = private->info; ++ const int (*port_count)[SCARLETT2_PORT_DIRNS] = info->port_count; ++ int line_out_count = ++ port_count[SCARLETT2_PORT_TYPE_ANALOGUE][SCARLETT2_PORT_OUT]; + + if (!info->line_out_remap_enable) + return index; ++ ++ if (index >= line_out_count) ++ return index; ++ + return info->line_out_remap[index]; + } + +@@ -3388,14 +3395,7 @@ static int scarlett2_mux_src_enum_ctl_get(struct snd_kcontrol *kctl, + struct usb_mixer_elem_info *elem = kctl->private_data; + struct usb_mixer_interface *mixer = elem->head.mixer; + struct scarlett2_data *private = mixer->private_data; +- const struct scarlett2_device_info *info = private->info; +- const int (*port_count)[SCARLETT2_PORT_DIRNS] = info->port_count; +- int line_out_count = +- port_count[SCARLETT2_PORT_TYPE_ANALOGUE][SCARLETT2_PORT_OUT]; +- int index = elem->control; +- +- if (index < line_out_count) +- index = line_out_remap(private, index); ++ int index = line_out_remap(private, elem->control); + + mutex_lock(&private->data_mutex); + if (private->mux_updated) +@@ -3412,16 +3412,9 @@ static int scarlett2_mux_src_enum_ctl_put(struct snd_kcontrol *kctl, + struct usb_mixer_elem_info *elem = kctl->private_data; + struct usb_mixer_interface *mixer = elem->head.mixer; + struct scarlett2_data *private = mixer->private_data; +- const struct scarlett2_device_info *info = private->info; +- const int (*port_count)[SCARLETT2_PORT_DIRNS] = info->port_count; +- int line_out_count = +- port_count[SCARLETT2_PORT_TYPE_ANALOGUE][SCARLETT2_PORT_OUT]; +- int index = elem->control; ++ int index = line_out_remap(private, elem->control); + int oval, val, err = 0; + +- if (index < line_out_count) +- index = line_out_remap(private, index); +- + mutex_lock(&private->data_mutex); + + oval = private->mux[index]; +-- +2.43.0 + diff --git a/queue-6.1/arm-davinci-always-select-config_cpu_arm926t.patch b/queue-6.1/arm-davinci-always-select-config_cpu_arm926t.patch new file mode 100644 index 00000000000..c7bc7231e84 --- /dev/null +++ b/queue-6.1/arm-davinci-always-select-config_cpu_arm926t.patch @@ -0,0 +1,39 @@ +From a6416d234589c6129d26de7fa77b5924d84a36e0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 8 Jan 2024 12:00:36 +0100 +Subject: ARM: davinci: always select CONFIG_CPU_ARM926T + +From: Arnd Bergmann + +[ Upstream commit 40974ee421b4d1fc74ac733d86899ce1b83d8f65 ] + +The select was lost by accident during the multiplatform conversion. +Any davinci-only + +arm-linux-gnueabi-ld: arch/arm/mach-davinci/sleep.o: in function `CACHE_FLUSH': +(.text+0x168): undefined reference to `arm926_flush_kern_cache_all' + +Fixes: f962396ce292 ("ARM: davinci: support multiplatform build for ARM v5") +Acked-by: Bartosz Golaszewski +Link: https://lore.kernel.org/r/20240108110055.1531153-1-arnd@kernel.org +Signed-off-by: Arnd Bergmann +Signed-off-by: Sasha Levin +--- + arch/arm/mach-davinci/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig +index c8cbd9a30791..0b54ca56555b 100644 +--- a/arch/arm/mach-davinci/Kconfig ++++ b/arch/arm/mach-davinci/Kconfig +@@ -4,6 +4,7 @@ menuconfig ARCH_DAVINCI + bool "TI DaVinci" + depends on ARCH_MULTI_V5 + depends on CPU_LITTLE_ENDIAN ++ select CPU_ARM926T + select DAVINCI_TIMER + select ZONE_DMA + select PM_GENERIC_DOMAINS if PM +-- +2.43.0 + diff --git a/queue-6.1/arm-dts-qcom-apq8064-correct-xoadc-register-address.patch b/queue-6.1/arm-dts-qcom-apq8064-correct-xoadc-register-address.patch new file mode 100644 index 00000000000..e9c819fb8bd --- /dev/null +++ b/queue-6.1/arm-dts-qcom-apq8064-correct-xoadc-register-address.patch @@ -0,0 +1,40 @@ +From cc9320c0c411510781b0e6c3cdad144f22dbe740 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 28 Sep 2023 14:02:35 +0300 +Subject: ARM: dts: qcom: apq8064: correct XOADC register address + +From: Dmitry Baryshkov + +[ Upstream commit 554557542e709e190eff8a598f0cde02647d533a ] + +The XOADC is present at the address 0x197 rather than just 197. It +doesn't change a lot (since the driver hardcodes all register +addresses), but the DT should present correct address anyway. + +Fixes: c4b70883ee33 ("ARM: dts: add XOADC and IIO HWMON to APQ8064") +Reviewed-by: Konrad Dybcio +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20230928110309.1212221-3-dmitry.baryshkov@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/qcom-apq8064.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi +index 4b57e9f5bc64..2b3927a829b7 100644 +--- a/arch/arm/boot/dts/qcom-apq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-apq8064.dtsi +@@ -750,7 +750,7 @@ pwrkey@1c { + + xoadc: xoadc@197 { + compatible = "qcom,pm8921-adc"; +- reg = <197>; ++ reg = <0x197>; + interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>; + #address-cells = <2>; + #size-cells = <0>; +-- +2.43.0 + diff --git a/queue-6.1/arm-dts-qcom-sdx65-correct-spmi-node-name.patch b/queue-6.1/arm-dts-qcom-sdx65-correct-spmi-node-name.patch new file mode 100644 index 00000000000..82a9434c882 --- /dev/null +++ b/queue-6.1/arm-dts-qcom-sdx65-correct-spmi-node-name.patch @@ -0,0 +1,39 @@ +From 451729b04862a8501d9cbff3687ed1b5f98b1006 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 24 Sep 2023 20:31:03 +0200 +Subject: ARM: dts: qcom: sdx65: correct SPMI node name + +From: Krzysztof Kozlowski + +[ Upstream commit a900ad783f507cb396e402827052e70c0c565ae9 ] + +Node names should not have vendor prefixes: + + qcom-sdx65-mtp.dtb: qcom,spmi@c440000: $nodename:0: 'qcom,spmi@c440000' does not match '^spmi@.* + +Reviewed-by: Konrad Dybcio +Signed-off-by: Krzysztof Kozlowski +Reviewed-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20230924183103.49487-3-krzysztof.kozlowski@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/qcom-sdx65.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi +index ecb9171e4da5..ebb78b489e63 100644 +--- a/arch/arm/boot/dts/qcom-sdx65.dtsi ++++ b/arch/arm/boot/dts/qcom-sdx65.dtsi +@@ -401,7 +401,7 @@ restart@c264000 { + reg = <0x0c264000 0x1000>; + }; + +- spmi_bus: qcom,spmi@c440000 { ++ spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0xd00>, + <0xc600000 0x2000000>, +-- +2.43.0 + diff --git a/queue-6.1/arm-dts-stm32-don-t-mix-scmi-and-non-scmi-board-comp.patch b/queue-6.1/arm-dts-stm32-don-t-mix-scmi-and-non-scmi-board-comp.patch new file mode 100644 index 00000000000..9302c7b1406 --- /dev/null +++ b/queue-6.1/arm-dts-stm32-don-t-mix-scmi-and-non-scmi-board-comp.patch @@ -0,0 +1,86 @@ +From 49a0e1c9f5f75c70908b65a30b2e9834c120a5a6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 22 Nov 2023 19:52:34 +0100 +Subject: ARM: dts: stm32: don't mix SCMI and non-SCMI board compatibles + +From: Ahmad Fatoum + +[ Upstream commit bfc3c6743de0ecb169026c36cbdbc0d12d22a528 ] + +The binding erroneously decreed that the SCMI variants of the ST +evaluation kits are compatible with the non-SCMI variants. + +This is not correct, as a kernel or bootloader compatible with the non-SCMI +variant is not necessarily able to function, when direct access +to resources is replaced by having to talk SCMI to the secure monitor. + +The binding has been adjusted to reflect thus, so synchronize the device +trees now. + +Fixes: 5b7e58313a77 ("ARM: dts: stm32: Add SCMI version of STM32 boards (DK1/DK2/ED1/EV1)") +Signed-off-by: Ahmad Fatoum +Signed-off-by: Alexandre Torgue +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts | 2 +- + arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts | 2 +- + arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts | 2 +- + arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts | 3 +-- + 4 files changed, 4 insertions(+), 5 deletions(-) + +diff --git a/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts +index e539cc80bef8..942a6ca38d97 100644 +--- a/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts ++++ b/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts +@@ -11,7 +11,7 @@ + + / { + model = "STMicroelectronics STM32MP157A-DK1 SCMI Discovery Board"; +- compatible = "st,stm32mp157a-dk1-scmi", "st,stm32mp157a-dk1", "st,stm32mp157"; ++ compatible = "st,stm32mp157a-dk1-scmi", "st,stm32mp157"; + + reserved-memory { + optee@de000000 { +diff --git a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts +index 97e4f94b0a24..99c4ff1f5c21 100644 +--- a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts ++++ b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts +@@ -11,7 +11,7 @@ + + / { + model = "STMicroelectronics STM32MP157C-DK2 SCMI Discovery Board"; +- compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157c-dk2", "st,stm32mp157"; ++ compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157"; + + reserved-memory { + optee@de000000 { +diff --git a/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts +index 9cf0a44d2f47..21010458b36f 100644 +--- a/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts ++++ b/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts +@@ -11,7 +11,7 @@ + + / { + model = "STMicroelectronics STM32MP157C-ED1 SCMI eval daughter"; +- compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157c-ed1", "st,stm32mp157"; ++ compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157"; + + reserved-memory { + optee@fe000000 { +diff --git a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts +index 3b9dd6f4ccc9..d37637149919 100644 +--- a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts ++++ b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts +@@ -11,8 +11,7 @@ + + / { + model = "STMicroelectronics STM32MP157C-EV1 SCMI eval daughter on eval mother"; +- compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", +- "st,stm32mp157"; ++ compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ed1", "st,stm32mp157"; + + reserved-memory { + optee@fe000000 { +-- +2.43.0 + diff --git a/queue-6.1/arm64-dts-hisilicon-hikey970-pmic-fix-regulator-cell.patch b/queue-6.1/arm64-dts-hisilicon-hikey970-pmic-fix-regulator-cell.patch new file mode 100644 index 00000000000..957eb20c531 --- /dev/null +++ b/queue-6.1/arm64-dts-hisilicon-hikey970-pmic-fix-regulator-cell.patch @@ -0,0 +1,37 @@ +From c27a09ce33a1e1e84b06dca41ab0eb28a79b510a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 30 Nov 2023 18:56:34 +0100 +Subject: arm64: dts: hisilicon: hikey970-pmic: fix regulator cells properties + +From: Johan Hovold + +[ Upstream commit 44ab3ee76a5a977864ba0bb6c352dcf6206804e0 ] + +The Hi6421 PMIC regulator child nodes do not have unit addresses so drop +the incorrect '#address-cells' and '#size-cells' properties. + +Fixes: 6219b20e1ecd ("arm64: dts: hisilicon: Add support for Hikey 970 PMIC") +Signed-off-by: Johan Hovold +Signed-off-by: Wei Xu +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi +index 970047f2dabd..c06e011a6c3f 100644 +--- a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi ++++ b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi +@@ -25,9 +25,6 @@ pmic: pmic@0 { + gpios = <&gpio28 0 0>; + + regulators { +- #address-cells = <1>; +- #size-cells = <0>; +- + ldo3: ldo3 { /* HDMI */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1500000>; +-- +2.43.0 + diff --git a/queue-6.1/arm64-dts-imx8mm-reduce-gpu-to-nominal-speed.patch b/queue-6.1/arm64-dts-imx8mm-reduce-gpu-to-nominal-speed.patch new file mode 100644 index 00000000000..4d69ba805a8 --- /dev/null +++ b/queue-6.1/arm64-dts-imx8mm-reduce-gpu-to-nominal-speed.patch @@ -0,0 +1,51 @@ +From 94d020b553a87fd895f1cd130f47a421a9c0da95 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Nov 2023 14:02:16 -0600 +Subject: arm64: dts: imx8mm: Reduce GPU to nominal speed + +From: Adam Ford + +[ Upstream commit 1f794d3eed5345413c2b0cf1bcccc92d77681220 ] + +When the GPU nodes were added, the GPU_PLL_OUT was configured +for 1000MHz, but this requires the SoC to run in overdrive mode +which requires an elevated voltage operating point. + +Since this may run some boards out of spec, the default clock +should be set to 800MHz for nominal operating mode. Boards +that run at the higher voltage can update their clocks +accordingly. + +Fixes: 4523be8e46be ("arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core") +Signed-off-by: Adam Ford +Signed-off-by: Shawn Guo +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/freescale/imx8mm.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi +index d583db18f74c..7a410d73600b 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi ++++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi +@@ -1303,7 +1303,7 @@ gpu_3d: gpu@38000000 { + assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>, + <&clk IMX8MM_GPU_PLL_OUT>; + assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; +- assigned-clock-rates = <0>, <1000000000>; ++ assigned-clock-rates = <0>, <800000000>; + power-domains = <&pgc_gpu>; + }; + +@@ -1318,7 +1318,7 @@ gpu_2d: gpu@38008000 { + assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>, + <&clk IMX8MM_GPU_PLL_OUT>; + assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; +- assigned-clock-rates = <0>, <1000000000>; ++ assigned-clock-rates = <0>, <800000000>; + power-domains = <&pgc_gpu>; + }; + +-- +2.43.0 + diff --git a/queue-6.1/arm64-dts-mediatek-mt8183-correct-mdp3-dma-related-n.patch b/queue-6.1/arm64-dts-mediatek-mt8183-correct-mdp3-dma-related-n.patch new file mode 100644 index 00000000000..da37321c9bb --- /dev/null +++ b/queue-6.1/arm64-dts-mediatek-mt8183-correct-mdp3-dma-related-n.patch @@ -0,0 +1,62 @@ +From 96e0d12e09a0772e68ccb5d52db3f09f3c2b3889 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 30 Oct 2023 17:48:38 +0800 +Subject: arm64: dts: mediatek: mt8183: correct MDP3 DMA-related nodes + +From: Moudy Ho + +[ Upstream commit 188ffcd7fea79af3cac441268fc99f60e87f03b3 ] + +In order to generalize the node names, the DMA-related nodes +corresponding to MT8183 MDP3 need to be corrected. + +Fixes: 60a2fb8d202a ("arm64: dts: mt8183: add MediaTek MDP3 nodes") +Signed-off-by: Moudy Ho +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: AngeloGioacchino Del Regno +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/mediatek/mt8183.dtsi | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi +index 10779a9947fe..d5d9b954c449 100644 +--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi +@@ -1586,7 +1586,7 @@ mmsys: syscon@14000000 { + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; + }; + +- mdp3-rdma0@14001000 { ++ dma-controller0@14001000 { + compatible = "mediatek,mt8183-mdp3-rdma"; + reg = <0 0x14001000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; +@@ -1598,6 +1598,7 @@ mdp3-rdma0@14001000 { + iommus = <&iommu M4U_PORT_MDP_RDMA0>; + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>, + <&gce 21 CMDQ_THR_PRIO_LOWEST 0>; ++ #dma-cells = <1>; + }; + + mdp3-rsz0@14003000 { +@@ -1618,7 +1619,7 @@ mdp3-rsz1@14004000 { + clocks = <&mmsys CLK_MM_MDP_RSZ1>; + }; + +- mdp3-wrot0@14005000 { ++ dma-controller@14005000 { + compatible = "mediatek,mt8183-mdp3-wrot"; + reg = <0 0x14005000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; +@@ -1627,6 +1628,7 @@ mdp3-wrot0@14005000 { + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_WROT0>; + iommus = <&iommu M4U_PORT_MDP_WROT0>; ++ #dma-cells = <1>; + }; + + mdp3-wdma@14006000 { +-- +2.43.0 + diff --git a/queue-6.1/arm64-dts-qcom-ipq6018-fix-clock-rates-for-gcc_usb0_.patch b/queue-6.1/arm64-dts-qcom-ipq6018-fix-clock-rates-for-gcc_usb0_.patch new file mode 100644 index 00000000000..bba10404571 --- /dev/null +++ b/queue-6.1/arm64-dts-qcom-ipq6018-fix-clock-rates-for-gcc_usb0_.patch @@ -0,0 +1,41 @@ +From 618d78e36d0bf5fa1332898bb7e02724de1576ef Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 18 Dec 2023 23:08:05 +0800 +Subject: arm64: dts: qcom: ipq6018: fix clock rates for GCC_USB0_MOCK_UTMI_CLK + +From: Chukun Pan + +[ Upstream commit 5c0dbe8b058436ad5daecb19c60869f832607ea3 ] + +The downstream QSDK kernel [1] and GCC_USB1_MOCK_UTMI_CLK are both 24MHz. +Adjust GCC_USB0_MOCK_UTMI_CLK to 24MHz to avoid the following error: + +clk: couldn't set gcc_usb0_mock_utmi_clk clk rate to 20000000 (-22), current rate: 24000000 + +1. https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/486c8485f59 + +Fixes: 5726079cd486 ("arm64: dts: ipq6018: Use reference clock to set dwc3 period") +Signed-off-by: Chukun Pan +Link: https://lore.kernel.org/r/20231218150805.1228160-1-amadeus@jmu.edu.cn +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +index 43ff8f1f1475..d436fa64caad 100644 +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -745,7 +745,7 @@ usb3: usb@8af8800 { + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + assigned-clock-rates = <133330000>, + <133330000>, +- <20000000>; ++ <24000000>; + + resets = <&gcc GCC_USB0_BCR>; + status = "disabled"; +-- +2.43.0 + diff --git a/queue-6.1/arm64-dts-qcom-ipq6018-fix-up-indentation.patch b/queue-6.1/arm64-dts-qcom-ipq6018-fix-up-indentation.patch new file mode 100644 index 00000000000..2c6dfe0a2ba --- /dev/null +++ b/queue-6.1/arm64-dts-qcom-ipq6018-fix-up-indentation.patch @@ -0,0 +1,121 @@ +From dc43f38d0dd8464fa59dc1f7b432762db5d4cfcf Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 2 Jan 2023 10:46:27 +0100 +Subject: arm64: dts: qcom: ipq6018: Fix up indentation + +From: Konrad Dybcio + +[ Upstream commit c2596b717e9d96ae57c45481acfbafe9d3d54e56 ] + +The dwc3 subnode was indented using spaces for some reason and other +properties were not exactly properly indented. Fix it. + +Signed-off-by: Konrad Dybcio +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230102094642.74254-3-konrad.dybcio@linaro.org +Stable-dep-of: 5c0dbe8b0584 ("arm64: dts: qcom: ipq6018: fix clock rates for GCC_USB0_MOCK_UTMI_CLK") +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 44 +++++++++++++-------------- + 1 file changed, 22 insertions(+), 22 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +index 43a948b64007..1533c61cb106 100644 +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -201,8 +201,8 @@ crypto: crypto@73a000 { + compatible = "qcom,crypto-v5.1"; + reg = <0x0 0x0073a000 0x0 0x6000>; + clocks = <&gcc GCC_CRYPTO_AHB_CLK>, +- <&gcc GCC_CRYPTO_AXI_CLK>, +- <&gcc GCC_CRYPTO_CLK>; ++ <&gcc GCC_CRYPTO_AXI_CLK>, ++ <&gcc GCC_CRYPTO_CLK>; + clock-names = "iface", "bus", "core"; + dmas = <&cryptobam 2>, <&cryptobam 3>; + dma-names = "rx", "tx"; +@@ -272,7 +272,7 @@ blsp1_uart3: serial@78b1000 { + reg = <0x0 0x078b1000 0x0 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; ++ <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; +@@ -285,7 +285,7 @@ blsp1_spi1: spi@78b5000 { + interrupts = ; + spi-max-frequency = <50000000>; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; ++ <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 12>, <&blsp_dma 13>; + dma-names = "tx", "rx"; +@@ -300,7 +300,7 @@ blsp1_spi2: spi@78b6000 { + interrupts = ; + spi-max-frequency = <50000000>; + clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; ++ <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 14>, <&blsp_dma 15>; + dma-names = "tx", "rx"; +@@ -358,8 +358,8 @@ qpic_nand: nand@79b0000 { + clock-names = "core", "aon"; + + dmas = <&qpic_bam 0>, +- <&qpic_bam 1>, +- <&qpic_bam 2>; ++ <&qpic_bam 1>, ++ <&qpic_bam 2>; + dma-names = "tx", "rx", "cmd"; + pinctrl-0 = <&qpic_pins>; + pinctrl-names = "default"; +@@ -372,10 +372,10 @@ intc: interrupt-controller@b000000 { + #size-cells = <2>; + interrupt-controller; + #interrupt-cells = <0x3>; +- reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ +- <0x0 0x0b002000 0x0 0x1000>, /*GICC*/ +- <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ +- <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ ++ reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ ++ <0x0 0x0b002000 0x0 0x1000>, /*GICC*/ ++ <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ ++ <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ + interrupts = ; + ranges = <0 0 0 0xb00a000 0 0xffd>; + +@@ -669,17 +669,17 @@ usb2: usb@70f8800 { + status = "disabled"; + + dwc_1: usb@7000000 { +- compatible = "snps,dwc3"; +- reg = <0x0 0x07000000 0x0 0xcd00>; +- interrupts = ; +- phys = <&qusb_phy_1>; +- phy-names = "usb2-phy"; +- tx-fifo-resize; +- snps,is-utmi-l1-suspend; +- snps,hird-threshold = /bits/ 8 <0x0>; +- snps,dis_u2_susphy_quirk; +- snps,dis_u3_susphy_quirk; +- dr_mode = "host"; ++ compatible = "snps,dwc3"; ++ reg = <0x0 0x07000000 0x0 0xcd00>; ++ interrupts = ; ++ phys = <&qusb_phy_1>; ++ phy-names = "usb2-phy"; ++ tx-fifo-resize; ++ snps,is-utmi-l1-suspend; ++ snps,hird-threshold = /bits/ 8 <0x0>; ++ snps,dis_u2_susphy_quirk; ++ snps,dis_u3_susphy_quirk; ++ dr_mode = "host"; + }; + }; + +-- +2.43.0 + diff --git a/queue-6.1/arm64-dts-qcom-ipq6018-improve-pcie-phy-pcs-reg-tabl.patch b/queue-6.1/arm64-dts-qcom-ipq6018-improve-pcie-phy-pcs-reg-tabl.patch new file mode 100644 index 00000000000..6219665f2bc --- /dev/null +++ b/queue-6.1/arm64-dts-qcom-ipq6018-improve-pcie-phy-pcs-reg-tabl.patch @@ -0,0 +1,43 @@ +From 3478643b96d58a8d739210cce5bea96b60a7cd15 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 3 Nov 2022 22:21:25 +0100 +Subject: arm64: dts: qcom: ipq6018: improve pcie phy pcs reg table + +From: Christian Marangi + +[ Upstream commit 08f399a818b0eff552b1f23c3171950a58aea78f ] + +This is not a fix on its own but more a cleanup. Phy qmp pcie driver +currently have a workaround to handle pcs_misc not declared and add +0x400 offset to the pcs reg if pcs_misc is not declared. + +Correctly declare pcs_misc reg and reduce PCS size to the common value +of 0x1f0 as done for every other qmp based pcie phy device. + +Signed-off-by: Christian Marangi +Reviewed-by: Vinod Koul +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20221103212125.17156-2-ansuelsmth@gmail.com +Stable-dep-of: 5c0dbe8b0584 ("arm64: dts: qcom: ipq6018: fix clock rates for GCC_USB0_MOCK_UTMI_CLK") +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +index d436fa64caad..f3743ef7354f 100644 +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -406,7 +406,8 @@ pcie_phy: phy@84000 { + pcie_phy0: phy@84200 { + reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */ + <0x0 0x84400 0x0 0x200>, /* Serdes Rx */ +- <0x0 0x84800 0x0 0x4f4>; /* PCS: Lane0, COM, PCIE */ ++ <0x0 0x84800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */ ++ <0x0 0x84c00 0x0 0xf4>; /* pcs_misc */ + #phy-cells = <0>; + + clocks = <&gcc GCC_PCIE0_PIPE_CLK>; +-- +2.43.0 + diff --git a/queue-6.1/arm64-dts-qcom-ipq6018-pad-addresses-to-8-hex-digits.patch b/queue-6.1/arm64-dts-qcom-ipq6018-pad-addresses-to-8-hex-digits.patch new file mode 100644 index 00000000000..7fde936a68e --- /dev/null +++ b/queue-6.1/arm64-dts-qcom-ipq6018-pad-addresses-to-8-hex-digits.patch @@ -0,0 +1,114 @@ +From f1e3e35bafdb162441baede2c551c7d5bbe40194 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 2 Jan 2023 10:46:26 +0100 +Subject: arm64: dts: qcom: ipq6018: Pad addresses to 8 hex digits + +From: Konrad Dybcio + +[ Upstream commit 647380e41520c7dbd651ebf0d9fd7dfa4928f42d ] + +Some addresses were 7-hex-digits long, or less. Fix that. + +Signed-off-by: Konrad Dybcio +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230102094642.74254-2-konrad.dybcio@linaro.org +Stable-dep-of: 5c0dbe8b0584 ("arm64: dts: qcom: ipq6018: fix clock rates for GCC_USB0_MOCK_UTMI_CLK") +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 24 ++++++++++++------------ + 1 file changed, 12 insertions(+), 12 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +index 55f685f51c71..43a948b64007 100644 +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -146,7 +146,7 @@ reserved-memory { + ranges; + + rpm_msg_ram: memory@60000 { +- reg = <0x0 0x60000 0x0 0x6000>; ++ reg = <0x0 0x00060000 0x0 0x6000>; + no-map; + }; + +@@ -181,7 +181,7 @@ soc: soc { + + prng: qrng@e1000 { + compatible = "qcom,prng-ee"; +- reg = <0x0 0xe3000 0x0 0x1000>; ++ reg = <0x0 0x000e3000 0x0 0x1000>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; +@@ -388,7 +388,7 @@ v2m@0 { + + pcie_phy: phy@84000 { + compatible = "qcom,ipq6018-qmp-pcie-phy"; +- reg = <0x0 0x84000 0x0 0x1bc>; /* Serdes PLL */ ++ reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */ + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; +@@ -404,10 +404,10 @@ pcie_phy: phy@84000 { + "common"; + + pcie_phy0: phy@84200 { +- reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */ +- <0x0 0x84400 0x0 0x200>, /* Serdes Rx */ +- <0x0 0x84800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */ +- <0x0 0x84c00 0x0 0xf4>; /* pcs_misc */ ++ reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */ ++ <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */ ++ <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */ ++ <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */ + #phy-cells = <0>; + + clocks = <&gcc GCC_PCIE0_PIPE_CLK>; +@@ -629,7 +629,7 @@ mdio: mdio@90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio"; +- reg = <0x0 0x90000 0x0 0x64>; ++ reg = <0x0 0x00090000 0x0 0x64>; + clocks = <&gcc GCC_MDIO_AHB_CLK>; + clock-names = "gcc_mdio_ahb_clk"; + status = "disabled"; +@@ -637,7 +637,7 @@ mdio: mdio@90000 { + + qusb_phy_1: qusb@59000 { + compatible = "qcom,ipq6018-qusb2-phy"; +- reg = <0x0 0x059000 0x0 0x180>; ++ reg = <0x0 0x00059000 0x0 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, +@@ -670,7 +670,7 @@ usb2: usb@70f8800 { + + dwc_1: usb@7000000 { + compatible = "snps,dwc3"; +- reg = <0x0 0x7000000 0x0 0xcd00>; ++ reg = <0x0 0x07000000 0x0 0xcd00>; + interrupts = ; + phys = <&qusb_phy_1>; + phy-names = "usb2-phy"; +@@ -685,7 +685,7 @@ dwc_1: usb@7000000 { + + ssphy_0: ssphy@78000 { + compatible = "qcom,ipq6018-qmp-usb3-phy"; +- reg = <0x0 0x78000 0x0 0x1c4>; ++ reg = <0x0 0x00078000 0x0 0x1c4>; + #address-cells = <2>; + #size-cells = <2>; + ranges; +@@ -714,7 +714,7 @@ usb0_ssphy: phy@78200 { + + qusb_phy_0: qusb@79000 { + compatible = "qcom,ipq6018-qusb2-phy"; +- reg = <0x0 0x079000 0x0 0x180>; ++ reg = <0x0 0x00079000 0x0 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, +-- +2.43.0 + diff --git a/queue-6.1/arm64-dts-qcom-ipq6018-use-lowercase-hex.patch b/queue-6.1/arm64-dts-qcom-ipq6018-use-lowercase-hex.patch new file mode 100644 index 00000000000..4f81824aca8 --- /dev/null +++ b/queue-6.1/arm64-dts-qcom-ipq6018-use-lowercase-hex.patch @@ -0,0 +1,64 @@ +From eb4cd68d402d05bcf38602b25bd1f5ee335c0f0c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 12 Dec 2022 12:10:29 +0100 +Subject: arm64: dts: qcom: ipq6018: Use lowercase hex + +From: Konrad Dybcio + +[ Upstream commit 0431dba3733bf52dacf7382e7b0c1b4c0b59e88d ] + +Use lowercase hex, as that's the preferred and overwhermingly present +style. + +Signed-off-by: Konrad Dybcio +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20221212111037.98160-2-konrad.dybcio@linaro.org +Stable-dep-of: 5c0dbe8b0584 ("arm64: dts: qcom: ipq6018: fix clock rates for GCC_USB0_MOCK_UTMI_CLK") +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +index f3743ef7354f..55f685f51c71 100644 +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -685,7 +685,7 @@ dwc_1: usb@7000000 { + + ssphy_0: ssphy@78000 { + compatible = "qcom,ipq6018-qmp-usb3-phy"; +- reg = <0x0 0x78000 0x0 0x1C4>; ++ reg = <0x0 0x78000 0x0 0x1c4>; + #address-cells = <2>; + #size-cells = <2>; + ranges; +@@ -702,7 +702,7 @@ ssphy_0: ssphy@78000 { + usb0_ssphy: phy@78200 { + reg = <0x0 0x00078200 0x0 0x130>, /* Tx */ + <0x0 0x00078400 0x0 0x200>, /* Rx */ +- <0x0 0x00078800 0x0 0x1F8>, /* PCS */ ++ <0x0 0x00078800 0x0 0x1f8>, /* PCS */ + <0x0 0x00078600 0x0 0x044>; /* PCS misc */ + #phy-cells = <0>; + #clock-cells = <0>; +@@ -727,7 +727,7 @@ qusb_phy_0: qusb@79000 { + + usb3: usb@8af8800 { + compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; +- reg = <0x0 0x8AF8800 0x0 0x400>; ++ reg = <0x0 0x8af8800 0x0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; +@@ -753,7 +753,7 @@ usb3: usb@8af8800 { + + dwc_0: usb@8a00000 { + compatible = "snps,dwc3"; +- reg = <0x0 0x8A00000 0x0 0xcd00>; ++ reg = <0x0 0x8a00000 0x0 0xcd00>; + interrupts = ; + phys = <&qusb_phy_0>, <&usb0_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; +-- +2.43.0 + diff --git a/queue-6.1/arm64-dts-qcom-qrb5165-rb5-correct-led-panic-indicat.patch b/queue-6.1/arm64-dts-qcom-qrb5165-rb5-correct-led-panic-indicat.patch new file mode 100644 index 00000000000..91f0b160fc2 --- /dev/null +++ b/queue-6.1/arm64-dts-qcom-qrb5165-rb5-correct-led-panic-indicat.patch @@ -0,0 +1,42 @@ +From 82a5b5bdf6d426ed661385f88e33292a97e21544 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 11 Nov 2023 10:46:23 +0100 +Subject: arm64: dts: qcom: qrb5165-rb5: correct LED panic indicator + +From: Krzysztof Kozlowski + +[ Upstream commit dc6b5562acbac0285ab3b2dad23930b6434bdfc6 ] + +There is no "panic-indicator" default trigger but a property with that +name: + + qrb5165-rb5.dtb: leds: led-user4: Unevaluated properties are not allowed ('linux,default-trigger' was unexpected) + +Fixes: b5cbd84e499a ("arm64: dts: qcom: qrb5165-rb5: Add onboard LED support") +Signed-off-by: Krzysztof Kozlowski +Reviewed-by: Manivannan Sadhasivam +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231111094623.12476-1-krzysztof.kozlowski@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +index 9731a7c63d53..1defbe0404e2 100644 +--- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts ++++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +@@ -63,8 +63,8 @@ led-user4 { + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "panic-indicator"; + default-state = "off"; ++ panic-indicator; + }; + + led-wlan { +-- +2.43.0 + diff --git a/queue-6.1/arm64-dts-qcom-sc7180-make-watchdog-bark-interrupt-e.patch b/queue-6.1/arm64-dts-qcom-sc7180-make-watchdog-bark-interrupt-e.patch new file mode 100644 index 00000000000..0cb98f98f7d --- /dev/null +++ b/queue-6.1/arm64-dts-qcom-sc7180-make-watchdog-bark-interrupt-e.patch @@ -0,0 +1,58 @@ +From 9c22172ea02f6168af9b2b67ae7a322592cb31e0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 6 Nov 2023 14:43:28 -0800 +Subject: arm64: dts: qcom: sc7180: Make watchdog bark interrupt edge triggered + +From: Douglas Anderson + +[ Upstream commit 7ac90b4cf107a3999b30844d7899e0331686b33b ] + +On sc7180 when the watchdog timer fires your logs get filled with: + watchdog0: pretimeout event + watchdog0: pretimeout event + watchdog0: pretimeout event + ... + watchdog0: pretimeout event + +If you're using console-ramoops to debug crashes the above gets quite +annoying since it blows away any other log messages that might have +been there. + +The issue is that the "bark" interrupt (AKA the "pretimeout" +interrupt) remains high until the watchdog is pet. Since we've got +things configured as "level" triggered we'll keep getting interrupted +over and over. + +Let's switch to edge triggered. Now we'll get one interrupt when the +"bark" interrupt goes off and won't get another one until the "bark" +interrupt is cleared and asserts again. + +This matches how many older Qualcomm SoCs have things configured. + +Fixes: 28cc13e4060c ("arm64: dts: qcom: sc7180: Add watchdog bark interrupt") +Reviewed-by: Guenter Roeck +Reviewed-by: Stephen Boyd +Signed-off-by: Douglas Anderson +Link: https://lore.kernel.org/r/20231106144335.v2.1.Ic7577567baff921347d423b722de8b857602efb1@changeid +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi +index 6f0ee4e13ef1..78e537f1d796 100644 +--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi +@@ -3378,7 +3378,7 @@ watchdog@17c10000 { + compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; + reg = <0 0x17c10000 0 0x1000>; + clocks = <&sleep_clk>; +- interrupts = ; ++ interrupts = ; + }; + + timer@17c20000{ +-- +2.43.0 + diff --git a/queue-6.1/arm64-dts-qcom-sc7280-fix-up-gpu-sids.patch b/queue-6.1/arm64-dts-qcom-sc7280-fix-up-gpu-sids.patch new file mode 100644 index 00000000000..b6a25b69d9d --- /dev/null +++ b/queue-6.1/arm64-dts-qcom-sc7280-fix-up-gpu-sids.patch @@ -0,0 +1,44 @@ +From 12912dec0136297c1cb98a6853d7c42f8051f70c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 20 Nov 2023 13:12:53 +0100 +Subject: arm64: dts: qcom: sc7280: Fix up GPU SIDs + +From: Konrad Dybcio + +[ Upstream commit 94085049fdad7a36fe14dd55e72e712fe55d6bca ] + +GPU_SMMU SID 1 is meant for Adreno LPAC (Low Priority Async Compute). +On platforms that support it (in firmware), it is necessary to +describe that link, or Adreno register access will hang the board. + +The current settings are functionally identical, *but* due to what is +likely hardcoded security policies, the secure firmware rejects them, +resulting in the board hanging. To avoid that, alter the settings such +that SID 0 and 1 are described separately. + +Fixes: 96c471970b7b ("arm64: dts: qcom: sc7280: Add gpu support") +Signed-off-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20230926-topic-a643-v2-2-06fa3d899c0a@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi +index b1016ccdf032..30e18ce54921 100644 +--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi +@@ -2533,7 +2533,8 @@ gpu: gpu@3d00000 { + "cx_mem", + "cx_dbgc"; + interrupts = ; +- iommus = <&adreno_smmu 0 0x401>; ++ iommus = <&adreno_smmu 0 0x400>, ++ <&adreno_smmu 1 0x400>; + operating-points-v2 = <&gpu_opp_table>; + qcom,gmu = <&gmu>; + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; +-- +2.43.0 + diff --git a/queue-6.1/arm64-dts-qcom-sc7280-fix-usb_2-wakeup-interrupt-typ.patch b/queue-6.1/arm64-dts-qcom-sc7280-fix-usb_2-wakeup-interrupt-typ.patch new file mode 100644 index 00000000000..c1e177a563d --- /dev/null +++ b/queue-6.1/arm64-dts-qcom-sc7280-fix-usb_2-wakeup-interrupt-typ.patch @@ -0,0 +1,43 @@ +From a61ffba5c52bc252c34f23c8b1e0604eaacdfbbe Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 20 Nov 2023 17:43:25 +0100 +Subject: arm64: dts: qcom: sc7280: fix usb_2 wakeup interrupt types + +From: Johan Hovold + +[ Upstream commit 24f8aba9a7c77c7e9d814a5754798e8346c7dd28 ] + +The DP/DM wakeup interrupts are edge triggered and which edge to trigger +on depends on use-case and whether a Low speed or Full/High speed device +is connected. + +Note that only triggering on rising edges can be used to detect resume +events but not disconnect events. + +Fixes: bb9efa59c665 ("arm64: dts: qcom: sc7280: Add USB related nodes") +Signed-off-by: Johan Hovold +Link: https://lore.kernel.org/r/20231120164331.8116-6-johan+linaro@kernel.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi +index fd1a451e1ba2..8a23250d5951 100644 +--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi +@@ -3392,8 +3392,8 @@ usb_2: usb@8cf8800 { + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, +- <&pdc 12 IRQ_TYPE_EDGE_RISING>, +- <&pdc 13 IRQ_TYPE_EDGE_RISING>; ++ <&pdc 12 IRQ_TYPE_EDGE_BOTH>, ++ <&pdc 13 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq"; +-- +2.43.0 + diff --git a/queue-6.1/arm64-dts-qcom-sc7280-make-watchdog-bark-interrupt-e.patch b/queue-6.1/arm64-dts-qcom-sc7280-make-watchdog-bark-interrupt-e.patch new file mode 100644 index 00000000000..1f2b3454c1d --- /dev/null +++ b/queue-6.1/arm64-dts-qcom-sc7280-make-watchdog-bark-interrupt-e.patch @@ -0,0 +1,40 @@ +From 8089eb21d50ac55f902a5398b98beacc11f10344 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 6 Nov 2023 14:43:29 -0800 +Subject: arm64: dts: qcom: sc7280: Make watchdog bark interrupt edge triggered + +From: Douglas Anderson + +[ Upstream commit 6897fac411db7b43243f67d4fd4d3f95abf7f656 ] + +As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog +bark interrupt edge triggered"), the Qualcomm watchdog timer's bark +interrupt should be configured as edge triggered. Make the change. + +Fixes: 0e51f883daa9 ("arm64: dts: qcom: sc7280: Add APSS watchdog node") +Reviewed-by: Guenter Roeck +Reviewed-by: Stephen Boyd +Signed-off-by: Douglas Anderson +Link: https://lore.kernel.org/r/20231106144335.v2.2.I11f77956d2492c88aca0ef5462123f225caf4fb4@changeid +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi +index 4b8777eb96f1..b1016ccdf032 100644 +--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi +@@ -5195,7 +5195,7 @@ watchdog: watchdog@17c10000 { + compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; + reg = <0 0x17c10000 0 0x1000>; + clocks = <&sleep_clk>; +- interrupts = ; ++ interrupts = ; + status = "reserved"; /* Owned by Gunyah hyp */ + }; + +-- +2.43.0 + diff --git a/queue-6.1/arm64-dts-qcom-sc7280-mark-adreno-smmu-as-dma-cohere.patch b/queue-6.1/arm64-dts-qcom-sc7280-mark-adreno-smmu-as-dma-cohere.patch new file mode 100644 index 00000000000..93a6ef5a302 --- /dev/null +++ b/queue-6.1/arm64-dts-qcom-sc7280-mark-adreno-smmu-as-dma-cohere.patch @@ -0,0 +1,37 @@ +From d344fef9c8b29825759f1b10655dd485b1748a55 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 20 Nov 2023 13:12:54 +0100 +Subject: arm64: dts: qcom: sc7280: Mark Adreno SMMU as DMA coherent + +From: Konrad Dybcio + +[ Upstream commit 31edad478534186a2718be9206ce7b19f2735f6e ] + +The SMMUs on sc7280 are cache-coherent. APPS_SMMU is marked as such, +mark the GPU one as well. + +Fixes: 96c471970b7b ("arm64: dts: qcom: sc7280: Add gpu support") +Reviewed-by: Akhil P Oommen +Signed-off-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20230926-topic-a643-v2-3-06fa3d899c0a@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sc7280.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi +index 30e18ce54921..fd1a451e1ba2 100644 +--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi +@@ -2701,6 +2701,7 @@ adreno_smmu: iommu@3da0000 { + "gpu_cc_hub_aon_clk"; + + power-domains = <&gpucc GPU_CC_CX_GDSC>; ++ dma-coherent; + }; + + remoteproc_mpss: remoteproc@4080000 { +-- +2.43.0 + diff --git a/queue-6.1/arm64-dts-qcom-sc7280-mark-sdhci-hosts-as-cache-cohe.patch b/queue-6.1/arm64-dts-qcom-sc7280-mark-sdhci-hosts-as-cache-cohe.patch new file mode 100644 index 00000000000..edcc3f92b2f --- /dev/null +++ b/queue-6.1/arm64-dts-qcom-sc7280-mark-sdhci-hosts-as-cache-cohe.patch @@ -0,0 +1,44 @@ +From b77d4b80ef9bf4ab88642c0d53e1ca277f8e377b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 18 Dec 2023 15:38:33 +0100 +Subject: arm64: dts: qcom: sc7280: Mark SDHCI hosts as cache-coherent + +From: Konrad Dybcio + +[ Upstream commit 827f5fc8d912203c1f971e47d61130b13c6820ba ] + +The SDHCI hosts on SC7280 are cache-coherent, just like on most fairly +recent Qualcomm SoCs. Mark them as such. + +Fixes: 298c81a7d44f ("arm64: dts: qcom: sc7280: Add nodes for eMMC and SD card") +Signed-off-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231218-topic-7280_dmac_sdhci-v1-1-97af7efd64a1@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi +index 8a23250d5951..7fc8c2045022 100644 +--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi +@@ -888,6 +888,7 @@ sdhc_1: mmc@7c4000 { + + bus-width = <8>; + supports-cqe; ++ dma-coherent; + + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; +@@ -3271,6 +3272,7 @@ sdhc_2: mmc@8804000 { + operating-points-v2 = <&sdhc2_opp_table>; + + bus-width = <4>; ++ dma-coherent; + + qcom,dll-config = <0x0007642c>; + +-- +2.43.0 + diff --git a/queue-6.1/arm64-dts-qcom-sc7280-mark-some-nodes-as-reserved.patch b/queue-6.1/arm64-dts-qcom-sc7280-mark-some-nodes-as-reserved.patch new file mode 100644 index 00000000000..42a7ab93d02 --- /dev/null +++ b/queue-6.1/arm64-dts-qcom-sc7280-mark-some-nodes-as-reserved.patch @@ -0,0 +1,126 @@ +From 96f3e84906d586f99241ef673d42c28a5c380ba0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 19 Sep 2023 14:45:55 +0200 +Subject: arm64: dts: qcom: sc7280: Mark some nodes as 'reserved' + +From: Luca Weiss + +[ Upstream commit 6da24ba932082bae110feb917a64bb54637fa7c0 ] + +With the standard Qualcomm TrustZone setup, components such as lpasscc, +pdc_reset and watchdog shouldn't be touched by Linux. Mark them with +the status 'reserved' and reenable them in the chrome-common dtsi. + +Signed-off-by: Luca Weiss +Link: https://lore.kernel.org/r/20230919-fp5-initial-v2-1-14bb7cedadf5@fairphone.com +Signed-off-by: Bjorn Andersson +Stable-dep-of: 6897fac411db ("arm64: dts: qcom: sc7280: Make watchdog bark interrupt edge triggered") +Signed-off-by: Sasha Levin +--- + .../boot/dts/qcom/sc7280-chrome-common.dtsi | 24 +++++++++++++++++++ + arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++- + 2 files changed, 31 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi +index 25f31c81b2b7..efe6ea538ad2 100644 +--- a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi +@@ -56,6 +56,26 @@ mba_mem: memory@9c700000 { + }; + }; + ++&lpass_aon { ++ status = "okay"; ++}; ++ ++&lpass_core { ++ status = "okay"; ++}; ++ ++&lpass_hm { ++ status = "okay"; ++}; ++ ++&lpasscc { ++ status = "okay"; ++}; ++ ++&pdc_reset { ++ status = "okay"; ++}; ++ + /* The PMIC PON code isn't compatible w/ how Chrome EC/BIOS handle things. */ + &pmk8350_pon { + status = "disabled"; +@@ -93,6 +113,10 @@ &rmtfs_mem { + reg = <0x0 0x9c900000 0x0 0x800000>; + }; + ++&watchdog { ++ status = "okay"; ++}; ++ + &wifi { + status = "okay"; + +diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi +index aea356c63b9a..4b8777eb96f1 100644 +--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi +@@ -2187,6 +2187,7 @@ lpasscc: lpasscc@3000000 { + clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; + clock-names = "iface"; + #clock-cells = <1>; ++ status = "reserved"; /* Owned by ADSP firmware */ + }; + + lpass_rx_macro: codec@3200000 { +@@ -2339,6 +2340,7 @@ lpass_aon: clock-controller@3380000 { + clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; + #clock-cells = <1>; + #power-domain-cells = <1>; ++ status = "reserved"; /* Owned by ADSP firmware */ + }; + + lpass_core: clock-controller@3900000 { +@@ -2349,6 +2351,7 @@ lpass_core: clock-controller@3900000 { + power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; + #clock-cells = <1>; + #power-domain-cells = <1>; ++ status = "reserved"; /* Owned by ADSP firmware */ + }; + + lpass_cpu: audio@3987000 { +@@ -2419,6 +2422,7 @@ lpass_hm: clock-controller@3c00000 { + clock-names = "bi_tcxo"; + #clock-cells = <1>; + #power-domain-cells = <1>; ++ status = "reserved"; /* Owned by ADSP firmware */ + }; + + lpass_ag_noc: interconnect@3c40000 { +@@ -4195,6 +4199,7 @@ pdc_reset: reset-controller@b5e0000 { + compatible = "qcom,sc7280-pdc-global"; + reg = <0 0x0b5e0000 0 0x20000>; + #reset-cells = <1>; ++ status = "reserved"; /* Owned by firmware */ + }; + + tsens0: thermal-sensor@c263000 { +@@ -5186,11 +5191,12 @@ gic-its@17a40000 { + }; + }; + +- watchdog@17c10000 { ++ watchdog: watchdog@17c10000 { + compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; + reg = <0 0x17c10000 0 0x1000>; + clocks = <&sleep_clk>; + interrupts = ; ++ status = "reserved"; /* Owned by Gunyah hyp */ + }; + + timer@17c20000 { +-- +2.43.0 + diff --git a/queue-6.1/arm64-dts-qcom-sc8280xp-make-watchdog-bark-interrupt.patch b/queue-6.1/arm64-dts-qcom-sc8280xp-make-watchdog-bark-interrupt.patch new file mode 100644 index 00000000000..127af551bea --- /dev/null +++ b/queue-6.1/arm64-dts-qcom-sc8280xp-make-watchdog-bark-interrupt.patch @@ -0,0 +1,41 @@ +From 24776ad88be557d81158cc6d344a7825e3c1a890 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 6 Nov 2023 14:43:34 -0800 +Subject: arm64: dts: qcom: sc8280xp: Make watchdog bark interrupt edge + triggered + +From: Douglas Anderson + +[ Upstream commit 6c4a9c7ea486da490400c84ba2768c90d228c283 ] + +As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog +bark interrupt edge triggered"), the Qualcomm watchdog timer's bark +interrupt should be configured as edge triggered. Make the change. + +Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") +Reviewed-by: Guenter Roeck +Reviewed-by: Stephen Boyd +Signed-off-by: Douglas Anderson +Link: https://lore.kernel.org/r/20231106144335.v2.7.I1c8ab71570f6906fd020decb80675f05fbe1fe74@changeid +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +index 405835ad28bc..7e3aaf5de3f5 100644 +--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +@@ -1653,7 +1653,7 @@ watchdog@17c10000 { + compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt"; + reg = <0 0x17c10000 0 0x1000>; + clocks = <&sleep_clk>; +- interrupts = ; ++ interrupts = ; + }; + + timer@17c20000 { +-- +2.43.0 + diff --git a/queue-6.1/arm64-dts-qcom-sdm845-db845c-correct-led-panic-indic.patch b/queue-6.1/arm64-dts-qcom-sdm845-db845c-correct-led-panic-indic.patch new file mode 100644 index 00000000000..7fcd29d8712 --- /dev/null +++ b/queue-6.1/arm64-dts-qcom-sdm845-db845c-correct-led-panic-indic.patch @@ -0,0 +1,41 @@ +From 829161c9027c57219571f8dd3e9a3bed37cbb661 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 11 Nov 2023 10:56:16 +0100 +Subject: arm64: dts: qcom: sdm845-db845c: correct LED panic indicator + +From: Krzysztof Kozlowski + +[ Upstream commit 0c90c75e663246203a2b7f6dd9e08a110f4c3c43 ] + +There is no "panic-indicator" default trigger but a property with that +name: + + sdm845-db845c.dtb: leds: led-0: Unevaluated properties are not allowed ('linux,default-trigger' was unexpected) + +Fixes: 3f72e2d3e682 ("arm64: dts: qcom: Add Dragonboard 845c") +Signed-off-by: Krzysztof Kozlowski +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231111095617.16496-1-krzysztof.kozlowski@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +index 8c9ccf5b4ea4..135ff4368c4a 100644 +--- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts ++++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +@@ -66,8 +66,8 @@ led-0 { + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&pm8998_gpio 13 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "panic-indicator"; + default-state = "off"; ++ panic-indicator; + }; + + led-1 { +-- +2.43.0 + diff --git a/queue-6.1/arm64-dts-qcom-sdm845-make-watchdog-bark-interrupt-e.patch b/queue-6.1/arm64-dts-qcom-sdm845-make-watchdog-bark-interrupt-e.patch new file mode 100644 index 00000000000..6f7694ee079 --- /dev/null +++ b/queue-6.1/arm64-dts-qcom-sdm845-make-watchdog-bark-interrupt-e.patch @@ -0,0 +1,40 @@ +From 7c2f36ada63c455c7251486d24120121865b5cb9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 6 Nov 2023 14:43:30 -0800 +Subject: arm64: dts: qcom: sdm845: Make watchdog bark interrupt edge triggered + +From: Douglas Anderson + +[ Upstream commit 263b348499454f38d36b9442c3cf9279c571bb54 ] + +As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog +bark interrupt edge triggered"), the Qualcomm watchdog timer's bark +interrupt should be configured as edge triggered. Make the change. + +Fixes: 36c436b03c58 ("arm64: dts: qcom: sdm845: Add watchdog bark interrupt") +Reviewed-by: Guenter Roeck +Reviewed-by: Stephen Boyd +Signed-off-by: Douglas Anderson +Link: https://lore.kernel.org/r/20231106144335.v2.3.I16675ebe5517c68453a1bd7f4334ff885f806c03@changeid +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi +index 52c9f5639f8a..1e6841902900 100644 +--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi ++++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi +@@ -5019,7 +5019,7 @@ watchdog@17980000 { + compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; + reg = <0 0x17980000 0 0x1000>; + clocks = <&sleep_clk>; +- interrupts = ; ++ interrupts = ; + }; + + apss_shared: mailbox@17990000 { +-- +2.43.0 + diff --git a/queue-6.1/arm64-dts-qcom-sm6350-make-watchdog-bark-interrupt-e.patch b/queue-6.1/arm64-dts-qcom-sm6350-make-watchdog-bark-interrupt-e.patch new file mode 100644 index 00000000000..7ac05e57703 --- /dev/null +++ b/queue-6.1/arm64-dts-qcom-sm6350-make-watchdog-bark-interrupt-e.patch @@ -0,0 +1,40 @@ +From 49f4725ace74ba4106cb7fee8772912183452520 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 6 Nov 2023 14:43:35 -0800 +Subject: arm64: dts: qcom: sm6350: Make watchdog bark interrupt edge triggered + +From: Douglas Anderson + +[ Upstream commit 5b84bb2b8d86595544fc8272364b0f1a34b68a4f ] + +As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog +bark interrupt edge triggered"), the Qualcomm watchdog timer's bark +interrupt should be configured as edge triggered. Make the change. + +Fixes: 5f82b9cda61e ("arm64: dts: qcom: Add SM6350 device tree") +Reviewed-by: Guenter Roeck +Reviewed-by: Stephen Boyd +Signed-off-by: Douglas Anderson +Link: https://lore.kernel.org/r/20231106144335.v2.8.Ic1d4402e99c70354d501ccd98105e908a902f671@changeid +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi +index cea7ca3f326f..9da373090593 100644 +--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi +@@ -1462,7 +1462,7 @@ watchdog@17c10000 { + compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt"; + reg = <0 0x17c10000 0 0x1000>; + clocks = <&sleep_clk>; +- interrupts = ; ++ interrupts = ; + }; + + timer@17c20000 { +-- +2.43.0 + diff --git a/queue-6.1/arm64-dts-qcom-sm8150-hdk-fix-ss-usb-regulators.patch b/queue-6.1/arm64-dts-qcom-sm8150-hdk-fix-ss-usb-regulators.patch new file mode 100644 index 00000000000..c451e8c5ed5 --- /dev/null +++ b/queue-6.1/arm64-dts-qcom-sm8150-hdk-fix-ss-usb-regulators.patch @@ -0,0 +1,70 @@ +From 1522cd2db6104a1960cf538c5a4ca040edc5520f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 15 Dec 2023 19:40:35 +0200 +Subject: arm64: dts: qcom: sm8150-hdk: fix SS USB regulators + +From: Dmitry Baryshkov + +[ Upstream commit a509adf05b2aac31b22781f5aa09e4768a5b6c39 ] + +The SM8150-HDK uses two different regulators to power up SuperSpeed USB +PHYs. The L5A regulator is used for the second USB host, while the first +(OTG) USB host uses different regulator, L18A. Fix the regulator for the +usb_1 QMPPHY and (to remove possible confusion) drop the +usb_ss_dp_core_1/_2 labels. + +Fixes: 0ab1b2d10afe ("arm64: dts: qcom: add sm8150 hdk dts") +Reviewed-by: Konrad Dybcio +Signed-off-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20231215174152.315403-4-dmitry.baryshkov@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 12 ++++++++---- + 1 file changed, 8 insertions(+), 4 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +index 3331ee957d64..368da4c7f41b 100644 +--- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts ++++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +@@ -126,8 +126,6 @@ vdda_qrefs_0p875_5: + vdda_sp_sensor: + vdda_ufs_2ln_core_1: + vdda_ufs_2ln_core_2: +- vdda_usb_ss_dp_core_1: +- vdda_usb_ss_dp_core_2: + vdda_qlink_lv: + vdda_qlink_lv_ck: + vreg_l5a_0p875: ldo5 { +@@ -209,6 +207,12 @@ vreg_l17a_3p0: ldo17 { + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; ++ ++ vreg_l18a_0p8: ldo18 { ++ regulator-min-microvolt = <880000>; ++ regulator-max-microvolt = <880000>; ++ regulator-initial-mode = ; ++ }; + }; + + pm8150l-rpmh-regulators { +@@ -439,13 +443,13 @@ &usb_2_hsphy { + &usb_1_qmpphy { + status = "okay"; + vdda-phy-supply = <&vreg_l3c_1p2>; +- vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; ++ vdda-pll-supply = <&vreg_l18a_0p8>; + }; + + &usb_2_qmpphy { + status = "okay"; + vdda-phy-supply = <&vreg_l3c_1p2>; +- vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; ++ vdda-pll-supply = <&vreg_l5a_0p875>; + }; + + &usb_1 { +-- +2.43.0 + diff --git a/queue-6.1/arm64-dts-qcom-sm8150-make-watchdog-bark-interrupt-e.patch b/queue-6.1/arm64-dts-qcom-sm8150-make-watchdog-bark-interrupt-e.patch new file mode 100644 index 00000000000..774b3ccd933 --- /dev/null +++ b/queue-6.1/arm64-dts-qcom-sm8150-make-watchdog-bark-interrupt-e.patch @@ -0,0 +1,40 @@ +From 119d8dcdc038014921a4e02cba2e35fbba53b98e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 6 Nov 2023 14:43:31 -0800 +Subject: arm64: dts: qcom: sm8150: Make watchdog bark interrupt edge triggered + +From: Douglas Anderson + +[ Upstream commit 9204e9a4099212c850e1703c374ef4538080825b ] + +As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog +bark interrupt edge triggered"), the Qualcomm watchdog timer's bark +interrupt should be configured as edge triggered. Make the change. + +Fixes: b094c8f8dd2a ("arm64: dts: qcom: sm8150: Add watchdog bark interrupt") +Reviewed-by: Guenter Roeck +Reviewed-by: Stephen Boyd +Signed-off-by: Douglas Anderson +Link: https://lore.kernel.org/r/20231106144335.v2.4.I23d0aa6c8f1fec5c26ad9b3c610df6f4c5392850@changeid +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi +index c586378fc6bc..c3c12b0cd416 100644 +--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi +@@ -3940,7 +3940,7 @@ watchdog@17c10000 { + compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; + reg = <0 0x17c10000 0 0x1000>; + clocks = <&sleep_clk>; +- interrupts = ; ++ interrupts = ; + }; + + timer@17c20000 { +-- +2.43.0 + diff --git a/queue-6.1/arm64-dts-qcom-sm8250-make-watchdog-bark-interrupt-e.patch b/queue-6.1/arm64-dts-qcom-sm8250-make-watchdog-bark-interrupt-e.patch new file mode 100644 index 00000000000..a7d7860b917 --- /dev/null +++ b/queue-6.1/arm64-dts-qcom-sm8250-make-watchdog-bark-interrupt-e.patch @@ -0,0 +1,40 @@ +From 16c352018242c7e3b3feadcff91d9d527f721a00 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 6 Nov 2023 14:43:32 -0800 +Subject: arm64: dts: qcom: sm8250: Make watchdog bark interrupt edge triggered + +From: Douglas Anderson + +[ Upstream commit 735d80e2e8e5d073ae8b1fff8b1589ea284aa5af ] + +As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog +bark interrupt edge triggered"), the Qualcomm watchdog timer's bark +interrupt should be configured as edge triggered. Make the change. + +Fixes: 46a4359f9156 ("arm64: dts: qcom: sm8250: Add watchdog bark interrupt") +Reviewed-by: Guenter Roeck +Reviewed-by: Stephen Boyd +Signed-off-by: Douglas Anderson +Link: https://lore.kernel.org/r/20231106144335.v2.5.I2910e7c10493d896841e9785c1817df9b9a58701@changeid +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi +index 4d9b30f0b284..3d02adbc0b62 100644 +--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi +@@ -4879,7 +4879,7 @@ watchdog@17c10000 { + compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; + reg = <0 0x17c10000 0 0x1000>; + clocks = <&sleep_clk>; +- interrupts = ; ++ interrupts = ; + }; + + timer@17c20000 { +-- +2.43.0 + diff --git a/queue-6.1/arm64-dts-qcom-sm8350-fix-dma0-address.patch b/queue-6.1/arm64-dts-qcom-sm8350-fix-dma0-address.patch new file mode 100644 index 00000000000..c5ae8e92a6b --- /dev/null +++ b/queue-6.1/arm64-dts-qcom-sm8350-fix-dma0-address.patch @@ -0,0 +1,42 @@ +From 443d186f9e02ac539d1a7b2343f2a792261fe2a0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 11 Nov 2023 23:07:40 +0100 +Subject: arm64: dts: qcom: sm8350: Fix DMA0 address + +From: Nia Espera + +[ Upstream commit 01a9e9eb6cdbce175ddea3cbe1163daed6d54344 ] + +DMA0 node downstream is specified at 0x900000, so fix the typo. Without +this, enabling any i2c node using DMA0 causes a hang. + +Fixes: bc08fbf49bc8 ("arm64: dts: qcom: sm8350: Define GPI DMA engines") +Fixes: 41d6bca799b3 ("arm64: dts: qcom: sm8350: correct DMA controller unit address") +Reviewed-by: Konrad Dybcio +Signed-off-by: Nia Espera +Link: https://lore.kernel.org/r/20231111-nia-sm8350-for-upstream-v4-2-3a638b02eea5@igalia.com +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sm8350.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi +index 793768a2c9e1..888bf4cd73c3 100644 +--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi +@@ -903,9 +903,9 @@ spi19: spi@894000 { + }; + }; + +- gpi_dma0: dma-controller@9800000 { ++ gpi_dma0: dma-controller@900000 { + compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; +- reg = <0 0x09800000 0 0x60000>; ++ reg = <0 0x00900000 0 0x60000>; + interrupts = , + , + , +-- +2.43.0 + diff --git a/queue-6.1/arm64-dts-renesas-white-hawk-cpu-fix-missing-serial-.patch b/queue-6.1/arm64-dts-renesas-white-hawk-cpu-fix-missing-serial-.patch new file mode 100644 index 00000000000..0c010dfa9a0 --- /dev/null +++ b/queue-6.1/arm64-dts-renesas-white-hawk-cpu-fix-missing-serial-.patch @@ -0,0 +1,39 @@ +From 3b83f757e40bc15919746e29adeb4493efac77a9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 13 Dec 2023 10:32:25 +0100 +Subject: arm64: dts: renesas: white-hawk-cpu: Fix missing serial console pin + control + +From: Geert Uytterhoeven + +[ Upstream commit fc67495680f60e88bb8ca43421c1dd628928d581 ] + +The pin control description for the serial console was added, but not +enabled, due to missing pinctrl properties in the serial port device +node. + +Fixes: 7a8d590de8132853 ("arm64: dts: renesas: white-hawk-cpu: Add serial port pin control") +Signed-off-by: Geert Uytterhoeven +Link: https://lore.kernel.org/r/8a51516581cd71ecbfa174af9c7cebad1fc83c5b.1702459865.git.geert+renesas@glider.be +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi +index 895f0bd9f754..541b1e73b65e 100644 +--- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi +@@ -125,6 +125,9 @@ &extalr_clk { + }; + + &hscif0 { ++ pinctrl-0 = <&hscif0_pins>; ++ pinctrl-names = "default"; ++ + status = "okay"; + }; + +-- +2.43.0 + diff --git a/queue-6.1/arm64-dts-ti-k3-am62a-main-fix-gpio-pin-count-in-dt-.patch b/queue-6.1/arm64-dts-ti-k3-am62a-main-fix-gpio-pin-count-in-dt-.patch new file mode 100644 index 00000000000..05d68df25eb --- /dev/null +++ b/queue-6.1/arm64-dts-ti-k3-am62a-main-fix-gpio-pin-count-in-dt-.patch @@ -0,0 +1,47 @@ +From 4c3d98ab5f16790e39b41462e259bd152cc50024 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 27 Oct 2023 12:29:30 +0530 +Subject: arm64: dts: ti: k3-am62a-main: Fix GPIO pin count in DT nodes + +From: Nitin Yadav + +[ Upstream commit 7dc4af358cc382c5d20bd5b726e53ef0f526eb6d ] + +Fix number of gpio pins in main_gpio0 & main_gpio1 DT nodes according +to AM62A7 datasheet[0]. + +[0] https://www.ti.com/lit/gpn/am62a3 Section: 6.3.10 GPIO (Page No. 52-55) +Fixes: 5fc6b1b62639 ("arm64: dts: ti: Introduce AM62A7 family of SoCs") +Signed-off-by: Nitin Yadav +Link: https://lore.kernel.org/r/20231027065930.1187405-1-n-yadav@ti.com +Signed-off-by: Nishanth Menon +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +index bc4b50bcd177..9301ea388802 100644 +--- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi ++++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +@@ -245,7 +245,7 @@ main_gpio0: gpio@600000 { + <193>, <194>, <195>; + interrupt-controller; + #interrupt-cells = <2>; +- ti,ngpio = <87>; ++ ti,ngpio = <92>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 77 0>; +@@ -263,7 +263,7 @@ main_gpio1: gpio@601000 { + <183>, <184>, <185>; + interrupt-controller; + #interrupt-cells = <2>; +- ti,ngpio = <88>; ++ ti,ngpio = <52>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 78 0>; +-- +2.43.0 + diff --git a/queue-6.1/arm64-dts-ti-k3-am65-main-fix-dss-irq-trigger-type.patch b/queue-6.1/arm64-dts-ti-k3-am65-main-fix-dss-irq-trigger-type.patch new file mode 100644 index 00000000000..5ae01fb9242 --- /dev/null +++ b/queue-6.1/arm64-dts-ti-k3-am65-main-fix-dss-irq-trigger-type.patch @@ -0,0 +1,47 @@ +From 7649dc91e7c74359954636a350228a300a96369e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 6 Nov 2023 11:57:48 +0200 +Subject: arm64: dts: ti: k3-am65-main: Fix DSS irq trigger type + +From: Tomi Valkeinen + +[ Upstream commit b57160859263c083c49482b0d083a586b1517f78 ] + +DSS irq trigger type is set to IRQ_TYPE_EDGE_RISING in the DT file, but +the TRM says it is level triggered. + +For some reason triggering on rising edge results in double the amount +of expected interrupts, e.g. for normal page flipping test the number of +interrupts per second is 2 * fps. It is as if the IRQ triggers on both +edges. There are no other side effects to this issue than slightly +increased CPU & power consumption due to the extra interrupt. + +Switching to IRQ_TYPE_LEVEL_HIGH is correct and fixes the issue, so +let's do that. + +Fixes: fc539b90eda2 ("arm64: dts: ti: am654: Add DSS node") +Signed-off-by: Tomi Valkeinen +Reviewed-by: Aradhya Bhatia +Link: https://lore.kernel.org/r/20231106-am65-dss-clk-edge-v1-1-4a959fec0e1e@ideasonboard.com +Signed-off-by: Nishanth Menon +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +index ebb1c5ce7aec..83dd8993027a 100644 +--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi ++++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +@@ -856,7 +856,7 @@ dss: dss@4a00000 { + assigned-clocks = <&k3_clks 67 2>; + assigned-clock-parents = <&k3_clks 67 5>; + +- interrupts = ; ++ interrupts = ; + + dma-coherent; + +-- +2.43.0 + diff --git a/queue-6.1/asoc-cs35l33-fix-gpio-name-and-drop-legacy-include.patch b/queue-6.1/asoc-cs35l33-fix-gpio-name-and-drop-legacy-include.patch new file mode 100644 index 00000000000..cec9a142d86 --- /dev/null +++ b/queue-6.1/asoc-cs35l33-fix-gpio-name-and-drop-legacy-include.patch @@ -0,0 +1,64 @@ +From 73fc4bfdeb8096de779af53358fd45438ac28632 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 1 Dec 2023 14:20:31 +0100 +Subject: ASoC: cs35l33: Fix GPIO name and drop legacy include + +From: Linus Walleij + +[ Upstream commit 50678d339d670a92658e5538ebee30447c88ccb3 ] + +This driver includes the legacy GPIO APIs and + but does not use any symbols from any of +them. + +Drop the includes. + +Further the driver is requesting "reset-gpios" rather than +just "reset" from the GPIO framework. This is wrong because +the gpiolib core will add "-gpios" before processing the +request from e.g. device tree. Drop the suffix. + +The last problem means that the optional RESET GPIO has +never been properly retrieved and used even if it existed, +but nobody noticed. + +Fixes: 3333cb7187b9 ("ASoC: cs35l33: Initial commit of the cs35l33 CODEC driver.") +Acked-by: Charles Keepax +Signed-off-by: Linus Walleij +Link: https://lore.kernel.org/r/20231201-descriptors-sound-cirrus-v2-2-ee9f9d4655eb@linaro.org +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/codecs/cs35l33.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +diff --git a/sound/soc/codecs/cs35l33.c b/sound/soc/codecs/cs35l33.c +index 15e79168d256..c3b7046fd29b 100644 +--- a/sound/soc/codecs/cs35l33.c ++++ b/sound/soc/codecs/cs35l33.c +@@ -22,13 +22,11 @@ + #include + #include + #include +-#include + #include + #include + #include + #include + #include +-#include + #include + #include + #include +@@ -1167,7 +1165,7 @@ static int cs35l33_i2c_probe(struct i2c_client *i2c_client) + + /* We could issue !RST or skip it based on AMP topology */ + cs35l33->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev, +- "reset-gpios", GPIOD_OUT_HIGH); ++ "reset", GPIOD_OUT_HIGH); + if (IS_ERR(cs35l33->reset_gpio)) { + dev_err(&i2c_client->dev, "%s ERROR: Can't get reset GPIO\n", + __func__); +-- +2.43.0 + diff --git a/queue-6.1/asoc-cs35l34-fix-gpio-name-and-drop-legacy-include.patch b/queue-6.1/asoc-cs35l34-fix-gpio-name-and-drop-legacy-include.patch new file mode 100644 index 00000000000..1460bdfe355 --- /dev/null +++ b/queue-6.1/asoc-cs35l34-fix-gpio-name-and-drop-legacy-include.patch @@ -0,0 +1,65 @@ +From 8c0fad5a02cf4fb7b85f247fd6a0dfffbb6493c4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 1 Dec 2023 14:20:32 +0100 +Subject: ASoC: cs35l34: Fix GPIO name and drop legacy include + +From: Linus Walleij + +[ Upstream commit a6122b0b4211d132934ef99e7b737910e6d54d2f ] + +This driver includes the legacy GPIO APIs and + but does not use any symbols from any of +them. + +Drop the includes. + +Further the driver is requesting "reset-gpios" rather than +just "reset" from the GPIO framework. This is wrong because +the gpiolib core will add "-gpios" before processing the +request from e.g. device tree. Drop the suffix. + +The last problem means that the optional RESET GPIO has +never been properly retrieved and used even if it existed, +but nobody noticed. + +Fixes: c1124c09e103 ("ASoC: cs35l34: Initial commit of the cs35l34 CODEC driver.") +Acked-by: Charles Keepax +Signed-off-by: Linus Walleij +Link: https://lore.kernel.org/r/20231201-descriptors-sound-cirrus-v2-3-ee9f9d4655eb@linaro.org +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/codecs/cs35l34.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +diff --git a/sound/soc/codecs/cs35l34.c b/sound/soc/codecs/cs35l34.c +index b3f98023e6a7..57d125c03fad 100644 +--- a/sound/soc/codecs/cs35l34.c ++++ b/sound/soc/codecs/cs35l34.c +@@ -20,14 +20,12 @@ + #include + #include + #include +-#include + #include + #include + #include + #include + #include + #include +-#include + #include + #include + #include +@@ -1061,7 +1059,7 @@ static int cs35l34_i2c_probe(struct i2c_client *i2c_client) + dev_err(&i2c_client->dev, "Failed to request IRQ: %d\n", ret); + + cs35l34->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev, +- "reset-gpios", GPIOD_OUT_LOW); ++ "reset", GPIOD_OUT_LOW); + if (IS_ERR(cs35l34->reset_gpio)) { + ret = PTR_ERR(cs35l34->reset_gpio); + goto err_regulator; +-- +2.43.0 + diff --git a/queue-6.1/asoc-intel-glk_rt5682_max98357a-fix-board-id-mismatc.patch b/queue-6.1/asoc-intel-glk_rt5682_max98357a-fix-board-id-mismatc.patch new file mode 100644 index 00000000000..ce7b81c6dba --- /dev/null +++ b/queue-6.1/asoc-intel-glk_rt5682_max98357a-fix-board-id-mismatc.patch @@ -0,0 +1,67 @@ +From 5b2f44dd121c2e56dc9e803f067a47404ee3df32 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Dec 2023 15:41:58 -0600 +Subject: ASoC: Intel: glk_rt5682_max98357a: fix board id mismatch + +From: Brent Lu + +[ Upstream commit 486ede0df82dd74472c6f5651e38ff48f7f766c1 ] + +The drv_name in enumeration table for ALC5682I-VS codec does not match +the board id string in machine driver. Modify the entry of "10EC5682" +to enumerate "RTL5682" as well and remove invalid entry. + +Fixes: 88b4d77d6035 ("ASoC: Intel: glk_rt5682_max98357a: support ALC5682I-VS codec") +Reported-by: Curtis Malainey +Reviewed-by: Curtis Malainey +Reviewed-by: Bard Liao +Signed-off-by: Brent Lu +Signed-off-by: Pierre-Louis Bossart +Link: https://lore.kernel.org/r/20231204214200.203100-4-pierre-louis.bossart@linux.intel.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/intel/common/soc-acpi-intel-glk-match.c | 14 ++++++-------- + 1 file changed, 6 insertions(+), 8 deletions(-) + +diff --git a/sound/soc/intel/common/soc-acpi-intel-glk-match.c b/sound/soc/intel/common/soc-acpi-intel-glk-match.c +index 387e73100884..8911c90bbaf6 100644 +--- a/sound/soc/intel/common/soc-acpi-intel-glk-match.c ++++ b/sound/soc/intel/common/soc-acpi-intel-glk-match.c +@@ -19,6 +19,11 @@ static const struct snd_soc_acpi_codecs glk_codecs = { + .codecs = {"MX98357A"} + }; + ++static const struct snd_soc_acpi_codecs glk_rt5682_rt5682s_hp = { ++ .num_codecs = 2, ++ .codecs = {"10EC5682", "RTL5682"}, ++}; ++ + struct snd_soc_acpi_mach snd_soc_acpi_intel_glk_machines[] = { + { + .id = "INT343A", +@@ -35,20 +40,13 @@ struct snd_soc_acpi_mach snd_soc_acpi_intel_glk_machines[] = { + .sof_tplg_filename = "sof-glk-da7219.tplg", + }, + { +- .id = "10EC5682", ++ .comp_ids = &glk_rt5682_rt5682s_hp, + .drv_name = "glk_rt5682_mx98357a", + .fw_filename = "intel/dsp_fw_glk.bin", + .machine_quirk = snd_soc_acpi_codec_list, + .quirk_data = &glk_codecs, + .sof_tplg_filename = "sof-glk-rt5682.tplg", + }, +- { +- .id = "RTL5682", +- .drv_name = "glk_rt5682_max98357a", +- .machine_quirk = snd_soc_acpi_codec_list, +- .quirk_data = &glk_codecs, +- .sof_tplg_filename = "sof-glk-rt5682.tplg", +- }, + { + .id = "10134242", + .drv_name = "glk_cs4242_mx98357a", +-- +2.43.0 + diff --git a/queue-6.1/asoc-rt5645-drop-double-ef20-entry-from-dmi_platform.patch b/queue-6.1/asoc-rt5645-drop-double-ef20-entry-from-dmi_platform.patch new file mode 100644 index 00000000000..e37f5853270 --- /dev/null +++ b/queue-6.1/asoc-rt5645-drop-double-ef20-entry-from-dmi_platform.patch @@ -0,0 +1,53 @@ +From 5045b61976847f960345851e15dc6202834c1b36 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 26 Nov 2023 22:40:18 +0100 +Subject: ASoC: rt5645: Drop double EF20 entry from dmi_platform_data[] + +From: Hans de Goede + +[ Upstream commit 51add1687f39292af626ac3c2046f49241713273 ] + +dmi_platform_data[] first contains a DMI entry matching: + + DMI_MATCH(DMI_PRODUCT_NAME, "EF20"), + +and then contains an identical entry except for the match being: + + DMI_MATCH(DMI_PRODUCT_NAME, "EF20EA"), + +Since these are partial (non exact) DMI matches the first match +will also match any board with "EF20EA" in their DMI product-name, +drop the second, redundant, entry. + +Fixes: a4dae468cfdd ("ASoC: rt5645: Add ACPI-defined GPIO for ECS EF20 series") +Cc: Chris Chiu +Signed-off-by: Hans de Goede +Link: https://msgid.link/r/20231126214024.300505-2-hdegoede@redhat.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/codecs/rt5645.c | 8 -------- + 1 file changed, 8 deletions(-) + +diff --git a/sound/soc/codecs/rt5645.c b/sound/soc/codecs/rt5645.c +index 60518ee5a86e..fd3dca08460b 100644 +--- a/sound/soc/codecs/rt5645.c ++++ b/sound/soc/codecs/rt5645.c +@@ -3827,14 +3827,6 @@ static const struct dmi_system_id dmi_platform_data[] = { + }, + .driver_data = (void *)&ecs_ef20_platform_data, + }, +- { +- .ident = "EF20EA", +- .callback = cht_rt5645_ef20_quirk_cb, +- .matches = { +- DMI_MATCH(DMI_PRODUCT_NAME, "EF20EA"), +- }, +- .driver_data = (void *)&ecs_ef20_platform_data, +- }, + { } + }; + +-- +2.43.0 + diff --git a/queue-6.1/block-add-check-of-minors-and-first_minor-in-device_.patch b/queue-6.1/block-add-check-of-minors-and-first_minor-in-device_.patch new file mode 100644 index 00000000000..cb3dc18629d --- /dev/null +++ b/queue-6.1/block-add-check-of-minors-and-first_minor-in-device_.patch @@ -0,0 +1,45 @@ +From 3a5fa9e452dfb74d36015bf8adf48d07baaf016b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 19 Dec 2023 15:59:42 +0800 +Subject: block: add check of 'minors' and 'first_minor' in device_add_disk() + +From: Li Nan + +[ Upstream commit 4c434392c4777881d01beada6701eff8c76b43fe ] + +'first_minor' represents the starting minor number of disks, and +'minors' represents the number of partitions in the device. Neither +of them can be greater than MINORMASK + 1. + +Commit e338924bd05d ("block: check minor range in device_add_disk()") +only added the check of 'first_minor + minors'. However, their sum might +be less than MINORMASK but their values are wrong. Complete the checks now. + +Fixes: e338924bd05d ("block: check minor range in device_add_disk()") +Signed-off-by: Li Nan +Reviewed-by: Christoph Hellwig +Link: https://lore.kernel.org/r/20231219075942.840255-1-linan666@huaweicloud.com +Signed-off-by: Jens Axboe +Signed-off-by: Sasha Levin +--- + block/genhd.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/block/genhd.c b/block/genhd.c +index 5b23f2c3d692..8e9d162cbdbd 100644 +--- a/block/genhd.c ++++ b/block/genhd.c +@@ -444,7 +444,9 @@ int __must_check device_add_disk(struct device *parent, struct gendisk *disk, + DISK_MAX_PARTS); + disk->minors = DISK_MAX_PARTS; + } +- if (disk->first_minor + disk->minors > MINORMASK + 1) ++ if (disk->first_minor > MINORMASK || ++ disk->minors > MINORMASK + 1 || ++ disk->first_minor + disk->minors > MINORMASK + 1) + goto out_exit_elevator; + } else { + if (WARN_ON(disk->minors)) +-- +2.43.0 + diff --git a/queue-6.1/block-make-blk_def_max_sectors-unsigned.patch b/queue-6.1/block-make-blk_def_max_sectors-unsigned.patch new file mode 100644 index 00000000000..2448082e57a --- /dev/null +++ b/queue-6.1/block-make-blk_def_max_sectors-unsigned.patch @@ -0,0 +1,75 @@ +From 6a8efbfdb9b4e671a47223f2be6f03a01133a243 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 5 Jan 2023 12:51:45 -0800 +Subject: block: make BLK_DEF_MAX_SECTORS unsigned + +From: Keith Busch + +[ Upstream commit 0a26f327e46c203229e72c823dfec71a2b405ec5 ] + +This is used as an unsigned value, so define it that way to avoid +having to cast it. + +Suggested-by: Christoph Hellwig +Signed-off-by: Keith Busch +Reviewed-by: Christoph Hellwig +Reviewed-by: Bart Van Assche +Reviewed-by: Martin K. Petersen +Link: https://lore.kernel.org/r/20230105205146.3610282-2-kbusch@meta.com +Signed-off-by: Jens Axboe +Stable-dep-of: 9a9525de8654 ("null_blk: don't cap max_hw_sectors to BLK_DEF_MAX_SECTORS") +Signed-off-by: Sasha Levin +--- + block/blk-settings.c | 2 +- + drivers/block/null_blk/main.c | 3 +-- + include/linux/blkdev.h | 3 ++- + 3 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/block/blk-settings.c b/block/blk-settings.c +index 86ff375c00ce..bbca4ce77a2d 100644 +--- a/block/blk-settings.c ++++ b/block/blk-settings.c +@@ -135,7 +135,7 @@ void blk_queue_max_hw_sectors(struct request_queue *q, unsigned int max_hw_secto + limits->max_hw_sectors = max_hw_sectors; + + max_sectors = min_not_zero(max_hw_sectors, limits->max_dev_sectors); +- max_sectors = min_t(unsigned int, max_sectors, BLK_DEF_MAX_SECTORS); ++ max_sectors = min(max_sectors, BLK_DEF_MAX_SECTORS); + max_sectors = round_down(max_sectors, + limits->logical_block_size >> SECTOR_SHIFT); + limits->max_sectors = max_sectors; +diff --git a/drivers/block/null_blk/main.c b/drivers/block/null_blk/main.c +index e9f38eba2f13..d921653b096b 100644 +--- a/drivers/block/null_blk/main.c ++++ b/drivers/block/null_blk/main.c +@@ -2116,8 +2116,7 @@ static int null_add_dev(struct nullb_device *dev) + blk_queue_physical_block_size(nullb->q, dev->blocksize); + if (!dev->max_sectors) + dev->max_sectors = queue_max_hw_sectors(nullb->q); +- dev->max_sectors = min_t(unsigned int, dev->max_sectors, +- BLK_DEF_MAX_SECTORS); ++ dev->max_sectors = min(dev->max_sectors, BLK_DEF_MAX_SECTORS); + blk_queue_max_hw_sectors(nullb->q, dev->max_sectors); + + if (dev->virt_boundary) +diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h +index 07a7eeef47d3..e255674a9ee7 100644 +--- a/include/linux/blkdev.h ++++ b/include/linux/blkdev.h +@@ -1109,11 +1109,12 @@ static inline bool bdev_is_partition(struct block_device *bdev) + enum blk_default_limits { + BLK_MAX_SEGMENTS = 128, + BLK_SAFE_MAX_SECTORS = 255, +- BLK_DEF_MAX_SECTORS = 2560, + BLK_MAX_SEGMENT_SIZE = 65536, + BLK_SEG_BOUNDARY_MASK = 0xFFFFFFFFUL, + }; + ++#define BLK_DEF_MAX_SECTORS 2560u ++ + static inline unsigned long queue_segment_boundary(const struct request_queue *q) + { + return q->limits.seg_boundary_mask; +-- +2.43.0 + diff --git a/queue-6.1/block-set-memalloc_noio-to-false-on-device_add_disk-.patch b/queue-6.1/block-set-memalloc_noio-to-false-on-device_add_disk-.patch new file mode 100644 index 00000000000..0b23fcd8f70 --- /dev/null +++ b/queue-6.1/block-set-memalloc_noio-to-false-on-device_add_disk-.patch @@ -0,0 +1,39 @@ +From 7670177e4eb17eee339578de1ed085278dc09538 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 11 Dec 2023 15:53:56 +0800 +Subject: block: Set memalloc_noio to false on device_add_disk() error path + +From: Li Nan + +[ Upstream commit 5fa3d1a00c2d4ba14f1300371ad39d5456e890d7 ] + +On the error path of device_add_disk(), device's memalloc_noio flag was +set but not cleared. As the comment of pm_runtime_set_memalloc_noio(), +"The function should be called between device_add() and device_del()". +Clear this flag before device_del() now. + +Fixes: 25e823c8c37d ("block/genhd.c: apply pm_runtime_set_memalloc_noio on block devices") +Signed-off-by: Li Nan +Reviewed-by: Christoph Hellwig +Link: https://lore.kernel.org/r/20231211075356.1839282-1-linan666@huaweicloud.com +Signed-off-by: Jens Axboe +Signed-off-by: Sasha Levin +--- + block/genhd.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/block/genhd.c b/block/genhd.c +index 886e75213f6a..5b23f2c3d692 100644 +--- a/block/genhd.c ++++ b/block/genhd.c +@@ -564,6 +564,7 @@ int __must_check device_add_disk(struct device *parent, struct gendisk *disk, + blk_integrity_del(disk); + out_del_block_link: + sysfs_remove_link(block_depr, dev_name(ddev)); ++ pm_runtime_set_memalloc_noio(ddev, false); + out_device_del: + device_del(ddev); + out_free_ext_minor: +-- +2.43.0 + diff --git a/queue-6.1/blocklayoutdriver-fix-reference-leak-of-pnfs_device_.patch b/queue-6.1/blocklayoutdriver-fix-reference-leak-of-pnfs_device_.patch new file mode 100644 index 00000000000..b781c8c3f77 --- /dev/null +++ b/queue-6.1/blocklayoutdriver-fix-reference-leak-of-pnfs_device_.patch @@ -0,0 +1,37 @@ +From d21f62e6aa9e83c4eb5bebb1bc60d0578787d83e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 5 Dec 2023 10:05:01 -0500 +Subject: blocklayoutdriver: Fix reference leak of pnfs_device_node + +From: Benjamin Coddington + +[ Upstream commit 1530827b90025cdf80c9b0d07a166d045a0a7b81 ] + +The error path for blocklayout's device lookup is missing a reference drop +for the case where a lookup finds the device, but the device is marked with +NFS_DEVICEID_UNAVAILABLE. + +Fixes: b3dce6a2f060 ("pnfs/blocklayout: handle transient devices") +Signed-off-by: Benjamin Coddington +Signed-off-by: Anna Schumaker +Signed-off-by: Sasha Levin +--- + fs/nfs/blocklayout/blocklayout.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/fs/nfs/blocklayout/blocklayout.c b/fs/nfs/blocklayout/blocklayout.c +index 943aeea1eb16..1d1d7abc3205 100644 +--- a/fs/nfs/blocklayout/blocklayout.c ++++ b/fs/nfs/blocklayout/blocklayout.c +@@ -580,6 +580,8 @@ bl_find_get_deviceid(struct nfs_server *server, + nfs4_delete_deviceid(node->ld, node->nfs_client, id); + goto retry; + } ++ ++ nfs4_put_deviceid_node(node); + return ERR_PTR(-ENODEV); + } + +-- +2.43.0 + diff --git a/queue-6.1/bluetooth-btmtkuart-fix-recv_buf-return-value.patch b/queue-6.1/bluetooth-btmtkuart-fix-recv_buf-return-value.patch new file mode 100644 index 00000000000..52b67bfad38 --- /dev/null +++ b/queue-6.1/bluetooth-btmtkuart-fix-recv_buf-return-value.patch @@ -0,0 +1,68 @@ +From 76465184dd8bf1e12f26198441b8eed4e6ea445d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 11 Dec 2023 17:40:19 +0100 +Subject: Bluetooth: btmtkuart: fix recv_buf() return value + +From: Francesco Dolcini + +[ Upstream commit 64057f051f20c2a2184b9db7f8037d928d68a4f4 ] + +Serdev recv_buf() callback is supposed to return the amount of bytes +consumed, therefore an int in between 0 and count. + +Do not return negative number in case of issue, just print an error and +return count. This fixes a WARN in ttyport_receive_buf(). + +Link: https://lore.kernel.org/all/087be419-ec6b-47ad-851a-5e1e3ea5cfcc@kernel.org/ +Fixes: 7237c4c9ec92 ("Bluetooth: mediatek: Add protocol support for MediaTek serial devices") +Signed-off-by: Francesco Dolcini +Signed-off-by: Luiz Augusto von Dentz +Signed-off-by: Sasha Levin +--- + drivers/bluetooth/btmtkuart.c | 11 +++-------- + 1 file changed, 3 insertions(+), 8 deletions(-) + +diff --git a/drivers/bluetooth/btmtkuart.c b/drivers/bluetooth/btmtkuart.c +index c98691cdbbd5..04b72394dda5 100644 +--- a/drivers/bluetooth/btmtkuart.c ++++ b/drivers/bluetooth/btmtkuart.c +@@ -337,7 +337,7 @@ mtk_stp_split(struct btmtkuart_dev *bdev, const unsigned char *data, int count, + return data; + } + +-static int btmtkuart_recv(struct hci_dev *hdev, const u8 *data, size_t count) ++static void btmtkuart_recv(struct hci_dev *hdev, const u8 *data, size_t count) + { + struct btmtkuart_dev *bdev = hci_get_drvdata(hdev); + const unsigned char *p_left = data, *p_h4; +@@ -376,25 +376,20 @@ static int btmtkuart_recv(struct hci_dev *hdev, const u8 *data, size_t count) + bt_dev_err(bdev->hdev, + "Frame reassembly failed (%d)", err); + bdev->rx_skb = NULL; +- return err; ++ return; + } + + sz_left -= sz_h4; + p_left += sz_h4; + } +- +- return 0; + } + + static int btmtkuart_receive_buf(struct serdev_device *serdev, const u8 *data, + size_t count) + { + struct btmtkuart_dev *bdev = serdev_device_get_drvdata(serdev); +- int err; + +- err = btmtkuart_recv(bdev->hdev, data, count); +- if (err < 0) +- return err; ++ btmtkuart_recv(bdev->hdev, data, count); + + bdev->hdev->stat.byte_rx += count; + +-- +2.43.0 + diff --git a/queue-6.1/bluetooth-fix-bogus-check-for-re-auth-no-supported-w.patch b/queue-6.1/bluetooth-fix-bogus-check-for-re-auth-no-supported-w.patch new file mode 100644 index 00000000000..8be4b789723 --- /dev/null +++ b/queue-6.1/bluetooth-fix-bogus-check-for-re-auth-no-supported-w.patch @@ -0,0 +1,88 @@ +From 74eff1a4e01b38bbf6589b12a88d5b22193f7163 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 30 Nov 2023 14:58:03 +0100 +Subject: Bluetooth: Fix bogus check for re-auth no supported with non-ssp + +From: Luiz Augusto von Dentz + +[ Upstream commit d03376c185926098cb4d668d6458801eb785c0a5 ] + +This reverts 19f8def031bfa50c579149b200bfeeb919727b27 +"Bluetooth: Fix auth_complete_evt for legacy units" which seems to be +working around a bug on a broken controller rather then any limitation +imposed by the Bluetooth spec, in fact if there ws not possible to +re-auth the command shall fail not succeed. + +Fixes: 19f8def031bf ("Bluetooth: Fix auth_complete_evt for legacy units") +Signed-off-by: Luiz Augusto von Dentz +Signed-off-by: Sasha Levin +--- + include/net/bluetooth/hci_core.h | 1 - + net/bluetooth/hci_conn.c | 8 +++----- + net/bluetooth/hci_event.c | 11 ++--------- + 3 files changed, 5 insertions(+), 15 deletions(-) + +diff --git a/include/net/bluetooth/hci_core.h b/include/net/bluetooth/hci_core.h +index 5f8a534b6574..09c978f3d95d 100644 +--- a/include/net/bluetooth/hci_core.h ++++ b/include/net/bluetooth/hci_core.h +@@ -942,7 +942,6 @@ void hci_inquiry_cache_flush(struct hci_dev *hdev); + /* ----- HCI Connections ----- */ + enum { + HCI_CONN_AUTH_PEND, +- HCI_CONN_REAUTH_PEND, + HCI_CONN_ENCRYPT_PEND, + HCI_CONN_RSWITCH_PEND, + HCI_CONN_MODE_CHANGE_PEND, +diff --git a/net/bluetooth/hci_conn.c b/net/bluetooth/hci_conn.c +index 55e0ecd88543..12d36875358b 100644 +--- a/net/bluetooth/hci_conn.c ++++ b/net/bluetooth/hci_conn.c +@@ -2314,12 +2314,10 @@ static int hci_conn_auth(struct hci_conn *conn, __u8 sec_level, __u8 auth_type) + hci_send_cmd(conn->hdev, HCI_OP_AUTH_REQUESTED, + sizeof(cp), &cp); + +- /* If we're already encrypted set the REAUTH_PEND flag, +- * otherwise set the ENCRYPT_PEND. ++ /* Set the ENCRYPT_PEND to trigger encryption after ++ * authentication. + */ +- if (test_bit(HCI_CONN_ENCRYPT, &conn->flags)) +- set_bit(HCI_CONN_REAUTH_PEND, &conn->flags); +- else ++ if (!test_bit(HCI_CONN_ENCRYPT, &conn->flags)) + set_bit(HCI_CONN_ENCRYPT_PEND, &conn->flags); + } + +diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c +index dcb13c64e8e7..56ecc5f97b91 100644 +--- a/net/bluetooth/hci_event.c ++++ b/net/bluetooth/hci_event.c +@@ -3511,14 +3511,8 @@ static void hci_auth_complete_evt(struct hci_dev *hdev, void *data, + + if (!ev->status) { + clear_bit(HCI_CONN_AUTH_FAILURE, &conn->flags); +- +- if (!hci_conn_ssp_enabled(conn) && +- test_bit(HCI_CONN_REAUTH_PEND, &conn->flags)) { +- bt_dev_info(hdev, "re-auth of legacy device is not possible."); +- } else { +- set_bit(HCI_CONN_AUTH, &conn->flags); +- conn->sec_level = conn->pending_sec_level; +- } ++ set_bit(HCI_CONN_AUTH, &conn->flags); ++ conn->sec_level = conn->pending_sec_level; + } else { + if (ev->status == HCI_ERROR_PIN_OR_KEY_MISSING) + set_bit(HCI_CONN_AUTH_FAILURE, &conn->flags); +@@ -3527,7 +3521,6 @@ static void hci_auth_complete_evt(struct hci_dev *hdev, void *data, + } + + clear_bit(HCI_CONN_AUTH_PEND, &conn->flags); +- clear_bit(HCI_CONN_REAUTH_PEND, &conn->flags); + + if (conn->state == BT_CONFIG) { + if (!ev->status && hci_conn_ssp_enabled(conn)) { +-- +2.43.0 + diff --git a/queue-6.1/bpf-add-crosstask-check-to-__bpf_get_stack.patch b/queue-6.1/bpf-add-crosstask-check-to-__bpf_get_stack.patch new file mode 100644 index 00000000000..9ebb81f81ed --- /dev/null +++ b/queue-6.1/bpf-add-crosstask-check-to-__bpf_get_stack.patch @@ -0,0 +1,121 @@ +From e8568aac933a75135d583342a4c89eba758ac7f9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 8 Nov 2023 03:23:34 -0800 +Subject: bpf: Add crosstask check to __bpf_get_stack + +From: Jordan Rome + +[ Upstream commit b8e3a87a627b575896e448021e5c2f8a3bc19931 ] + +Currently get_perf_callchain only supports user stack walking for +the current task. Passing the correct *crosstask* param will return +0 frames if the task passed to __bpf_get_stack isn't the current +one instead of a single incorrect frame/address. This change +passes the correct *crosstask* param but also does a preemptive +check in __bpf_get_stack if the task is current and returns +-EOPNOTSUPP if it is not. + +This issue was found using bpf_get_task_stack inside a BPF +iterator ("iter/task"), which iterates over all tasks. +bpf_get_task_stack works fine for fetching kernel stacks +but because get_perf_callchain relies on the caller to know +if the requested *task* is the current one (via *crosstask*) +it was failing in a confusing way. + +It might be possible to get user stacks for all tasks utilizing +something like access_process_vm but that requires the bpf +program calling bpf_get_task_stack to be sleepable and would +therefore be a breaking change. + +Fixes: fa28dcb82a38 ("bpf: Introduce helper bpf_get_task_stack()") +Signed-off-by: Jordan Rome +Signed-off-by: Andrii Nakryiko +Link: https://lore.kernel.org/bpf/20231108112334.3433136-1-jordalgo@meta.com +Signed-off-by: Sasha Levin +--- + include/uapi/linux/bpf.h | 3 +++ + kernel/bpf/stackmap.c | 11 ++++++++++- + tools/include/uapi/linux/bpf.h | 3 +++ + 3 files changed, 16 insertions(+), 1 deletion(-) + +diff --git a/include/uapi/linux/bpf.h b/include/uapi/linux/bpf.h +index 92dbe89dafbf..201dc77ebbd7 100644 +--- a/include/uapi/linux/bpf.h ++++ b/include/uapi/linux/bpf.h +@@ -4353,6 +4353,8 @@ union bpf_attr { + * long bpf_get_task_stack(struct task_struct *task, void *buf, u32 size, u64 flags) + * Description + * Return a user or a kernel stack in bpf program provided buffer. ++ * Note: the user stack will only be populated if the *task* is ++ * the current task; all other tasks will return -EOPNOTSUPP. + * To achieve this, the helper needs *task*, which is a valid + * pointer to **struct task_struct**. To store the stacktrace, the + * bpf program provides *buf* with a nonnegative *size*. +@@ -4364,6 +4366,7 @@ union bpf_attr { + * + * **BPF_F_USER_STACK** + * Collect a user space stack instead of a kernel stack. ++ * The *task* must be the current task. + * **BPF_F_USER_BUILD_ID** + * Collect buildid+offset instead of ips for user stack, + * only valid if **BPF_F_USER_STACK** is also specified. +diff --git a/kernel/bpf/stackmap.c b/kernel/bpf/stackmap.c +index aecea7451b61..f86db3cf7212 100644 +--- a/kernel/bpf/stackmap.c ++++ b/kernel/bpf/stackmap.c +@@ -391,6 +391,7 @@ static long __bpf_get_stack(struct pt_regs *regs, struct task_struct *task, + { + u32 trace_nr, copy_len, elem_size, num_elem, max_depth; + bool user_build_id = flags & BPF_F_USER_BUILD_ID; ++ bool crosstask = task && task != current; + u32 skip = flags & BPF_F_SKIP_FIELD_MASK; + bool user = flags & BPF_F_USER_STACK; + struct perf_callchain_entry *trace; +@@ -413,6 +414,14 @@ static long __bpf_get_stack(struct pt_regs *regs, struct task_struct *task, + if (task && user && !user_mode(regs)) + goto err_fault; + ++ /* get_perf_callchain does not support crosstask user stack walking ++ * but returns an empty stack instead of NULL. ++ */ ++ if (crosstask && user) { ++ err = -EOPNOTSUPP; ++ goto clear; ++ } ++ + num_elem = size / elem_size; + max_depth = num_elem + skip; + if (sysctl_perf_event_max_stack < max_depth) +@@ -424,7 +433,7 @@ static long __bpf_get_stack(struct pt_regs *regs, struct task_struct *task, + trace = get_callchain_entry_for_task(task, max_depth); + else + trace = get_perf_callchain(regs, 0, kernel, user, max_depth, +- false, false); ++ crosstask, false); + if (unlikely(!trace)) + goto err_fault; + +diff --git a/tools/include/uapi/linux/bpf.h b/tools/include/uapi/linux/bpf.h +index 92dbe89dafbf..201dc77ebbd7 100644 +--- a/tools/include/uapi/linux/bpf.h ++++ b/tools/include/uapi/linux/bpf.h +@@ -4353,6 +4353,8 @@ union bpf_attr { + * long bpf_get_task_stack(struct task_struct *task, void *buf, u32 size, u64 flags) + * Description + * Return a user or a kernel stack in bpf program provided buffer. ++ * Note: the user stack will only be populated if the *task* is ++ * the current task; all other tasks will return -EOPNOTSUPP. + * To achieve this, the helper needs *task*, which is a valid + * pointer to **struct task_struct**. To store the stacktrace, the + * bpf program provides *buf* with a nonnegative *size*. +@@ -4364,6 +4366,7 @@ union bpf_attr { + * + * **BPF_F_USER_STACK** + * Collect a user space stack instead of a kernel stack. ++ * The *task* must be the current task. + * **BPF_F_USER_BUILD_ID** + * Collect buildid+offset instead of ips for user stack, + * only valid if **BPF_F_USER_STACK** is also specified. +-- +2.43.0 + diff --git a/queue-6.1/bpf-add-map-and-need_defer-parameters-to-.map_fd_put.patch b/queue-6.1/bpf-add-map-and-need_defer-parameters-to-.map_fd_put.patch new file mode 100644 index 00000000000..a629d246dd8 --- /dev/null +++ b/queue-6.1/bpf-add-map-and-need_defer-parameters-to-.map_fd_put.patch @@ -0,0 +1,174 @@ +From d4583a4f366f28b22ae3c98878b4b7f7030185a8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Dec 2023 22:04:20 +0800 +Subject: bpf: Add map and need_defer parameters to .map_fd_put_ptr() + +From: Hou Tao + +[ Upstream commit 20c20bd11a0702ce4dc9300c3da58acf551d9725 ] + +map is the pointer of outer map, and need_defer needs some explanation. +need_defer tells the implementation to defer the reference release of +the passed element and ensure that the element is still alive before +the bpf program, which may manipulate it, exits. + +The following three cases will invoke map_fd_put_ptr() and different +need_defer values will be passed to these callers: + +1) release the reference of the old element in the map during map update + or map deletion. The release must be deferred, otherwise the bpf + program may incur use-after-free problem, so need_defer needs to be + true. +2) release the reference of the to-be-added element in the error path of + map update. The to-be-added element is not visible to any bpf + program, so it is OK to pass false for need_defer parameter. +3) release the references of all elements in the map during map release. + Any bpf program which has access to the map must have been exited and + released, so need_defer=false will be OK. + +These two parameters will be used by the following patches to fix the +potential use-after-free problem for map-in-map. + +Signed-off-by: Hou Tao +Link: https://lore.kernel.org/r/20231204140425.1480317-3-houtao@huaweicloud.com +Signed-off-by: Alexei Starovoitov +Stable-dep-of: 876673364161 ("bpf: Defer the free of inner map when necessary") +Signed-off-by: Sasha Levin +--- + include/linux/bpf.h | 6 +++++- + kernel/bpf/arraymap.c | 12 +++++++----- + kernel/bpf/hashtab.c | 6 +++--- + kernel/bpf/map_in_map.c | 2 +- + kernel/bpf/map_in_map.h | 2 +- + 5 files changed, 17 insertions(+), 11 deletions(-) + +diff --git a/include/linux/bpf.h b/include/linux/bpf.h +index 21b192ce018a..47420a973e58 100644 +--- a/include/linux/bpf.h ++++ b/include/linux/bpf.h +@@ -102,7 +102,11 @@ struct bpf_map_ops { + /* funcs called by prog_array and perf_event_array map */ + void *(*map_fd_get_ptr)(struct bpf_map *map, struct file *map_file, + int fd); +- void (*map_fd_put_ptr)(void *ptr); ++ /* If need_defer is true, the implementation should guarantee that ++ * the to-be-put element is still alive before the bpf program, which ++ * may manipulate it, exists. ++ */ ++ void (*map_fd_put_ptr)(struct bpf_map *map, void *ptr, bool need_defer); + int (*map_gen_lookup)(struct bpf_map *map, struct bpf_insn *insn_buf); + u32 (*map_fd_sys_lookup_elem)(void *ptr); + void (*map_seq_show_elem)(struct bpf_map *map, void *key, +diff --git a/kernel/bpf/arraymap.c b/kernel/bpf/arraymap.c +index 00f23febb9a7..c04e69f34e4d 100644 +--- a/kernel/bpf/arraymap.c ++++ b/kernel/bpf/arraymap.c +@@ -852,7 +852,7 @@ int bpf_fd_array_map_update_elem(struct bpf_map *map, struct file *map_file, + } + + if (old_ptr) +- map->ops->map_fd_put_ptr(old_ptr); ++ map->ops->map_fd_put_ptr(map, old_ptr, true); + return 0; + } + +@@ -875,7 +875,7 @@ static int fd_array_map_delete_elem(struct bpf_map *map, void *key) + } + + if (old_ptr) { +- map->ops->map_fd_put_ptr(old_ptr); ++ map->ops->map_fd_put_ptr(map, old_ptr, true); + return 0; + } else { + return -ENOENT; +@@ -898,8 +898,9 @@ static void *prog_fd_array_get_ptr(struct bpf_map *map, + return prog; + } + +-static void prog_fd_array_put_ptr(void *ptr) ++static void prog_fd_array_put_ptr(struct bpf_map *map, void *ptr, bool need_defer) + { ++ /* bpf_prog is freed after one RCU or tasks trace grace period */ + bpf_prog_put(ptr); + } + +@@ -1185,8 +1186,9 @@ static void *perf_event_fd_array_get_ptr(struct bpf_map *map, + return ee; + } + +-static void perf_event_fd_array_put_ptr(void *ptr) ++static void perf_event_fd_array_put_ptr(struct bpf_map *map, void *ptr, bool need_defer) + { ++ /* bpf_perf_event is freed after one RCU grace period */ + bpf_event_entry_free_rcu(ptr); + } + +@@ -1239,7 +1241,7 @@ static void *cgroup_fd_array_get_ptr(struct bpf_map *map, + return cgroup_get_from_fd(fd); + } + +-static void cgroup_fd_array_put_ptr(void *ptr) ++static void cgroup_fd_array_put_ptr(struct bpf_map *map, void *ptr, bool need_defer) + { + /* cgroup_put free cgrp after a rcu grace period */ + cgroup_put(ptr); +diff --git a/kernel/bpf/hashtab.c b/kernel/bpf/hashtab.c +index ce0051eee746..88c71de0a0a9 100644 +--- a/kernel/bpf/hashtab.c ++++ b/kernel/bpf/hashtab.c +@@ -880,7 +880,7 @@ static void htab_put_fd_value(struct bpf_htab *htab, struct htab_elem *l) + + if (map->ops->map_fd_put_ptr) { + ptr = fd_htab_map_get_ptr(map, l); +- map->ops->map_fd_put_ptr(ptr); ++ map->ops->map_fd_put_ptr(map, ptr, true); + } + } + +@@ -2424,7 +2424,7 @@ static void fd_htab_map_free(struct bpf_map *map) + hlist_nulls_for_each_entry_safe(l, n, head, hash_node) { + void *ptr = fd_htab_map_get_ptr(map, l); + +- map->ops->map_fd_put_ptr(ptr); ++ map->ops->map_fd_put_ptr(map, ptr, false); + } + } + +@@ -2465,7 +2465,7 @@ int bpf_fd_htab_map_update_elem(struct bpf_map *map, struct file *map_file, + + ret = htab_map_update_elem(map, key, &ptr, map_flags); + if (ret) +- map->ops->map_fd_put_ptr(ptr); ++ map->ops->map_fd_put_ptr(map, ptr, false); + + return ret; + } +diff --git a/kernel/bpf/map_in_map.c b/kernel/bpf/map_in_map.c +index 8e87f69aae60..47ecc4818c93 100644 +--- a/kernel/bpf/map_in_map.c ++++ b/kernel/bpf/map_in_map.c +@@ -115,7 +115,7 @@ void *bpf_map_fd_get_ptr(struct bpf_map *map, + return inner_map; + } + +-void bpf_map_fd_put_ptr(void *ptr) ++void bpf_map_fd_put_ptr(struct bpf_map *map, void *ptr, bool need_defer) + { + /* ptr->ops->map_free() has to go through one + * rcu grace period by itself. +diff --git a/kernel/bpf/map_in_map.h b/kernel/bpf/map_in_map.h +index bcb7534afb3c..7d61602354de 100644 +--- a/kernel/bpf/map_in_map.h ++++ b/kernel/bpf/map_in_map.h +@@ -13,7 +13,7 @@ struct bpf_map *bpf_map_meta_alloc(int inner_map_ufd); + void bpf_map_meta_free(struct bpf_map *map_meta); + void *bpf_map_fd_get_ptr(struct bpf_map *map, struct file *map_file, + int ufd); +-void bpf_map_fd_put_ptr(void *ptr); ++void bpf_map_fd_put_ptr(struct bpf_map *map, void *ptr, bool need_defer); + u32 bpf_map_fd_sys_lookup_elem(void *ptr); + + #endif +-- +2.43.0 + diff --git a/queue-6.1/bpf-add-percpu-stats-for-bpf_map-elements-insertions.patch b/queue-6.1/bpf-add-percpu-stats-for-bpf_map-elements-insertions.patch new file mode 100644 index 00000000000..5211de40793 --- /dev/null +++ b/queue-6.1/bpf-add-percpu-stats-for-bpf_map-elements-insertions.patch @@ -0,0 +1,77 @@ +From 4fcd45cc2334be78cdb680b7c4d08d1bc16a3b3e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 6 Jul 2023 13:39:28 +0000 +Subject: bpf: add percpu stats for bpf_map elements insertions/deletions + +From: Anton Protopopov + +[ Upstream commit 25954730461af01f66afa9e17036b051986b007e ] + +Add a generic percpu stats for bpf_map elements insertions/deletions in order +to keep track of both, the current (approximate) number of elements in a map +and per-cpu statistics on update/delete operations. + +To expose these stats a particular map implementation should initialize the +counter and adjust it as needed using the 'bpf_map_*_elem_count' helpers +provided by this commit. + +Signed-off-by: Anton Protopopov +Link: https://lore.kernel.org/r/20230706133932.45883-2-aspsk@isovalent.com +Signed-off-by: Alexei Starovoitov +Stable-dep-of: 876673364161 ("bpf: Defer the free of inner map when necessary") +Signed-off-by: Sasha Levin +--- + include/linux/bpf.h | 30 ++++++++++++++++++++++++++++++ + 1 file changed, 30 insertions(+) + +diff --git a/include/linux/bpf.h b/include/linux/bpf.h +index ba22cf4f5fc0..21b192ce018a 100644 +--- a/include/linux/bpf.h ++++ b/include/linux/bpf.h +@@ -249,6 +249,7 @@ struct bpf_map { + } owner; + bool bypass_spec_v1; + bool frozen; /* write-once; write-protected by freeze_mutex */ ++ s64 __percpu *elem_count; + }; + + static inline bool map_value_has_spin_lock(const struct bpf_map *map) +@@ -1791,6 +1792,35 @@ bpf_map_alloc_percpu(const struct bpf_map *map, size_t size, size_t align, + } + #endif + ++static inline int ++bpf_map_init_elem_count(struct bpf_map *map) ++{ ++ size_t size = sizeof(*map->elem_count), align = size; ++ gfp_t flags = GFP_USER | __GFP_NOWARN; ++ ++ map->elem_count = bpf_map_alloc_percpu(map, size, align, flags); ++ if (!map->elem_count) ++ return -ENOMEM; ++ ++ return 0; ++} ++ ++static inline void ++bpf_map_free_elem_count(struct bpf_map *map) ++{ ++ free_percpu(map->elem_count); ++} ++ ++static inline void bpf_map_inc_elem_count(struct bpf_map *map) ++{ ++ this_cpu_inc(*map->elem_count); ++} ++ ++static inline void bpf_map_dec_elem_count(struct bpf_map *map) ++{ ++ this_cpu_dec(*map->elem_count); ++} ++ + extern int sysctl_unprivileged_bpf_disabled; + + static inline bool bpf_allow_ptr_leaks(void) +-- +2.43.0 + diff --git a/queue-6.1/bpf-defer-the-free-of-inner-map-when-necessary.patch b/queue-6.1/bpf-defer-the-free-of-inner-map-when-necessary.patch new file mode 100644 index 00000000000..99e0dd05a5d --- /dev/null +++ b/queue-6.1/bpf-defer-the-free-of-inner-map-when-necessary.patch @@ -0,0 +1,141 @@ +From 78112dcfc9d0be828362408a7c0dde19dbbf93eb Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Dec 2023 22:04:22 +0800 +Subject: bpf: Defer the free of inner map when necessary + +From: Hou Tao + +[ Upstream commit 876673364161da50eed6b472d746ef88242b2368 ] + +When updating or deleting an inner map in map array or map htab, the map +may still be accessed by non-sleepable program or sleepable program. +However bpf_map_fd_put_ptr() decreases the ref-counter of the inner map +directly through bpf_map_put(), if the ref-counter is the last one +(which is true for most cases), the inner map will be freed by +ops->map_free() in a kworker. But for now, most .map_free() callbacks +don't use synchronize_rcu() or its variants to wait for the elapse of a +RCU grace period, so after the invocation of ops->map_free completes, +the bpf program which is accessing the inner map may incur +use-after-free problem. + +Fix the free of inner map by invoking bpf_map_free_deferred() after both +one RCU grace period and one tasks trace RCU grace period if the inner +map has been removed from the outer map before. The deferment is +accomplished by using call_rcu() or call_rcu_tasks_trace() when +releasing the last ref-counter of bpf map. The newly-added rcu_head +field in bpf_map shares the same storage space with work field to +reduce the size of bpf_map. + +Fixes: bba1dc0b55ac ("bpf: Remove redundant synchronize_rcu.") +Fixes: 638e4b825d52 ("bpf: Allows per-cpu maps and map-in-map in sleepable programs") +Signed-off-by: Hou Tao +Link: https://lore.kernel.org/r/20231204140425.1480317-5-houtao@huaweicloud.com +Signed-off-by: Alexei Starovoitov +Signed-off-by: Sasha Levin +--- + include/linux/bpf.h | 7 ++++++- + kernel/bpf/map_in_map.c | 11 ++++++++--- + kernel/bpf/syscall.c | 32 +++++++++++++++++++++++++++----- + 3 files changed, 41 insertions(+), 9 deletions(-) + +diff --git a/include/linux/bpf.h b/include/linux/bpf.h +index 47420a973e58..c04a61ffac8a 100644 +--- a/include/linux/bpf.h ++++ b/include/linux/bpf.h +@@ -237,7 +237,11 @@ struct bpf_map { + */ + atomic64_t refcnt ____cacheline_aligned; + atomic64_t usercnt; +- struct work_struct work; ++ /* rcu is used before freeing and work is only used during freeing */ ++ union { ++ struct work_struct work; ++ struct rcu_head rcu; ++ }; + struct mutex freeze_mutex; + atomic64_t writecnt; + /* 'Ownership' of program-containing map is claimed by the first program +@@ -253,6 +257,7 @@ struct bpf_map { + } owner; + bool bypass_spec_v1; + bool frozen; /* write-once; write-protected by freeze_mutex */ ++ bool free_after_mult_rcu_gp; + s64 __percpu *elem_count; + }; + +diff --git a/kernel/bpf/map_in_map.c b/kernel/bpf/map_in_map.c +index 47ecc4818c93..141f3332038c 100644 +--- a/kernel/bpf/map_in_map.c ++++ b/kernel/bpf/map_in_map.c +@@ -117,10 +117,15 @@ void *bpf_map_fd_get_ptr(struct bpf_map *map, + + void bpf_map_fd_put_ptr(struct bpf_map *map, void *ptr, bool need_defer) + { +- /* ptr->ops->map_free() has to go through one +- * rcu grace period by itself. ++ struct bpf_map *inner_map = ptr; ++ ++ /* The inner map may still be used by both non-sleepable and sleepable ++ * bpf program, so free it after one RCU grace period and one tasks ++ * trace RCU grace period. + */ +- bpf_map_put(ptr); ++ if (need_defer) ++ WRITE_ONCE(inner_map->free_after_mult_rcu_gp, true); ++ bpf_map_put(inner_map); + } + + u32 bpf_map_fd_sys_lookup_elem(void *ptr) +diff --git a/kernel/bpf/syscall.c b/kernel/bpf/syscall.c +index 0c8b7733573e..f019c0821c70 100644 +--- a/kernel/bpf/syscall.c ++++ b/kernel/bpf/syscall.c +@@ -628,6 +628,28 @@ static void bpf_map_put_uref(struct bpf_map *map) + } + } + ++static void bpf_map_free_in_work(struct bpf_map *map) ++{ ++ INIT_WORK(&map->work, bpf_map_free_deferred); ++ /* Avoid spawning kworkers, since they all might contend ++ * for the same mutex like slab_mutex. ++ */ ++ queue_work(system_unbound_wq, &map->work); ++} ++ ++static void bpf_map_free_rcu_gp(struct rcu_head *rcu) ++{ ++ bpf_map_free_in_work(container_of(rcu, struct bpf_map, rcu)); ++} ++ ++static void bpf_map_free_mult_rcu_gp(struct rcu_head *rcu) ++{ ++ if (rcu_trace_implies_rcu_gp()) ++ bpf_map_free_rcu_gp(rcu); ++ else ++ call_rcu(rcu, bpf_map_free_rcu_gp); ++} ++ + /* decrement map refcnt and schedule it for freeing via workqueue + * (unrelying map implementation ops->map_free() might sleep) + */ +@@ -637,11 +659,11 @@ static void __bpf_map_put(struct bpf_map *map, bool do_idr_lock) + /* bpf_map_free_id() must be called first */ + bpf_map_free_id(map, do_idr_lock); + btf_put(map->btf); +- INIT_WORK(&map->work, bpf_map_free_deferred); +- /* Avoid spawning kworkers, since they all might contend +- * for the same mutex like slab_mutex. +- */ +- queue_work(system_unbound_wq, &map->work); ++ ++ if (READ_ONCE(map->free_after_mult_rcu_gp)) ++ call_rcu_tasks_trace(&map->rcu, bpf_map_free_mult_rcu_gp); ++ else ++ bpf_map_free_in_work(map); + } + } + +-- +2.43.0 + diff --git a/queue-6.1/bpf-enforce-precision-of-r0-on-callback-return.patch b/queue-6.1/bpf-enforce-precision-of-r0-on-callback-return.patch new file mode 100644 index 00000000000..031bba9c7f5 --- /dev/null +++ b/queue-6.1/bpf-enforce-precision-of-r0-on-callback-return.patch @@ -0,0 +1,46 @@ +From c38c4f1daffbeda1d194c3fa36fb17ca168930d0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 2 Dec 2023 09:56:57 -0800 +Subject: bpf: enforce precision of R0 on callback return + +From: Andrii Nakryiko + +[ Upstream commit 0acd03a5bd188b0c501d285d938439618bd855c4 ] + +Given verifier checks actual value, r0 has to be precise, so we need to +propagate precision properly. r0 also has to be marked as read, +otherwise subsequent state comparisons will ignore such register as +unimportant and precision won't really help here. + +Fixes: 69c087ba6225 ("bpf: Add bpf_for_each_map_elem() helper") +Acked-by: Eduard Zingerman +Acked-by: Shung-Hsi Yu +Signed-off-by: Andrii Nakryiko +Link: https://lore.kernel.org/r/20231202175705.885270-4-andrii@kernel.org +Signed-off-by: Alexei Starovoitov +Signed-off-by: Sasha Levin +--- + kernel/bpf/verifier.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c +index 142e10d49fd8..024a2393613f 100644 +--- a/kernel/bpf/verifier.c ++++ b/kernel/bpf/verifier.c +@@ -7284,6 +7284,13 @@ static int prepare_func_exit(struct bpf_verifier_env *env, int *insn_idx) + verbose(env, "R0 not a scalar value\n"); + return -EACCES; + } ++ ++ /* we are going to rely on register's precise value */ ++ err = mark_reg_read(env, r0, r0->parent, REG_LIVE_READ64); ++ err = err ?: mark_chain_precision(env, BPF_REG_0); ++ if (err) ++ return err; ++ + if (!tnum_in(range, r0->var_off)) { + verbose_invalid_scalar(env, r0, &range, "callback return", "R0"); + return -EINVAL; +-- +2.43.0 + diff --git a/queue-6.1/bpf-fix-check-for-attempt-to-corrupt-spilled-pointer.patch b/queue-6.1/bpf-fix-check-for-attempt-to-corrupt-spilled-pointer.patch new file mode 100644 index 00000000000..e3e1988cfae --- /dev/null +++ b/queue-6.1/bpf-fix-check-for-attempt-to-corrupt-spilled-pointer.patch @@ -0,0 +1,42 @@ +From a81b375ac84d04ebbad9f495443df3953a8131c7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 5 Dec 2023 10:42:41 -0800 +Subject: bpf: fix check for attempt to corrupt spilled pointer + +From: Andrii Nakryiko + +[ Upstream commit ab125ed3ec1c10ccc36bc98c7a4256ad114a3dae ] + +When register is spilled onto a stack as a 1/2/4-byte register, we set +slot_type[BPF_REG_SIZE - 1] (plus potentially few more below it, +depending on actual spill size). So to check if some stack slot has +spilled register we need to consult slot_type[7], not slot_type[0]. + +To avoid the need to remember and double-check this in the future, just +use is_spilled_reg() helper. + +Fixes: 27113c59b6d0 ("bpf: Check the other end of slot_type for STACK_SPILL") +Signed-off-by: Andrii Nakryiko +Link: https://lore.kernel.org/r/20231205184248.1502704-4-andrii@kernel.org +Signed-off-by: Alexei Starovoitov +Signed-off-by: Sasha Levin +--- + kernel/bpf/verifier.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c +index 024a2393613f..adadf8546270 100644 +--- a/kernel/bpf/verifier.c ++++ b/kernel/bpf/verifier.c +@@ -3284,7 +3284,7 @@ static int check_stack_write_fixed_off(struct bpf_verifier_env *env, + * so it's aligned access and [off, off + size) are within stack limits + */ + if (!env->allow_ptr_leaks && +- state->stack[spi].slot_type[0] == STACK_SPILL && ++ is_spilled_reg(&state->stack[spi]) && + size != BPF_REG_SIZE) { + verbose(env, "attempt to corrupt spilled pointer on stack\n"); + return -EACCES; +-- +2.43.0 + diff --git a/queue-6.1/bpf-fix-verification-of-indirect-var-off-stack-acces.patch b/queue-6.1/bpf-fix-verification-of-indirect-var-off-stack-acces.patch new file mode 100644 index 00000000000..ed7fa767a3e --- /dev/null +++ b/queue-6.1/bpf-fix-verification-of-indirect-var-off-stack-acces.patch @@ -0,0 +1,83 @@ +From 7b4ec453d802ce53d96da6be739a2a011d72b3c3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 6 Dec 2023 23:11:48 -0500 +Subject: bpf: Fix verification of indirect var-off stack access + +From: Andrei Matei + +[ Upstream commit a833a17aeac73b33f79433d7cee68d5cafd71e4f ] + +This patch fixes a bug around the verification of possibly-zero-sized +stack accesses. When the access was done through a var-offset stack +pointer, check_stack_access_within_bounds was incorrectly computing the +maximum-offset of a zero-sized read to be the same as the register's min +offset. Instead, we have to take in account the register's maximum +possible value. The patch also simplifies how the max offset is checked; +the check is now simpler than for min offset. + +The bug was allowing accesses to erroneously pass the +check_stack_access_within_bounds() checks, only to later crash in +check_stack_range_initialized() when all the possibly-affected stack +slots are iterated (this time with a correct max offset). +check_stack_range_initialized() is relying on +check_stack_access_within_bounds() for its accesses to the +stack-tracking vector to be within bounds; in the case of zero-sized +accesses, we were essentially only verifying that the lowest possible +slot was within bounds. We would crash when the max-offset of the stack +pointer was >= 0 (which shouldn't pass verification, and hopefully is +not something anyone's code attempts to do in practice). + +Thanks Hao for reporting! + +Fixes: 01f810ace9ed3 ("bpf: Allow variable-offset stack access") +Reported-by: Hao Sun +Signed-off-by: Andrei Matei +Signed-off-by: Andrii Nakryiko +Acked-by: Eduard Zingerman +Acked-by: Andrii Nakryiko +Link: https://lore.kernel.org/bpf/20231207041150.229139-2-andreimatei1@gmail.com + +Closes: https://lore.kernel.org/bpf/CACkBjsZGEUaRCHsmaX=h-efVogsRfK1FPxmkgb0Os_frnHiNdw@mail.gmail.com/ +Signed-off-by: Sasha Levin +--- + kernel/bpf/verifier.c | 14 ++++---------- + 1 file changed, 4 insertions(+), 10 deletions(-) + +diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c +index adadf8546270..95e7b638418e 100644 +--- a/kernel/bpf/verifier.c ++++ b/kernel/bpf/verifier.c +@@ -4950,10 +4950,7 @@ static int check_stack_access_within_bounds( + + if (tnum_is_const(reg->var_off)) { + min_off = reg->var_off.value + off; +- if (access_size > 0) +- max_off = min_off + access_size - 1; +- else +- max_off = min_off; ++ max_off = min_off + access_size; + } else { + if (reg->smax_value >= BPF_MAX_VAR_OFF || + reg->smin_value <= -BPF_MAX_VAR_OFF) { +@@ -4962,15 +4959,12 @@ static int check_stack_access_within_bounds( + return -EACCES; + } + min_off = reg->smin_value + off; +- if (access_size > 0) +- max_off = reg->smax_value + off + access_size - 1; +- else +- max_off = min_off; ++ max_off = reg->smax_value + off + access_size; + } + + err = check_stack_slot_within_bounds(min_off, state, type); +- if (!err) +- err = check_stack_slot_within_bounds(max_off, state, type); ++ if (!err && max_off > 0) ++ err = -EINVAL; /* out of stack access into non-negative offsets */ + + if (err) { + if (tnum_is_const(reg->var_off)) { +-- +2.43.0 + diff --git a/queue-6.1/bpf-lpm-fix-check-prefixlen-before-walking-trie.patch b/queue-6.1/bpf-lpm-fix-check-prefixlen-before-walking-trie.patch new file mode 100644 index 00000000000..953482b6d04 --- /dev/null +++ b/queue-6.1/bpf-lpm-fix-check-prefixlen-before-walking-trie.patch @@ -0,0 +1,43 @@ +From 4eba773c556f57057e53b743e95447422ac36902 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 5 Nov 2023 09:58:01 +0100 +Subject: bpf, lpm: Fix check prefixlen before walking trie + +From: Florian Lehner + +[ Upstream commit 9b75dbeb36fcd9fc7ed51d370310d0518a387769 ] + +When looking up an element in LPM trie, the condition 'matchlen == +trie->max_prefixlen' will never return true, if key->prefixlen is larger +than trie->max_prefixlen. Consequently all elements in the LPM trie will +be visited and no element is returned in the end. + +To resolve this, check key->prefixlen first before walking the LPM trie. + +Fixes: b95a5c4db09b ("bpf: add a longest prefix match trie map implementation") +Signed-off-by: Florian Lehner +Signed-off-by: Andrii Nakryiko +Link: https://lore.kernel.org/bpf/20231105085801.3742-1-dev@der-flo.net +Signed-off-by: Alexei Starovoitov +Signed-off-by: Sasha Levin +--- + kernel/bpf/lpm_trie.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/kernel/bpf/lpm_trie.c b/kernel/bpf/lpm_trie.c +index d833496e9e42..ce3a091d52e8 100644 +--- a/kernel/bpf/lpm_trie.c ++++ b/kernel/bpf/lpm_trie.c +@@ -231,6 +231,9 @@ static void *trie_lookup_elem(struct bpf_map *map, void *_key) + struct lpm_trie_node *node, *found = NULL; + struct bpf_lpm_trie_key *key = _key; + ++ if (key->prefixlen > trie->max_prefixlen) ++ return NULL; ++ + /* Start walking the trie from the root node ... */ + + for (node = rcu_dereference_check(trie->root, rcu_read_lock_bh_held()); +-- +2.43.0 + diff --git a/queue-6.1/bpf-sockmap-fix-proto-update-hook-to-avoid-dup-calls.patch b/queue-6.1/bpf-sockmap-fix-proto-update-hook-to-avoid-dup-calls.patch new file mode 100644 index 00000000000..f8488b8a178 --- /dev/null +++ b/queue-6.1/bpf-sockmap-fix-proto-update-hook-to-avoid-dup-calls.patch @@ -0,0 +1,81 @@ +From d423d282ffc09799285ec83a7e5534851f16ea99 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 21 Dec 2023 15:23:23 -0800 +Subject: bpf: sockmap, fix proto update hook to avoid dup calls + +From: John Fastabend + +[ Upstream commit 16b2f264983dc264c1560cc0170e760dec1bf54f ] + +When sockets are added to a sockmap or sockhash we allocate and init a +psock. Then update the proto ops with sock_map_init_proto the flow is + + sock_hash_update_common + sock_map_link + psock = sock_map_psock_get_checked() <-returns existing psock + sock_map_init_proto(sk, psock) <- updates sk_proto + +If the socket is already in a map this results in the sock_map_init_proto +being called multiple times on the same socket. We do this because when +a socket is added to multiple maps this might result in a new set of BPF +programs being attached to the socket requiring an updated ops struct. + +This creates a rule where it must be safe to call psock_update_sk_prot +multiple times. When we added a fix for UAF through unix sockets in patch +4dd9a38a753fc we broke this rule by adding a sock_hold in that path +to ensure the sock is not released. The result is if a af_unix stream sock +is placed in multiple maps it results in a memory leak because we call +sock_hold multiple times with only a single sock_put on it. + +Fixes: 8866730aed51 ("bpf, sockmap: af_unix stream sockets need to hold ref for pair sock") +Reported-by: Xingwei Lee +Signed-off-by: John Fastabend +Signed-off-by: Martin KaFai Lau +Reviewed-by: Jakub Sitnicki +Link: https://lore.kernel.org/r/20231221232327.43678-2-john.fastabend@gmail.com +Signed-off-by: Sasha Levin +--- + net/unix/unix_bpf.c | 21 ++++++++++++++++++--- + 1 file changed, 18 insertions(+), 3 deletions(-) + +diff --git a/net/unix/unix_bpf.c b/net/unix/unix_bpf.c +index 7ea7c3a0d0d0..bd84785bf8d6 100644 +--- a/net/unix/unix_bpf.c ++++ b/net/unix/unix_bpf.c +@@ -161,15 +161,30 @@ int unix_stream_bpf_update_proto(struct sock *sk, struct sk_psock *psock, bool r + { + struct sock *sk_pair; + ++ /* Restore does not decrement the sk_pair reference yet because we must ++ * keep the a reference to the socket until after an RCU grace period ++ * and any pending sends have completed. ++ */ + if (restore) { + sk->sk_write_space = psock->saved_write_space; + sock_replace_proto(sk, psock->sk_proto); + return 0; + } + +- sk_pair = unix_peer(sk); +- sock_hold(sk_pair); +- psock->sk_pair = sk_pair; ++ /* psock_update_sk_prot can be called multiple times if psock is ++ * added to multiple maps and/or slots in the same map. There is ++ * also an edge case where replacing a psock with itself can trigger ++ * an extra psock_update_sk_prot during the insert process. So it ++ * must be safe to do multiple calls. Here we need to ensure we don't ++ * increment the refcnt through sock_hold many times. There will only ++ * be a single matching destroy operation. ++ */ ++ if (!psock->sk_pair) { ++ sk_pair = unix_peer(sk); ++ sock_hold(sk_pair); ++ psock->sk_pair = sk_pair; ++ } ++ + unix_stream_bpf_check_needs_rebuild(psock->sk_proto); + sock_replace_proto(sk, &unix_stream_bpf_prot); + return 0; +-- +2.43.0 + diff --git a/queue-6.1/calipso-fix-memory-leak-in-netlbl_calipso_add_pass.patch b/queue-6.1/calipso-fix-memory-leak-in-netlbl_calipso_add_pass.patch new file mode 100644 index 00000000000..54ee8a50858 --- /dev/null +++ b/queue-6.1/calipso-fix-memory-leak-in-netlbl_calipso_add_pass.patch @@ -0,0 +1,138 @@ +From c87cc1c3bbe522c9a873857c7366c6dc0c66267f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 23 Nov 2023 09:25:54 +0000 +Subject: calipso: fix memory leak in netlbl_calipso_add_pass() + +From: Gavrilov Ilia + +[ Upstream commit ec4e9d630a64df500641892f4e259e8149594a99 ] + +If IPv6 support is disabled at boot (ipv6.disable=1), +the calipso_init() -> netlbl_calipso_ops_register() function isn't called, +and the netlbl_calipso_ops_get() function always returns NULL. +In this case, the netlbl_calipso_add_pass() function allocates memory +for the doi_def variable but doesn't free it with the calipso_doi_free(). + +BUG: memory leak +unreferenced object 0xffff888011d68180 (size 64): + comm "syz-executor.1", pid 10746, jiffies 4295410986 (age 17.928s) + hex dump (first 32 bytes): + 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 ................ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ + backtrace: + [<...>] kmalloc include/linux/slab.h:552 [inline] + [<...>] netlbl_calipso_add_pass net/netlabel/netlabel_calipso.c:76 [inline] + [<...>] netlbl_calipso_add+0x22e/0x4f0 net/netlabel/netlabel_calipso.c:111 + [<...>] genl_family_rcv_msg_doit+0x22f/0x330 net/netlink/genetlink.c:739 + [<...>] genl_family_rcv_msg net/netlink/genetlink.c:783 [inline] + [<...>] genl_rcv_msg+0x341/0x5a0 net/netlink/genetlink.c:800 + [<...>] netlink_rcv_skb+0x14d/0x440 net/netlink/af_netlink.c:2515 + [<...>] genl_rcv+0x29/0x40 net/netlink/genetlink.c:811 + [<...>] netlink_unicast_kernel net/netlink/af_netlink.c:1313 [inline] + [<...>] netlink_unicast+0x54b/0x800 net/netlink/af_netlink.c:1339 + [<...>] netlink_sendmsg+0x90a/0xdf0 net/netlink/af_netlink.c:1934 + [<...>] sock_sendmsg_nosec net/socket.c:651 [inline] + [<...>] sock_sendmsg+0x157/0x190 net/socket.c:671 + [<...>] ____sys_sendmsg+0x712/0x870 net/socket.c:2342 + [<...>] ___sys_sendmsg+0xf8/0x170 net/socket.c:2396 + [<...>] __sys_sendmsg+0xea/0x1b0 net/socket.c:2429 + [<...>] do_syscall_64+0x30/0x40 arch/x86/entry/common.c:46 + [<...>] entry_SYSCALL_64_after_hwframe+0x61/0xc6 + +Found by InfoTeCS on behalf of Linux Verification Center +(linuxtesting.org) with Syzkaller + +Fixes: cb72d38211ea ("netlabel: Initial support for the CALIPSO netlink protocol.") +Signed-off-by: Gavrilov Ilia +[PM: merged via the LSM tree at Jakub Kicinski request] +Signed-off-by: Paul Moore +Signed-off-by: Sasha Levin +--- + net/netlabel/netlabel_calipso.c | 49 +++++++++++++++++---------------- + 1 file changed, 26 insertions(+), 23 deletions(-) + +diff --git a/net/netlabel/netlabel_calipso.c b/net/netlabel/netlabel_calipso.c +index f1d5b8465217..a07c2216d28b 100644 +--- a/net/netlabel/netlabel_calipso.c ++++ b/net/netlabel/netlabel_calipso.c +@@ -54,6 +54,28 @@ static const struct nla_policy calipso_genl_policy[NLBL_CALIPSO_A_MAX + 1] = { + [NLBL_CALIPSO_A_MTYPE] = { .type = NLA_U32 }, + }; + ++static const struct netlbl_calipso_ops *calipso_ops; ++ ++/** ++ * netlbl_calipso_ops_register - Register the CALIPSO operations ++ * @ops: ops to register ++ * ++ * Description: ++ * Register the CALIPSO packet engine operations. ++ * ++ */ ++const struct netlbl_calipso_ops * ++netlbl_calipso_ops_register(const struct netlbl_calipso_ops *ops) ++{ ++ return xchg(&calipso_ops, ops); ++} ++EXPORT_SYMBOL(netlbl_calipso_ops_register); ++ ++static const struct netlbl_calipso_ops *netlbl_calipso_ops_get(void) ++{ ++ return READ_ONCE(calipso_ops); ++} ++ + /* NetLabel Command Handlers + */ + /** +@@ -96,15 +118,18 @@ static int netlbl_calipso_add_pass(struct genl_info *info, + * + */ + static int netlbl_calipso_add(struct sk_buff *skb, struct genl_info *info) +- + { + int ret_val = -EINVAL; + struct netlbl_audit audit_info; ++ const struct netlbl_calipso_ops *ops = netlbl_calipso_ops_get(); + + if (!info->attrs[NLBL_CALIPSO_A_DOI] || + !info->attrs[NLBL_CALIPSO_A_MTYPE]) + return -EINVAL; + ++ if (!ops) ++ return -EOPNOTSUPP; ++ + netlbl_netlink_auditinfo(&audit_info); + switch (nla_get_u32(info->attrs[NLBL_CALIPSO_A_MTYPE])) { + case CALIPSO_MAP_PASS: +@@ -363,28 +388,6 @@ int __init netlbl_calipso_genl_init(void) + return genl_register_family(&netlbl_calipso_gnl_family); + } + +-static const struct netlbl_calipso_ops *calipso_ops; +- +-/** +- * netlbl_calipso_ops_register - Register the CALIPSO operations +- * @ops: ops to register +- * +- * Description: +- * Register the CALIPSO packet engine operations. +- * +- */ +-const struct netlbl_calipso_ops * +-netlbl_calipso_ops_register(const struct netlbl_calipso_ops *ops) +-{ +- return xchg(&calipso_ops, ops); +-} +-EXPORT_SYMBOL(netlbl_calipso_ops_register); +- +-static const struct netlbl_calipso_ops *netlbl_calipso_ops_get(void) +-{ +- return READ_ONCE(calipso_ops); +-} +- + /** + * calipso_doi_add - Add a new DOI to the CALIPSO protocol engine + * @doi_def: the DOI structure +-- +2.43.0 + diff --git a/queue-6.1/clk-fixed-rate-fix-clk_hw_register_fixed_rate_with_a.patch b/queue-6.1/clk-fixed-rate-fix-clk_hw_register_fixed_rate_with_a.patch new file mode 100644 index 00000000000..4464164770f --- /dev/null +++ b/queue-6.1/clk-fixed-rate-fix-clk_hw_register_fixed_rate_with_a.patch @@ -0,0 +1,43 @@ +From d14f813cf6afa89c86991e33238ee23d64a4b348 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 18 Dec 2023 18:14:16 +0100 +Subject: clk: fixed-rate: fix + clk_hw_register_fixed_rate_with_accuracy_parent_hw +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Théo Lebrun + +[ Upstream commit ee0cf5e07f44a10fce8f1bfa9db226c0b5ecf880 ] + +Add missing comma and remove extraneous NULL argument. The macro is +currently used by no one which explains why the typo slipped by. + +Fixes: 2d34f09e79c9 ("clk: fixed-rate: Add support for specifying parents via DT/pointers") +Signed-off-by: Théo Lebrun +Link: https://lore.kernel.org/r/20231218-mbly-clk-v1-1-44ce54108f06@bootlin.com +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + include/linux/clk-provider.h | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h +index 15e336281d1f..94fcfefb52f3 100644 +--- a/include/linux/clk-provider.h ++++ b/include/linux/clk-provider.h +@@ -446,8 +446,8 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name, + */ + #define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \ + parent_hw, flags, fixed_rate, fixed_accuracy) \ +- __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw) \ +- NULL, NULL, (flags), (fixed_rate), \ ++ __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \ ++ NULL, (flags), (fixed_rate), \ + (fixed_accuracy), 0, false) + /** + * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate +-- +2.43.0 + diff --git a/queue-6.1/clk-qcom-gpucc-sm8150-update-the-gpu_cc_pll1-config.patch b/queue-6.1/clk-qcom-gpucc-sm8150-update-the-gpu_cc_pll1-config.patch new file mode 100644 index 00000000000..ad63930d5cc --- /dev/null +++ b/queue-6.1/clk-qcom-gpucc-sm8150-update-the-gpu_cc_pll1-config.patch @@ -0,0 +1,40 @@ +From da963c21e23e542dcf82b0b35731b336e8e68d8c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 22 Nov 2023 09:58:14 +0530 +Subject: clk: qcom: gpucc-sm8150: Update the gpu_cc_pll1 config + +From: Satya Priya Kakitapalli + +[ Upstream commit 6ebd9a4f8b8d2b35cf965a04849c4ba763722f13 ] + +Update the test_ctl_hi_val and test_ctl_hi1_val of gpu_cc_pll1 +as per latest HW recommendation. + +Fixes: 0cef71f2ccc8 ("clk: qcom: Add graphics clock controller driver for SM8150") +Signed-off-by: Satya Priya Kakitapalli +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231122042814.4158076-1-quic_skakitap@quicinc.com +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/gpucc-sm8150.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/clk/qcom/gpucc-sm8150.c b/drivers/clk/qcom/gpucc-sm8150.c +index 8422fd047493..c89a5b59ddb7 100644 +--- a/drivers/clk/qcom/gpucc-sm8150.c ++++ b/drivers/clk/qcom/gpucc-sm8150.c +@@ -37,8 +37,8 @@ static struct alpha_pll_config gpu_cc_pll1_config = { + .config_ctl_hi_val = 0x00002267, + .config_ctl_hi1_val = 0x00000024, + .test_ctl_val = 0x00000000, +- .test_ctl_hi_val = 0x00000002, +- .test_ctl_hi1_val = 0x00000000, ++ .test_ctl_hi_val = 0x00000000, ++ .test_ctl_hi1_val = 0x00000020, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x000000d0, +-- +2.43.0 + diff --git a/queue-6.1/clk-qcom-videocc-sm8150-add-missing-pll-config-prope.patch b/queue-6.1/clk-qcom-videocc-sm8150-add-missing-pll-config-prope.patch new file mode 100644 index 00000000000..d208522142a --- /dev/null +++ b/queue-6.1/clk-qcom-videocc-sm8150-add-missing-pll-config-prope.patch @@ -0,0 +1,37 @@ +From f29aa2ed3e7b6ab49e643cf59fdc1c65e5712ea7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 1 Dec 2023 15:20:26 +0530 +Subject: clk: qcom: videocc-sm8150: Add missing PLL config property + +From: Satya Priya Kakitapalli + +[ Upstream commit 71f130c9193f613d497f7245365ed05ffdb0a401 ] + +When the driver was ported upstream, PLL test_ctl_hi1 register value +was omitted. Add it to ensure the PLLs are fully configured. + +Fixes: 5658e8cf1a8a ("clk: qcom: add video clock controller driver for SM8150") +Signed-off-by: Satya Priya Kakitapalli +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231201-videocc-8150-v3-3-56bec3a5e443@quicinc.com +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/videocc-sm8150.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/clk/qcom/videocc-sm8150.c b/drivers/clk/qcom/videocc-sm8150.c +index 6a5f89f53da8..52a9a453a143 100644 +--- a/drivers/clk/qcom/videocc-sm8150.c ++++ b/drivers/clk/qcom/videocc-sm8150.c +@@ -33,6 +33,7 @@ static struct alpha_pll_config video_pll0_config = { + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002267, + .config_ctl_hi1_val = 0x00000024, ++ .test_ctl_hi1_val = 0x00000020, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x000000D0, +-- +2.43.0 + diff --git a/queue-6.1/clk-qcom-videocc-sm8150-update-the-videocc-resets.patch b/queue-6.1/clk-qcom-videocc-sm8150-update-the-videocc-resets.patch new file mode 100644 index 00000000000..4b56c318889 --- /dev/null +++ b/queue-6.1/clk-qcom-videocc-sm8150-update-the-videocc-resets.patch @@ -0,0 +1,41 @@ +From 9d488117b4b71ca5f4921d03c45ff7884cfbacfb Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 1 Dec 2023 15:20:25 +0530 +Subject: clk: qcom: videocc-sm8150: Update the videocc resets + +From: Satya Priya Kakitapalli + +[ Upstream commit 1fd9a939db24d2f66e48f8bca3e3654add3fa205 ] + +Add all the available resets for the video clock controller +on sm8150. + +Fixes: 5658e8cf1a8a ("clk: qcom: add video clock controller driver for SM8150") +Signed-off-by: Satya Priya Kakitapalli +Reviewed-by: Bryan O'Donoghue +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231201-videocc-8150-v3-2-56bec3a5e443@quicinc.com +Signed-off-by: Bjorn Andersson +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/videocc-sm8150.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/clk/qcom/videocc-sm8150.c b/drivers/clk/qcom/videocc-sm8150.c +index 1afdbe4a249d..6a5f89f53da8 100644 +--- a/drivers/clk/qcom/videocc-sm8150.c ++++ b/drivers/clk/qcom/videocc-sm8150.c +@@ -214,6 +214,10 @@ static const struct regmap_config video_cc_sm8150_regmap_config = { + + static const struct qcom_reset_map video_cc_sm8150_resets[] = { + [VIDEO_CC_MVSC_CORE_CLK_BCR] = { 0x850, 2 }, ++ [VIDEO_CC_INTERFACE_BCR] = { 0x8f0 }, ++ [VIDEO_CC_MVS0_BCR] = { 0x870 }, ++ [VIDEO_CC_MVS1_BCR] = { 0x8b0 }, ++ [VIDEO_CC_MVSC_BCR] = { 0x810 }, + }; + + static const struct qcom_cc_desc video_cc_sm8150_desc = { +-- +2.43.0 + diff --git a/queue-6.1/clk-renesas-rzg2l-check-reset-monitor-registers.patch b/queue-6.1/clk-renesas-rzg2l-check-reset-monitor-registers.patch new file mode 100644 index 00000000000..902fbf8d81b --- /dev/null +++ b/queue-6.1/clk-renesas-rzg2l-check-reset-monitor-registers.patch @@ -0,0 +1,138 @@ +From 53c139cf001b44013dfd4c6fa66a5bb062417600 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 7 Dec 2023 09:06:50 +0200 +Subject: clk: renesas: rzg2l: Check reset monitor registers + +From: Claudiu Beznea + +[ Upstream commit da235d2fac212d0add570e755feb1167a830bc99 ] + +The hardware manual of both RZ/G2L and RZ/G3S specifies that the reset +monitor registers need to be interrogated when the reset signals are +toggled (chapters "Procedures for Supplying and Stopping Reset Signals" +and "Procedure for Activating Modules"). Without this, there is a +chance that different modules (e.g. Ethernet) are not ready after their +reset signal is toggled, leading to failures (on probe or resume from +deep sleep states). + +The same indications are available for RZ/V2M for TYPE-B reset controls. + +Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") +Fixes: 8090bea32484 ("clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg") +Signed-off-by: Claudiu Beznea +Reviewed-by: Geert Uytterhoeven +Link: https://lore.kernel.org/r/20231207070700.4156557-2-claudiu.beznea.uj@bp.renesas.com +Signed-off-by: Geert Uytterhoeven +Signed-off-by: Sasha Levin +--- + drivers/clk/renesas/rzg2l-cpg.c | 59 ++++++++++++++++++++++++--------- + 1 file changed, 44 insertions(+), 15 deletions(-) + +diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c +index 93720f319409..473feb36a38f 100644 +--- a/drivers/clk/renesas/rzg2l-cpg.c ++++ b/drivers/clk/renesas/rzg2l-cpg.c +@@ -1121,12 +1121,27 @@ static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev, + struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev); + const struct rzg2l_cpg_info *info = priv->info; + unsigned int reg = info->resets[id].off; +- u32 value = BIT(info->resets[id].bit) << 16; ++ u32 mask = BIT(info->resets[id].bit); ++ s8 monbit = info->resets[id].monbit; ++ u32 value = mask << 16; + + dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, CLK_RST_R(reg)); + + writel(value, priv->base + CLK_RST_R(reg)); +- return 0; ++ ++ if (info->has_clk_mon_regs) { ++ reg = CLK_MRST_R(reg); ++ } else if (monbit >= 0) { ++ reg = CPG_RST_MON; ++ mask = BIT(monbit); ++ } else { ++ /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ ++ udelay(35); ++ return 0; ++ } ++ ++ return readl_poll_timeout_atomic(priv->base + reg, value, ++ value & mask, 10, 200); + } + + static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev, +@@ -1135,14 +1150,28 @@ static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev, + struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev); + const struct rzg2l_cpg_info *info = priv->info; + unsigned int reg = info->resets[id].off; +- u32 dis = BIT(info->resets[id].bit); +- u32 value = (dis << 16) | dis; ++ u32 mask = BIT(info->resets[id].bit); ++ s8 monbit = info->resets[id].monbit; ++ u32 value = (mask << 16) | mask; + + dev_dbg(rcdev->dev, "deassert id:%ld offset:0x%x\n", id, + CLK_RST_R(reg)); + + writel(value, priv->base + CLK_RST_R(reg)); +- return 0; ++ ++ if (info->has_clk_mon_regs) { ++ reg = CLK_MRST_R(reg); ++ } else if (monbit >= 0) { ++ reg = CPG_RST_MON; ++ mask = BIT(monbit); ++ } else { ++ /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ ++ udelay(35); ++ return 0; ++ } ++ ++ return readl_poll_timeout_atomic(priv->base + reg, value, ++ !(value & mask), 10, 200); + } + + static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev, +@@ -1154,9 +1183,6 @@ static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev, + if (ret) + return ret; + +- /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ +- udelay(35); +- + return rzg2l_cpg_deassert(rcdev, id); + } + +@@ -1165,18 +1191,21 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev, + { + struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev); + const struct rzg2l_cpg_info *info = priv->info; +- unsigned int reg = info->resets[id].off; +- u32 bitmask = BIT(info->resets[id].bit); + s8 monbit = info->resets[id].monbit; ++ unsigned int reg; ++ u32 bitmask; + + if (info->has_clk_mon_regs) { +- return !!(readl(priv->base + CLK_MRST_R(reg)) & bitmask); ++ reg = CLK_MRST_R(info->resets[id].off); ++ bitmask = BIT(info->resets[id].bit); + } else if (monbit >= 0) { +- u32 monbitmask = BIT(monbit); +- +- return !!(readl(priv->base + CPG_RST_MON) & monbitmask); ++ reg = CPG_RST_MON; ++ bitmask = BIT(monbit); ++ } else { ++ return -ENOTSUPP; + } +- return -ENOTSUPP; ++ ++ return !!(readl(priv->base + reg) & bitmask); + } + + static const struct reset_control_ops rzg2l_cpg_reset_ops = { +-- +2.43.0 + diff --git a/queue-6.1/clk-renesas-rzg2l-cpg-reuse-code-in-rzg2l_cpg_reset.patch b/queue-6.1/clk-renesas-rzg2l-cpg-reuse-code-in-rzg2l_cpg_reset.patch new file mode 100644 index 00000000000..a19a4af6fb6 --- /dev/null +++ b/queue-6.1/clk-renesas-rzg2l-cpg-reuse-code-in-rzg2l_cpg_reset.patch @@ -0,0 +1,82 @@ +From 128806e9c7840373cb3ef94f4910f4c5e44ba855 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 20 Nov 2023 09:00:11 +0200 +Subject: clk: renesas: rzg2l-cpg: Reuse code in rzg2l_cpg_reset() + +From: Claudiu Beznea + +[ Upstream commit 5f9e29b9159a41fcf6733c3b59fa46a90ce3ae20 ] + +Code in rzg2l_cpg_reset() is equivalent with the combined code of +rzg2l_cpg_assert() and rzg2l_cpg_deassert(). There is no need to have +different versions thus re-use rzg2l_cpg_assert() and rzg2l_cpg_deassert(). + +Signed-off-by: Claudiu Beznea +Reviewed-by: Geert Uytterhoeven +Link: https://lore.kernel.org/r/20231120070024.4079344-2-claudiu.beznea.uj@bp.renesas.com +Signed-off-by: Geert Uytterhoeven +Stable-dep-of: da235d2fac21 ("clk: renesas: rzg2l: Check reset monitor registers") +Signed-off-by: Sasha Levin +--- + drivers/clk/renesas/rzg2l-cpg.c | 38 +++++++++++++-------------------- + 1 file changed, 15 insertions(+), 23 deletions(-) + +diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c +index 84767cfc1e73..93720f319409 100644 +--- a/drivers/clk/renesas/rzg2l-cpg.c ++++ b/drivers/clk/renesas/rzg2l-cpg.c +@@ -1115,29 +1115,6 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod, + + #define rcdev_to_priv(x) container_of(x, struct rzg2l_cpg_priv, rcdev) + +-static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev, +- unsigned long id) +-{ +- struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev); +- const struct rzg2l_cpg_info *info = priv->info; +- unsigned int reg = info->resets[id].off; +- u32 dis = BIT(info->resets[id].bit); +- u32 we = dis << 16; +- +- dev_dbg(rcdev->dev, "reset id:%ld offset:0x%x\n", id, CLK_RST_R(reg)); +- +- /* Reset module */ +- writel(we, priv->base + CLK_RST_R(reg)); +- +- /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ +- udelay(35); +- +- /* Release module from reset state */ +- writel(we | dis, priv->base + CLK_RST_R(reg)); +- +- return 0; +-} +- + static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev, + unsigned long id) + { +@@ -1168,6 +1145,21 @@ static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev, + return 0; + } + ++static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev, ++ unsigned long id) ++{ ++ int ret; ++ ++ ret = rzg2l_cpg_assert(rcdev, id); ++ if (ret) ++ return ret; ++ ++ /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ ++ udelay(35); ++ ++ return rzg2l_cpg_deassert(rcdev, id); ++} ++ + static int rzg2l_cpg_status(struct reset_controller_dev *rcdev, + unsigned long id) + { +-- +2.43.0 + diff --git a/queue-6.1/clk-si5341-fix-an-error-code-problem-in-si5341_outpu.patch b/queue-6.1/clk-si5341-fix-an-error-code-problem-in-si5341_outpu.patch new file mode 100644 index 00000000000..9ccf0b4aa11 --- /dev/null +++ b/queue-6.1/clk-si5341-fix-an-error-code-problem-in-si5341_outpu.patch @@ -0,0 +1,41 @@ +From d5ca16eca71c777344d41c31423b98502baaac31 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 1 Nov 2023 11:16:36 +0800 +Subject: clk: si5341: fix an error code problem in si5341_output_clk_set_rate + +From: Su Hui + +[ Upstream commit 5607068ae5ab02c3ac9cabc6859d36e98004c341 ] + +regmap_bulk_write() return zero or negative error code, return the value +of regmap_bulk_write() rather than '0'. + +Fixes: 3044a860fd09 ("clk: Add Si5341/Si5340 driver") +Acked-by: Mike Looijmans +Signed-off-by: Su Hui +Link: https://lore.kernel.org/r/20231101031633.996124-1-suhui@nfschina.com +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/clk-si5341.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +diff --git a/drivers/clk/clk-si5341.c b/drivers/clk/clk-si5341.c +index c7d8cbd22bac..5acb35236c58 100644 +--- a/drivers/clk/clk-si5341.c ++++ b/drivers/clk/clk-si5341.c +@@ -892,10 +892,8 @@ static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate, + r[0] = r_div ? (r_div & 0xff) : 1; + r[1] = (r_div >> 8) & 0xff; + r[2] = (r_div >> 16) & 0xff; +- err = regmap_bulk_write(output->data->regmap, ++ return regmap_bulk_write(output->data->regmap, + SI5341_OUT_R_REG(output), r, 3); +- +- return 0; + } + + static int si5341_output_reparent(struct clk_si5341_output *output, u8 index) +-- +2.43.0 + diff --git a/queue-6.1/cpufreq-scmi-process-the-result-of-devm_of_clk_add_h.patch b/queue-6.1/cpufreq-scmi-process-the-result-of-devm_of_clk_add_h.patch new file mode 100644 index 00000000000..6e1c8d4808c --- /dev/null +++ b/queue-6.1/cpufreq-scmi-process-the-result-of-devm_of_clk_add_h.patch @@ -0,0 +1,43 @@ +From 0a7532f3228846792a6bcc43662b7dda4e255a87 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 5 Dec 2023 18:12:20 +0300 +Subject: cpufreq: scmi: process the result of devm_of_clk_add_hw_provider() + +From: Alexandra Diupina + +[ Upstream commit c4a5118a3ae1eadc687d84eef9431f9e13eb015c ] + +devm_of_clk_add_hw_provider() may return an errno, so +add a return value check + +Found by Linux Verification Center (linuxtesting.org) with SVACE. + +Fixes: 8410e7f3b31e ("cpufreq: scmi: Fix OPP addition failure with a dummy clock provider") +Signed-off-by: Alexandra Diupina +Signed-off-by: Viresh Kumar +Signed-off-by: Sasha Levin +--- + drivers/cpufreq/scmi-cpufreq.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/drivers/cpufreq/scmi-cpufreq.c b/drivers/cpufreq/scmi-cpufreq.c +index f34e6382a4c5..028df8a5f537 100644 +--- a/drivers/cpufreq/scmi-cpufreq.c ++++ b/drivers/cpufreq/scmi-cpufreq.c +@@ -310,8 +310,11 @@ static int scmi_cpufreq_probe(struct scmi_device *sdev) + + #ifdef CONFIG_COMMON_CLK + /* dummy clock provider as needed by OPP if clocks property is used */ +- if (of_property_present(dev->of_node, "#clock-cells")) +- devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, NULL); ++ if (of_property_present(dev->of_node, "#clock-cells")) { ++ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, NULL); ++ if (ret) ++ return dev_err_probe(dev, ret, "%s: registering clock provider failed\n", __func__); ++ } + #endif + + ret = cpufreq_register_driver(&scmi_cpufreq_driver); +-- +2.43.0 + diff --git a/queue-6.1/cpufreq-use-of_property_present-for-testing-dt-prope.patch b/queue-6.1/cpufreq-use-of_property_present-for-testing-dt-prope.patch new file mode 100644 index 00000000000..581e1441c03 --- /dev/null +++ b/queue-6.1/cpufreq-use-of_property_present-for-testing-dt-prope.patch @@ -0,0 +1,105 @@ +From b612fe14f18e4fb961abdb1a86d21faf37733c81 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 10 Mar 2023 08:47:02 -0600 +Subject: cpufreq: Use of_property_present() for testing DT property presence + +From: Rob Herring + +[ Upstream commit b8f3a396a7ee43e6079176cc0fb8de2b95a23681 ] + +It is preferred to use typed property access functions (i.e. +of_property_read_ functions) rather than low-level +of_get_property/of_find_property functions for reading properties. As +part of this, convert of_get_property/of_find_property calls to the +recently added of_property_present() helper when we just want to test +for presence of a property and nothing more. + +Signed-off-by: Rob Herring +Signed-off-by: Viresh Kumar +Stable-dep-of: c4a5118a3ae1 ("cpufreq: scmi: process the result of devm_of_clk_add_hw_provider()") +Signed-off-by: Sasha Levin +--- + drivers/cpufreq/cpufreq-dt-platdev.c | 2 +- + drivers/cpufreq/imx-cpufreq-dt.c | 2 +- + drivers/cpufreq/imx6q-cpufreq.c | 4 ++-- + drivers/cpufreq/scmi-cpufreq.c | 2 +- + drivers/cpufreq/tegra20-cpufreq.c | 2 +- + 5 files changed, 6 insertions(+), 6 deletions(-) + +diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c +index 69a8742c0a7a..8514bb62dd10 100644 +--- a/drivers/cpufreq/cpufreq-dt-platdev.c ++++ b/drivers/cpufreq/cpufreq-dt-platdev.c +@@ -176,7 +176,7 @@ static bool __init cpu0_node_has_opp_v2_prop(void) + struct device_node *np = of_cpu_device_node_get(0); + bool ret = false; + +- if (of_get_property(np, "operating-points-v2", NULL)) ++ if (of_property_present(np, "operating-points-v2")) + ret = true; + + of_node_put(np); +diff --git a/drivers/cpufreq/imx-cpufreq-dt.c b/drivers/cpufreq/imx-cpufreq-dt.c +index 76e553af2071..535867a7dfdd 100644 +--- a/drivers/cpufreq/imx-cpufreq-dt.c ++++ b/drivers/cpufreq/imx-cpufreq-dt.c +@@ -89,7 +89,7 @@ static int imx_cpufreq_dt_probe(struct platform_device *pdev) + + cpu_dev = get_cpu_device(0); + +- if (!of_find_property(cpu_dev->of_node, "cpu-supply", NULL)) ++ if (!of_property_present(cpu_dev->of_node, "cpu-supply")) + return -ENODEV; + + if (of_machine_is_compatible("fsl,imx7ulp")) { +diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c +index 925fc17eaacb..39b0362a3b9a 100644 +--- a/drivers/cpufreq/imx6q-cpufreq.c ++++ b/drivers/cpufreq/imx6q-cpufreq.c +@@ -230,7 +230,7 @@ static int imx6q_opp_check_speed_grading(struct device *dev) + u32 val; + int ret; + +- if (of_find_property(dev->of_node, "nvmem-cells", NULL)) { ++ if (of_property_present(dev->of_node, "nvmem-cells")) { + ret = nvmem_cell_read_u32(dev, "speed_grade", &val); + if (ret) + return ret; +@@ -285,7 +285,7 @@ static int imx6ul_opp_check_speed_grading(struct device *dev) + u32 val; + int ret = 0; + +- if (of_find_property(dev->of_node, "nvmem-cells", NULL)) { ++ if (of_property_present(dev->of_node, "nvmem-cells")) { + ret = nvmem_cell_read_u32(dev, "speed_grade", &val); + if (ret) + return ret; +diff --git a/drivers/cpufreq/scmi-cpufreq.c b/drivers/cpufreq/scmi-cpufreq.c +index 513a071845c2..f34e6382a4c5 100644 +--- a/drivers/cpufreq/scmi-cpufreq.c ++++ b/drivers/cpufreq/scmi-cpufreq.c +@@ -310,7 +310,7 @@ static int scmi_cpufreq_probe(struct scmi_device *sdev) + + #ifdef CONFIG_COMMON_CLK + /* dummy clock provider as needed by OPP if clocks property is used */ +- if (of_find_property(dev->of_node, "#clock-cells", NULL)) ++ if (of_property_present(dev->of_node, "#clock-cells")) + devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, NULL); + #endif + +diff --git a/drivers/cpufreq/tegra20-cpufreq.c b/drivers/cpufreq/tegra20-cpufreq.c +index ab7ac7df9e62..dfd2de4f8e07 100644 +--- a/drivers/cpufreq/tegra20-cpufreq.c ++++ b/drivers/cpufreq/tegra20-cpufreq.c +@@ -25,7 +25,7 @@ static bool cpu0_node_has_opp_v2_prop(void) + struct device_node *np = of_cpu_device_node_get(0); + bool ret = false; + +- if (of_get_property(np, "operating-points-v2", NULL)) ++ if (of_property_present(np, "operating-points-v2")) + ret = true; + + of_node_put(np); +-- +2.43.0 + diff --git a/queue-6.1/crypto-af_alg-disallow-multiple-in-flight-aio-reques.patch b/queue-6.1/crypto-af_alg-disallow-multiple-in-flight-aio-reques.patch new file mode 100644 index 00000000000..89cd845b922 --- /dev/null +++ b/queue-6.1/crypto-af_alg-disallow-multiple-in-flight-aio-reques.patch @@ -0,0 +1,85 @@ +From fe3e76db21257a7490eb1d88a074da61be7c34f0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Nov 2023 16:25:49 +0800 +Subject: crypto: af_alg - Disallow multiple in-flight AIO requests + +From: Herbert Xu + +[ Upstream commit 67b164a871af1d736f131fd6fe78a610909f06f3 ] + +Having multiple in-flight AIO requests results in unpredictable +output because they all share the same IV. Fix this by only allowing +one request at a time. + +Fixes: 83094e5e9e49 ("crypto: af_alg - add async support to algif_aead") +Fixes: a596999b7ddf ("crypto: algif - change algif_skcipher to be asynchronous") +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + crypto/af_alg.c | 14 +++++++++++++- + include/crypto/if_alg.h | 3 +++ + 2 files changed, 16 insertions(+), 1 deletion(-) + +diff --git a/crypto/af_alg.c b/crypto/af_alg.c +index e893c0f6c879..fef69d2a6b18 100644 +--- a/crypto/af_alg.c ++++ b/crypto/af_alg.c +@@ -1045,9 +1045,13 @@ EXPORT_SYMBOL_GPL(af_alg_sendpage); + void af_alg_free_resources(struct af_alg_async_req *areq) + { + struct sock *sk = areq->sk; ++ struct af_alg_ctx *ctx; + + af_alg_free_areq_sgls(areq); + sock_kfree_s(sk, areq, areq->areqlen); ++ ++ ctx = alg_sk(sk)->private; ++ ctx->inflight = false; + } + EXPORT_SYMBOL_GPL(af_alg_free_resources); + +@@ -1117,11 +1121,19 @@ EXPORT_SYMBOL_GPL(af_alg_poll); + struct af_alg_async_req *af_alg_alloc_areq(struct sock *sk, + unsigned int areqlen) + { +- struct af_alg_async_req *areq = sock_kmalloc(sk, areqlen, GFP_KERNEL); ++ struct af_alg_ctx *ctx = alg_sk(sk)->private; ++ struct af_alg_async_req *areq; ++ ++ /* Only one AIO request can be in flight. */ ++ if (ctx->inflight) ++ return ERR_PTR(-EBUSY); + ++ areq = sock_kmalloc(sk, areqlen, GFP_KERNEL); + if (unlikely(!areq)) + return ERR_PTR(-ENOMEM); + ++ ctx->inflight = true; ++ + areq->areqlen = areqlen; + areq->sk = sk; + areq->last_rsgl = NULL; +diff --git a/include/crypto/if_alg.h b/include/crypto/if_alg.h +index a5db86670bdf..a406e281ae57 100644 +--- a/include/crypto/if_alg.h ++++ b/include/crypto/if_alg.h +@@ -138,6 +138,7 @@ struct af_alg_async_req { + * recvmsg is invoked. + * @init: True if metadata has been sent. + * @len: Length of memory allocated for this data structure. ++ * @inflight: Non-zero when AIO requests are in flight. + */ + struct af_alg_ctx { + struct list_head tsgl_list; +@@ -156,6 +157,8 @@ struct af_alg_ctx { + bool init; + + unsigned int len; ++ ++ unsigned int inflight; + }; + + int af_alg_register_type(const struct af_alg_type *type); +-- +2.43.0 + diff --git a/queue-6.1/crypto-ccp-fix-memleak-in-ccp_init_dm_workarea.patch b/queue-6.1/crypto-ccp-fix-memleak-in-ccp_init_dm_workarea.patch new file mode 100644 index 00000000000..d966a4b1323 --- /dev/null +++ b/queue-6.1/crypto-ccp-fix-memleak-in-ccp_init_dm_workarea.patch @@ -0,0 +1,45 @@ +From fcc6519c5411fc494328b2991889605198b7f73d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 27 Nov 2023 11:47:10 +0800 +Subject: crypto: ccp - fix memleak in ccp_init_dm_workarea + +From: Dinghao Liu + +[ Upstream commit a1c95dd5bc1d6a5d7a75a376c2107421b7d6240d ] + +When dma_map_single() fails, wa->address is supposed to be freed +by the callers of ccp_init_dm_workarea() through ccp_dm_free(). +However, many of the call spots don't expect to have to call +ccp_dm_free() on failure of ccp_init_dm_workarea(), which may +lead to a memleak. Let's free wa->address in ccp_init_dm_workarea() +when dma_map_single() fails. + +Fixes: 63b945091a07 ("crypto: ccp - CCP device driver and interface support") +Signed-off-by: Dinghao Liu +Acked-by: Tom Lendacky +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/ccp/ccp-ops.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/drivers/crypto/ccp/ccp-ops.c b/drivers/crypto/ccp/ccp-ops.c +index aa4e1a500691..cb8e99936abb 100644 +--- a/drivers/crypto/ccp/ccp-ops.c ++++ b/drivers/crypto/ccp/ccp-ops.c +@@ -179,8 +179,11 @@ static int ccp_init_dm_workarea(struct ccp_dm_workarea *wa, + + wa->dma.address = dma_map_single(wa->dev, wa->address, len, + dir); +- if (dma_mapping_error(wa->dev, wa->dma.address)) ++ if (dma_mapping_error(wa->dev, wa->dma.address)) { ++ kfree(wa->address); ++ wa->address = NULL; + return -ENOMEM; ++ } + + wa->dma.length = len; + } +-- +2.43.0 + diff --git a/queue-6.1/crypto-hisilicon-hpre-save-capability-registers-in-p.patch b/queue-6.1/crypto-hisilicon-hpre-save-capability-registers-in-p.patch new file mode 100644 index 00000000000..b6cfd055a6d --- /dev/null +++ b/queue-6.1/crypto-hisilicon-hpre-save-capability-registers-in-p.patch @@ -0,0 +1,211 @@ +From ebac5ff448b99a539f1cf96be295c6c9037ed571 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 2 Dec 2023 17:17:20 +0800 +Subject: crypto: hisilicon/hpre - save capability registers in probe process + +From: Zhiqi Song + +[ Upstream commit cf8b5156bbc8c9376f699e8d35e9464b739e33ff ] + +Pre-store the valid value of hpre alg support related capability +register in hpre_qm_init(), which will be called by hpre_probe(). +It can reduce the number of capability register queries and avoid +obtaining incorrect values in abnormal scenarios, such as reset +failed and the memory space disabled. + +Fixes: f214d59a0603 ("crypto: hisilicon/hpre - support hpre capability") +Signed-off-by: Zhiqi Song +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/hisilicon/hpre/hpre_main.c | 82 ++++++++++++++++++----- + 1 file changed, 64 insertions(+), 18 deletions(-) + +diff --git a/drivers/crypto/hisilicon/hpre/hpre_main.c b/drivers/crypto/hisilicon/hpre/hpre_main.c +index cf02c9cde85a..269df4ec148b 100644 +--- a/drivers/crypto/hisilicon/hpre/hpre_main.c ++++ b/drivers/crypto/hisilicon/hpre/hpre_main.c +@@ -226,6 +226,20 @@ static const struct hisi_qm_cap_info hpre_basic_info[] = { + {HPRE_CORE10_ALG_BITMAP_CAP, 0x3170, 0, GENMASK(31, 0), 0x0, 0x10, 0x10} + }; + ++enum hpre_pre_store_cap_idx { ++ HPRE_CLUSTER_NUM_CAP_IDX = 0x0, ++ HPRE_CORE_ENABLE_BITMAP_CAP_IDX, ++ HPRE_DRV_ALG_BITMAP_CAP_IDX, ++ HPRE_DEV_ALG_BITMAP_CAP_IDX, ++}; ++ ++static const u32 hpre_pre_store_caps[] = { ++ HPRE_CLUSTER_NUM_CAP, ++ HPRE_CORE_ENABLE_BITMAP_CAP, ++ HPRE_DRV_ALG_BITMAP_CAP, ++ HPRE_DEV_ALG_BITMAP_CAP, ++}; ++ + static const struct hpre_hw_error hpre_hw_errors[] = { + { + .int_msk = BIT(0), +@@ -345,7 +359,7 @@ bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg) + { + u32 cap_val; + +- cap_val = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DRV_ALG_BITMAP_CAP, qm->cap_ver); ++ cap_val = qm->cap_tables.dev_cap_table[HPRE_DRV_ALG_BITMAP_CAP_IDX].cap_val; + if (alg & cap_val) + return true; + +@@ -421,16 +435,6 @@ static u32 vfs_num; + module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); + MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); + +-static inline int hpre_cluster_num(struct hisi_qm *qm) +-{ +- return hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CLUSTER_NUM_CAP, qm->cap_ver); +-} +- +-static inline int hpre_cluster_core_mask(struct hisi_qm *qm) +-{ +- return hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CORE_ENABLE_BITMAP_CAP, qm->cap_ver); +-} +- + struct hisi_qp *hpre_create_qp(u8 type) + { + int node = cpu_to_node(smp_processor_id()); +@@ -497,13 +501,15 @@ static int hpre_cfg_by_dsm(struct hisi_qm *qm) + + static int hpre_set_cluster(struct hisi_qm *qm) + { +- u32 cluster_core_mask = hpre_cluster_core_mask(qm); +- u8 clusters_num = hpre_cluster_num(qm); + struct device *dev = &qm->pdev->dev; + unsigned long offset; ++ u32 cluster_core_mask; ++ u8 clusters_num; + u32 val = 0; + int ret, i; + ++ cluster_core_mask = qm->cap_tables.dev_cap_table[HPRE_CORE_ENABLE_BITMAP_CAP_IDX].cap_val; ++ clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val; + for (i = 0; i < clusters_num; i++) { + offset = i * HPRE_CLSTR_ADDR_INTRVL; + +@@ -698,11 +704,12 @@ static int hpre_set_user_domain_and_cache(struct hisi_qm *qm) + + static void hpre_cnt_regs_clear(struct hisi_qm *qm) + { +- u8 clusters_num = hpre_cluster_num(qm); + unsigned long offset; ++ u8 clusters_num; + int i; + + /* clear clusterX/cluster_ctrl */ ++ clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val; + for (i = 0; i < clusters_num; i++) { + offset = HPRE_CLSTR_BASE + i * HPRE_CLSTR_ADDR_INTRVL; + writel(0x0, qm->io_base + offset + HPRE_CLUSTER_INQURY); +@@ -989,13 +996,14 @@ static int hpre_pf_comm_regs_debugfs_init(struct hisi_qm *qm) + + static int hpre_cluster_debugfs_init(struct hisi_qm *qm) + { +- u8 clusters_num = hpre_cluster_num(qm); + struct device *dev = &qm->pdev->dev; + char buf[HPRE_DBGFS_VAL_MAX_LEN]; + struct debugfs_regset32 *regset; + struct dentry *tmp_d; ++ u8 clusters_num; + int i, ret; + ++ clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val; + for (i = 0; i < clusters_num; i++) { + ret = snprintf(buf, HPRE_DBGFS_VAL_MAX_LEN, "cluster%d", i); + if (ret >= HPRE_DBGFS_VAL_MAX_LEN) +@@ -1100,6 +1108,34 @@ static void hpre_debugfs_exit(struct hisi_qm *qm) + debugfs_remove_recursive(qm->debug.debug_root); + } + ++static int hpre_pre_store_cap_reg(struct hisi_qm *qm) ++{ ++ struct hisi_qm_cap_record *hpre_cap; ++ struct device *dev = &qm->pdev->dev; ++ size_t i, size; ++ ++ size = ARRAY_SIZE(hpre_pre_store_caps); ++ hpre_cap = devm_kzalloc(dev, sizeof(*hpre_cap) * size, GFP_KERNEL); ++ if (!hpre_cap) ++ return -ENOMEM; ++ ++ for (i = 0; i < size; i++) { ++ hpre_cap[i].type = hpre_pre_store_caps[i]; ++ hpre_cap[i].cap_val = hisi_qm_get_hw_info(qm, hpre_basic_info, ++ hpre_pre_store_caps[i], qm->cap_ver); ++ } ++ ++ if (hpre_cap[HPRE_CLUSTER_NUM_CAP_IDX].cap_val > HPRE_CLUSTERS_NUM_MAX) { ++ dev_err(dev, "Device cluster num %u is out of range for driver supports %d!\n", ++ hpre_cap[HPRE_CLUSTER_NUM_CAP_IDX].cap_val, HPRE_CLUSTERS_NUM_MAX); ++ return -EINVAL; ++ } ++ ++ qm->cap_tables.dev_cap_table = hpre_cap; ++ ++ return 0; ++} ++ + static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) + { + u64 alg_msk; +@@ -1133,7 +1169,15 @@ static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) + return ret; + } + +- alg_msk = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DEV_ALG_BITMAP_CAP, qm->cap_ver); ++ /* Fetch and save the value of capability registers */ ++ ret = hpre_pre_store_cap_reg(qm); ++ if (ret) { ++ pci_err(pdev, "Failed to pre-store capability registers!\n"); ++ hisi_qm_uninit(qm); ++ return ret; ++ } ++ ++ alg_msk = qm->cap_tables.dev_cap_table[HPRE_DEV_ALG_BITMAP_CAP_IDX].cap_val; + ret = hisi_qm_set_algs(qm, alg_msk, hpre_dev_algs, ARRAY_SIZE(hpre_dev_algs)); + if (ret) { + pci_err(pdev, "Failed to set hpre algs!\n"); +@@ -1147,11 +1191,12 @@ static int hpre_show_last_regs_init(struct hisi_qm *qm) + { + int cluster_dfx_regs_num = ARRAY_SIZE(hpre_cluster_dfx_regs); + int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs); +- u8 clusters_num = hpre_cluster_num(qm); + struct qm_debug *debug = &qm->debug; + void __iomem *io_base; ++ u8 clusters_num; + int i, j, idx; + ++ clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val; + debug->last_words = kcalloc(cluster_dfx_regs_num * clusters_num + + com_dfx_regs_num, sizeof(unsigned int), GFP_KERNEL); + if (!debug->last_words) +@@ -1188,10 +1233,10 @@ static void hpre_show_last_dfx_regs(struct hisi_qm *qm) + { + int cluster_dfx_regs_num = ARRAY_SIZE(hpre_cluster_dfx_regs); + int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs); +- u8 clusters_num = hpre_cluster_num(qm); + struct qm_debug *debug = &qm->debug; + struct pci_dev *pdev = qm->pdev; + void __iomem *io_base; ++ u8 clusters_num; + int i, j, idx; + u32 val; + +@@ -1206,6 +1251,7 @@ static void hpre_show_last_dfx_regs(struct hisi_qm *qm) + hpre_com_dfx_regs[i].name, debug->last_words[i], val); + } + ++ clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val; + for (i = 0; i < clusters_num; i++) { + io_base = qm->io_base + hpre_cluster_offsets[i]; + for (j = 0; j < cluster_dfx_regs_num; j++) { +-- +2.43.0 + diff --git a/queue-6.1/crypto-hisilicon-qm-add-a-function-to-set-qm-algs.patch b/queue-6.1/crypto-hisilicon-qm-add-a-function-to-set-qm-algs.patch new file mode 100644 index 00000000000..175f5d1936e --- /dev/null +++ b/queue-6.1/crypto-hisilicon-qm-add-a-function-to-set-qm-algs.patch @@ -0,0 +1,385 @@ +From bc1332dd8cf25152825087606f8825ef90b9fb59 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 2 Dec 2023 17:17:18 +0800 +Subject: crypto: hisilicon/qm - add a function to set qm algs + +From: Wenkai Lin + +[ Upstream commit f76f0d7f20672611974d3cc705996751fc403734 ] + +Extract a public function to set qm algs and remove +the similar code for setting qm algs in each module. + +Signed-off-by: Wenkai Lin +Signed-off-by: Hao Fang +Signed-off-by: Zhiqi Song +Signed-off-by: Herbert Xu +Stable-dep-of: cf8b5156bbc8 ("crypto: hisilicon/hpre - save capability registers in probe process") +Signed-off-by: Sasha Levin +--- + drivers/crypto/hisilicon/hpre/hpre_main.c | 42 ++----------------- + drivers/crypto/hisilicon/qm.c | 36 +++++++++++++++++ + drivers/crypto/hisilicon/sec2/sec_main.c | 47 ++++------------------ + drivers/crypto/hisilicon/zip/zip_main.c | 49 ++++------------------- + include/linux/hisi_acc_qm.h | 8 +++- + 5 files changed, 62 insertions(+), 120 deletions(-) + +diff --git a/drivers/crypto/hisilicon/hpre/hpre_main.c b/drivers/crypto/hisilicon/hpre/hpre_main.c +index ff8a5f20a5df..cf02c9cde85a 100644 +--- a/drivers/crypto/hisilicon/hpre/hpre_main.c ++++ b/drivers/crypto/hisilicon/hpre/hpre_main.c +@@ -118,8 +118,6 @@ + #define HPRE_DFX_COMMON2_LEN 0xE + #define HPRE_DFX_CORE_LEN 0x43 + +-#define HPRE_DEV_ALG_MAX_LEN 256 +- + static const char hpre_name[] = "hisi_hpre"; + static struct dentry *hpre_debugfs_root; + static const struct pci_device_id hpre_dev_ids[] = { +@@ -135,12 +133,7 @@ struct hpre_hw_error { + const char *msg; + }; + +-struct hpre_dev_alg { +- u32 alg_msk; +- const char *alg; +-}; +- +-static const struct hpre_dev_alg hpre_dev_algs[] = { ++static const struct qm_dev_alg hpre_dev_algs[] = { + { + .alg_msk = BIT(0), + .alg = "rsa\n" +@@ -359,35 +352,6 @@ bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg) + return false; + } + +-static int hpre_set_qm_algs(struct hisi_qm *qm) +-{ +- struct device *dev = &qm->pdev->dev; +- char *algs, *ptr; +- u32 alg_msk; +- int i; +- +- if (!qm->use_sva) +- return 0; +- +- algs = devm_kzalloc(dev, HPRE_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL); +- if (!algs) +- return -ENOMEM; +- +- alg_msk = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DEV_ALG_BITMAP_CAP, qm->cap_ver); +- +- for (i = 0; i < ARRAY_SIZE(hpre_dev_algs); i++) +- if (alg_msk & hpre_dev_algs[i].alg_msk) +- strcat(algs, hpre_dev_algs[i].alg); +- +- ptr = strrchr(algs, '\n'); +- if (ptr) +- *ptr = '\0'; +- +- qm->uacce->algs = algs; +- +- return 0; +-} +- + static int hpre_diff_regs_show(struct seq_file *s, void *unused) + { + struct hisi_qm *qm = s->private; +@@ -1138,6 +1102,7 @@ static void hpre_debugfs_exit(struct hisi_qm *qm) + + static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) + { ++ u64 alg_msk; + int ret; + + if (pdev->revision == QM_HW_V1) { +@@ -1168,7 +1133,8 @@ static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) + return ret; + } + +- ret = hpre_set_qm_algs(qm); ++ alg_msk = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DEV_ALG_BITMAP_CAP, qm->cap_ver); ++ ret = hisi_qm_set_algs(qm, alg_msk, hpre_dev_algs, ARRAY_SIZE(hpre_dev_algs)); + if (ret) { + pci_err(pdev, "Failed to set hpre algs!\n"); + hisi_qm_uninit(qm); +diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c +index d4c6a601c5f2..5539be1bfb40 100644 +--- a/drivers/crypto/hisilicon/qm.c ++++ b/drivers/crypto/hisilicon/qm.c +@@ -237,6 +237,8 @@ + #define QM_QOS_MAX_CIR_S 11 + #define QM_AUTOSUSPEND_DELAY 3000 + ++#define QM_DEV_ALG_MAX_LEN 256 ++ + #define QM_MK_CQC_DW3_V1(hop_num, pg_sz, buf_sz, cqe_sz) \ + (((hop_num) << QM_CQ_HOP_NUM_SHIFT) | \ + ((pg_sz) << QM_CQ_PAGE_SIZE_SHIFT) | \ +@@ -795,6 +797,40 @@ static void qm_get_xqc_depth(struct hisi_qm *qm, u16 *low_bits, + *high_bits = (depth >> QM_XQ_DEPTH_SHIFT) & QM_XQ_DEPTH_MASK; + } + ++int hisi_qm_set_algs(struct hisi_qm *qm, u64 alg_msk, const struct qm_dev_alg *dev_algs, ++ u32 dev_algs_size) ++{ ++ struct device *dev = &qm->pdev->dev; ++ char *algs, *ptr; ++ int i; ++ ++ if (!qm->uacce) ++ return 0; ++ ++ if (dev_algs_size >= QM_DEV_ALG_MAX_LEN) { ++ dev_err(dev, "algs size %u is equal or larger than %d.\n", ++ dev_algs_size, QM_DEV_ALG_MAX_LEN); ++ return -EINVAL; ++ } ++ ++ algs = devm_kzalloc(dev, QM_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL); ++ if (!algs) ++ return -ENOMEM; ++ ++ for (i = 0; i < dev_algs_size; i++) ++ if (alg_msk & dev_algs[i].alg_msk) ++ strcat(algs, dev_algs[i].alg); ++ ++ ptr = strrchr(algs, '\n'); ++ if (ptr) { ++ *ptr = '\0'; ++ qm->uacce->algs = algs; ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(hisi_qm_set_algs); ++ + static u32 qm_get_irq_num(struct hisi_qm *qm) + { + if (qm->fun_type == QM_HW_PF) +diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisilicon/sec2/sec_main.c +index e384988bda91..3605f610699c 100644 +--- a/drivers/crypto/hisilicon/sec2/sec_main.c ++++ b/drivers/crypto/hisilicon/sec2/sec_main.c +@@ -121,7 +121,6 @@ + GENMASK_ULL(42, 25)) + #define SEC_AEAD_BITMAP (GENMASK_ULL(7, 6) | GENMASK_ULL(18, 17) | \ + GENMASK_ULL(45, 43)) +-#define SEC_DEV_ALG_MAX_LEN 256 + + struct sec_hw_error { + u32 int_msk; +@@ -133,11 +132,6 @@ struct sec_dfx_item { + u32 offset; + }; + +-struct sec_dev_alg { +- u64 alg_msk; +- const char *algs; +-}; +- + static const char sec_name[] = "hisi_sec2"; + static struct dentry *sec_debugfs_root; + +@@ -174,15 +168,15 @@ static const struct hisi_qm_cap_info sec_basic_info[] = { + {SEC_CORE4_ALG_BITMAP_HIGH, 0x3170, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF}, + }; + +-static const struct sec_dev_alg sec_dev_algs[] = { { ++static const struct qm_dev_alg sec_dev_algs[] = { { + .alg_msk = SEC_CIPHER_BITMAP, +- .algs = "cipher\n", ++ .alg = "cipher\n", + }, { + .alg_msk = SEC_DIGEST_BITMAP, +- .algs = "digest\n", ++ .alg = "digest\n", + }, { + .alg_msk = SEC_AEAD_BITMAP, +- .algs = "aead\n", ++ .alg = "aead\n", + }, + }; + +@@ -1079,37 +1073,9 @@ static int sec_pf_probe_init(struct sec_dev *sec) + return ret; + } + +-static int sec_set_qm_algs(struct hisi_qm *qm) +-{ +- struct device *dev = &qm->pdev->dev; +- char *algs, *ptr; +- u64 alg_mask; +- int i; +- +- if (!qm->use_sva) +- return 0; +- +- algs = devm_kzalloc(dev, SEC_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL); +- if (!algs) +- return -ENOMEM; +- +- alg_mask = sec_get_alg_bitmap(qm, SEC_DEV_ALG_BITMAP_HIGH, SEC_DEV_ALG_BITMAP_LOW); +- +- for (i = 0; i < ARRAY_SIZE(sec_dev_algs); i++) +- if (alg_mask & sec_dev_algs[i].alg_msk) +- strcat(algs, sec_dev_algs[i].algs); +- +- ptr = strrchr(algs, '\n'); +- if (ptr) +- *ptr = '\0'; +- +- qm->uacce->algs = algs; +- +- return 0; +-} +- + static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) + { ++ u64 alg_msk; + int ret; + + qm->pdev = pdev; +@@ -1144,7 +1110,8 @@ static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) + return ret; + } + +- ret = sec_set_qm_algs(qm); ++ alg_msk = sec_get_alg_bitmap(qm, SEC_DEV_ALG_BITMAP_HIGH, SEC_DEV_ALG_BITMAP_LOW); ++ ret = hisi_qm_set_algs(qm, alg_msk, sec_dev_algs, ARRAY_SIZE(sec_dev_algs)); + if (ret) { + pci_err(qm->pdev, "Failed to set sec algs!\n"); + hisi_qm_uninit(qm); +diff --git a/drivers/crypto/hisilicon/zip/zip_main.c b/drivers/crypto/hisilicon/zip/zip_main.c +index 2c5e805ffdc3..a7a2091b6560 100644 +--- a/drivers/crypto/hisilicon/zip/zip_main.c ++++ b/drivers/crypto/hisilicon/zip/zip_main.c +@@ -74,7 +74,6 @@ + #define HZIP_AXI_SHUTDOWN_ENABLE BIT(14) + #define HZIP_WR_PORT BIT(11) + +-#define HZIP_DEV_ALG_MAX_LEN 256 + #define HZIP_ALG_ZLIB_BIT GENMASK(1, 0) + #define HZIP_ALG_GZIP_BIT GENMASK(3, 2) + #define HZIP_ALG_DEFLATE_BIT GENMASK(5, 4) +@@ -128,23 +127,18 @@ struct zip_dfx_item { + u32 offset; + }; + +-struct zip_dev_alg { +- u32 alg_msk; +- const char *algs; +-}; +- +-static const struct zip_dev_alg zip_dev_algs[] = { { ++static const struct qm_dev_alg zip_dev_algs[] = { { + .alg_msk = HZIP_ALG_ZLIB_BIT, +- .algs = "zlib\n", ++ .alg = "zlib\n", + }, { + .alg_msk = HZIP_ALG_GZIP_BIT, +- .algs = "gzip\n", ++ .alg = "gzip\n", + }, { + .alg_msk = HZIP_ALG_DEFLATE_BIT, +- .algs = "deflate\n", ++ .alg = "deflate\n", + }, { + .alg_msk = HZIP_ALG_LZ77_BIT, +- .algs = "lz77_zstd\n", ++ .alg = "lz77_zstd\n", + }, + }; + +@@ -478,35 +472,6 @@ static int hisi_zip_set_high_perf(struct hisi_qm *qm) + return ret; + } + +-static int hisi_zip_set_qm_algs(struct hisi_qm *qm) +-{ +- struct device *dev = &qm->pdev->dev; +- char *algs, *ptr; +- u32 alg_mask; +- int i; +- +- if (!qm->use_sva) +- return 0; +- +- algs = devm_kzalloc(dev, HZIP_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL); +- if (!algs) +- return -ENOMEM; +- +- alg_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DEV_ALG_BITMAP, qm->cap_ver); +- +- for (i = 0; i < ARRAY_SIZE(zip_dev_algs); i++) +- if (alg_mask & zip_dev_algs[i].alg_msk) +- strcat(algs, zip_dev_algs[i].algs); +- +- ptr = strrchr(algs, '\n'); +- if (ptr) +- *ptr = '\0'; +- +- qm->uacce->algs = algs; +- +- return 0; +-} +- + static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm) + { + u32 val; +@@ -1193,6 +1158,7 @@ static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip) + + static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) + { ++ u64 alg_msk; + int ret; + + qm->pdev = pdev; +@@ -1228,7 +1194,8 @@ static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) + return ret; + } + +- ret = hisi_zip_set_qm_algs(qm); ++ alg_msk = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DEV_ALG_BITMAP, qm->cap_ver); ++ ret = hisi_qm_set_algs(qm, alg_msk, zip_dev_algs, ARRAY_SIZE(zip_dev_algs)); + if (ret) { + pci_err(qm->pdev, "Failed to set zip algs!\n"); + hisi_qm_uninit(qm); +diff --git a/include/linux/hisi_acc_qm.h b/include/linux/hisi_acc_qm.h +index 241b0dc3183e..b566ae420449 100644 +--- a/include/linux/hisi_acc_qm.h ++++ b/include/linux/hisi_acc_qm.h +@@ -161,6 +161,11 @@ enum qm_cap_bits { + QM_SUPPORT_RPM, + }; + ++struct qm_dev_alg { ++ u64 alg_msk; ++ const char *alg; ++}; ++ + struct dfx_diff_registers { + u32 *regs; + u32 reg_offset; +@@ -347,7 +352,6 @@ struct hisi_qm { + struct work_struct rst_work; + struct work_struct cmd_process; + +- const char *algs; + bool use_sva; + bool is_frozen; + +@@ -533,6 +537,8 @@ void hisi_qm_regs_dump(struct seq_file *s, struct debugfs_regset32 *regset); + u32 hisi_qm_get_hw_info(struct hisi_qm *qm, + const struct hisi_qm_cap_info *info_table, + u32 index, bool is_read); ++int hisi_qm_set_algs(struct hisi_qm *qm, u64 alg_msk, const struct qm_dev_alg *dev_algs, ++ u32 dev_algs_size); + + /* Used by VFIO ACC live migration driver */ + struct pci_driver *hisi_sec_get_pf_driver(void); +-- +2.43.0 + diff --git a/queue-6.1/crypto-hisilicon-qm-save-capability-registers-in-qm-.patch b/queue-6.1/crypto-hisilicon-qm-save-capability-registers-in-qm-.patch new file mode 100644 index 00000000000..2fe91c31536 --- /dev/null +++ b/queue-6.1/crypto-hisilicon-qm-save-capability-registers-in-qm-.patch @@ -0,0 +1,257 @@ +From bbddf2e188c35ec55a6957bb005e2615fbc053e6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 2 Dec 2023 17:17:19 +0800 +Subject: crypto: hisilicon/qm - save capability registers in qm init process + +From: Zhiqi Song + +[ Upstream commit cabe13d0bd2efb8dd50ed2310f57b33e1a69a0d4 ] + +In previous capability register implementation, qm irq related values +were read from capability registers dynamically when needed. But in +abnormal scenario, e.g. the core is timeout and the device needs to +soft reset and reset failed after disabling the MSE, the device can +not be removed normally, causing the following call trace: + + | Call trace: + | pci_irq_vector+0xfc/0x140 + | hisi_qm_uninit+0x278/0x3b0 [hisi_qm] + | hpre_remove+0x16c/0x1c0 [hisi_hpre] + | pci_device_remove+0x6c/0x264 + | device_release_driver_internal+0x1ec/0x3e0 + | device_release_driver+0x3c/0x60 + | pci_stop_bus_device+0xfc/0x22c + | pci_stop_and_remove_bus_device+0x38/0x70 + | pci_iov_remove_virtfn+0x108/0x1c0 + | sriov_disable+0x7c/0x1e4 + | pci_disable_sriov+0x4c/0x6c + | hisi_qm_sriov_disable+0x90/0x160 [hisi_qm] + | hpre_remove+0x1a8/0x1c0 [hisi_hpre] + | pci_device_remove+0x6c/0x264 + | device_release_driver_internal+0x1ec/0x3e0 + | driver_detach+0x168/0x2d0 + | bus_remove_driver+0xc0/0x230 + | driver_unregister+0x58/0xdc + | pci_unregister_driver+0x40/0x220 + | hpre_exit+0x34/0x64 [hisi_hpre] + | __arm64_sys_delete_module+0x374/0x620 + [...] + + | Call trace: + | free_msi_irqs+0x25c/0x300 + | pci_disable_msi+0x19c/0x264 + | pci_free_irq_vectors+0x4c/0x70 + | hisi_qm_pci_uninit+0x44/0x90 [hisi_qm] + | hisi_qm_uninit+0x28c/0x3b0 [hisi_qm] + | hpre_remove+0x16c/0x1c0 [hisi_hpre] + | pci_device_remove+0x6c/0x264 + [...] + +The reason for this call trace is that when the MSE is disabled, the value +of capability registers in the BAR space become invalid. This will make the +subsequent unregister process get the wrong irq vector through capability +registers and get the wrong irq number by pci_irq_vector(). + +So add a capability table structure to pre-store the valid value of the irq +information capability register in qm init process, avoid obtaining invalid +capability register value after the MSE is disabled. + +Fixes: 3536cc55cada ("crypto: hisilicon/qm - support get device irq information from hardware registers") +Signed-off-by: Zhiqi Song +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/hisilicon/qm.c | 62 +++++++++++++++++++++++++++++------ + include/linux/hisi_acc_qm.h | 12 +++++++ + 2 files changed, 64 insertions(+), 10 deletions(-) + +diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c +index f9acf7ecc41b..d4c6a601c5f2 100644 +--- a/drivers/crypto/hisilicon/qm.c ++++ b/drivers/crypto/hisilicon/qm.c +@@ -315,6 +315,13 @@ enum qm_basic_type { + QM_VF_IRQ_NUM_CAP, + }; + ++enum qm_pre_store_cap_idx { ++ QM_EQ_IRQ_TYPE_CAP_IDX = 0x0, ++ QM_AEQ_IRQ_TYPE_CAP_IDX, ++ QM_ABN_IRQ_TYPE_CAP_IDX, ++ QM_PF2VF_IRQ_TYPE_CAP_IDX, ++}; ++ + static const struct hisi_qm_cap_info qm_cap_info_comm[] = { + {QM_SUPPORT_DB_ISOLATION, 0x30, 0, BIT(0), 0x0, 0x0, 0x0}, + {QM_SUPPORT_FUNC_QOS, 0x3100, 0, BIT(8), 0x0, 0x0, 0x1}, +@@ -344,6 +351,13 @@ static const struct hisi_qm_cap_info qm_basic_info[] = { + {QM_VF_IRQ_NUM_CAP, 0x311c, 0, GENMASK(15, 0), 0x1, 0x2, 0x3}, + }; + ++static const u32 qm_pre_store_caps[] = { ++ QM_EQ_IRQ_TYPE_CAP, ++ QM_AEQ_IRQ_TYPE_CAP, ++ QM_ABN_IRQ_TYPE_CAP, ++ QM_PF2VF_IRQ_TYPE_CAP, ++}; ++ + struct qm_mailbox { + __le16 w0; + __le16 queue_num; +@@ -4804,7 +4818,7 @@ static void qm_unregister_abnormal_irq(struct hisi_qm *qm) + if (qm->fun_type == QM_HW_VF) + return; + +- val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_ABN_IRQ_TYPE_CAP, qm->cap_ver); ++ val = qm->cap_tables.qm_cap_table[QM_ABN_IRQ_TYPE_CAP_IDX].cap_val; + if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_ABN_IRQ_TYPE_MASK)) + return; + +@@ -4821,7 +4835,7 @@ static int qm_register_abnormal_irq(struct hisi_qm *qm) + if (qm->fun_type == QM_HW_VF) + return 0; + +- val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_ABN_IRQ_TYPE_CAP, qm->cap_ver); ++ val = qm->cap_tables.qm_cap_table[QM_ABN_IRQ_TYPE_CAP_IDX].cap_val; + if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_ABN_IRQ_TYPE_MASK)) + return 0; + +@@ -4838,7 +4852,7 @@ static void qm_unregister_mb_cmd_irq(struct hisi_qm *qm) + struct pci_dev *pdev = qm->pdev; + u32 irq_vector, val; + +- val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_PF2VF_IRQ_TYPE_CAP, qm->cap_ver); ++ val = qm->cap_tables.qm_cap_table[QM_PF2VF_IRQ_TYPE_CAP_IDX].cap_val; + if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK)) + return; + +@@ -4852,7 +4866,7 @@ static int qm_register_mb_cmd_irq(struct hisi_qm *qm) + u32 irq_vector, val; + int ret; + +- val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_PF2VF_IRQ_TYPE_CAP, qm->cap_ver); ++ val = qm->cap_tables.qm_cap_table[QM_PF2VF_IRQ_TYPE_CAP_IDX].cap_val; + if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK)) + return 0; + +@@ -4869,7 +4883,7 @@ static void qm_unregister_aeq_irq(struct hisi_qm *qm) + struct pci_dev *pdev = qm->pdev; + u32 irq_vector, val; + +- val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_AEQ_IRQ_TYPE_CAP, qm->cap_ver); ++ val = qm->cap_tables.qm_cap_table[QM_AEQ_IRQ_TYPE_CAP_IDX].cap_val; + if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK)) + return; + +@@ -4883,7 +4897,7 @@ static int qm_register_aeq_irq(struct hisi_qm *qm) + u32 irq_vector, val; + int ret; + +- val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_AEQ_IRQ_TYPE_CAP, qm->cap_ver); ++ val = qm->cap_tables.qm_cap_table[QM_AEQ_IRQ_TYPE_CAP_IDX].cap_val; + if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK)) + return 0; + +@@ -4901,7 +4915,7 @@ static void qm_unregister_eq_irq(struct hisi_qm *qm) + struct pci_dev *pdev = qm->pdev; + u32 irq_vector, val; + +- val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_EQ_IRQ_TYPE_CAP, qm->cap_ver); ++ val = qm->cap_tables.qm_cap_table[QM_EQ_IRQ_TYPE_CAP_IDX].cap_val; + if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK)) + return; + +@@ -4915,7 +4929,7 @@ static int qm_register_eq_irq(struct hisi_qm *qm) + u32 irq_vector, val; + int ret; + +- val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_EQ_IRQ_TYPE_CAP, qm->cap_ver); ++ val = qm->cap_tables.qm_cap_table[QM_EQ_IRQ_TYPE_CAP_IDX].cap_val; + if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK)) + return 0; + +@@ -5003,7 +5017,29 @@ static int qm_get_qp_num(struct hisi_qm *qm) + return 0; + } + +-static void qm_get_hw_caps(struct hisi_qm *qm) ++static int qm_pre_store_irq_type_caps(struct hisi_qm *qm) ++{ ++ struct hisi_qm_cap_record *qm_cap; ++ struct pci_dev *pdev = qm->pdev; ++ size_t i, size; ++ ++ size = ARRAY_SIZE(qm_pre_store_caps); ++ qm_cap = devm_kzalloc(&pdev->dev, sizeof(*qm_cap) * size, GFP_KERNEL); ++ if (!qm_cap) ++ return -ENOMEM; ++ ++ for (i = 0; i < size; i++) { ++ qm_cap[i].type = qm_pre_store_caps[i]; ++ qm_cap[i].cap_val = hisi_qm_get_hw_info(qm, qm_basic_info, ++ qm_pre_store_caps[i], qm->cap_ver); ++ } ++ ++ qm->cap_tables.qm_cap_table = qm_cap; ++ ++ return 0; ++} ++ ++static int qm_get_hw_caps(struct hisi_qm *qm) + { + const struct hisi_qm_cap_info *cap_info = qm->fun_type == QM_HW_PF ? + qm_cap_info_pf : qm_cap_info_vf; +@@ -5034,6 +5070,9 @@ static void qm_get_hw_caps(struct hisi_qm *qm) + if (val) + set_bit(cap_info[i].type, &qm->caps); + } ++ ++ /* Fetch and save the value of irq type related capability registers */ ++ return qm_pre_store_irq_type_caps(qm); + } + + static int qm_get_pci_res(struct hisi_qm *qm) +@@ -5055,7 +5094,10 @@ static int qm_get_pci_res(struct hisi_qm *qm) + goto err_request_mem_regions; + } + +- qm_get_hw_caps(qm); ++ ret = qm_get_hw_caps(qm); ++ if (ret) ++ goto err_ioremap; ++ + if (test_bit(QM_SUPPORT_DB_ISOLATION, &qm->caps)) { + qm->db_interval = QM_QP_DB_INTERVAL; + qm->db_phys_base = pci_resource_start(pdev, PCI_BAR_4); +diff --git a/include/linux/hisi_acc_qm.h b/include/linux/hisi_acc_qm.h +index 41203ce27d64..241b0dc3183e 100644 +--- a/include/linux/hisi_acc_qm.h ++++ b/include/linux/hisi_acc_qm.h +@@ -266,6 +266,16 @@ struct hisi_qm_cap_info { + u32 v3_val; + }; + ++struct hisi_qm_cap_record { ++ u32 type; ++ u32 cap_val; ++}; ++ ++struct hisi_qm_cap_tables { ++ struct hisi_qm_cap_record *qm_cap_table; ++ struct hisi_qm_cap_record *dev_cap_table; ++}; ++ + struct hisi_qm_list { + struct mutex lock; + struct list_head list; +@@ -348,6 +358,8 @@ struct hisi_qm { + struct qm_shaper_factor *factor; + u32 mb_qos; + u32 type_rate; ++ ++ struct hisi_qm_cap_tables cap_tables; + }; + + struct hisi_qp_status { +-- +2.43.0 + diff --git a/queue-6.1/crypto-hisilicon-sec2-save-capability-registers-in-p.patch b/queue-6.1/crypto-hisilicon-sec2-save-capability-registers-in-p.patch new file mode 100644 index 00000000000..a2c58d5f951 --- /dev/null +++ b/queue-6.1/crypto-hisilicon-sec2-save-capability-registers-in-p.patch @@ -0,0 +1,152 @@ +From 3292574633802cdcd54bd2685f13a410d7dae05b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 2 Dec 2023 17:17:21 +0800 +Subject: crypto: hisilicon/sec2 - save capability registers in probe process + +From: Zhiqi Song + +[ Upstream commit f1115b0096c3163592e04e74f5a7548c25bda957 ] + +Pre-store the valid value of the sec alg support related capability +register in sec_qm_init(), which will be called by probe process. +It can reduce the number of capability register queries and avoid +obtaining incorrect values in abnormal scenarios, such as reset +failed and the memory space disabled. + +Fixes: 921715b6b782 ("crypto: hisilicon/sec - get algorithm bitmap from registers") +Signed-off-by: Zhiqi Song +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/hisilicon/sec2/sec.h | 7 ++++ + drivers/crypto/hisilicon/sec2/sec_crypto.c | 13 +++++-- + drivers/crypto/hisilicon/sec2/sec_main.c | 43 ++++++++++++++++++++-- + 3 files changed, 57 insertions(+), 6 deletions(-) + +diff --git a/drivers/crypto/hisilicon/sec2/sec.h b/drivers/crypto/hisilicon/sec2/sec.h +index 3e57fc04b377..410c83712e28 100644 +--- a/drivers/crypto/hisilicon/sec2/sec.h ++++ b/drivers/crypto/hisilicon/sec2/sec.h +@@ -220,6 +220,13 @@ enum sec_cap_type { + SEC_CORE4_ALG_BITMAP_HIGH, + }; + ++enum sec_cap_reg_record_idx { ++ SEC_DRV_ALG_BITMAP_LOW_IDX = 0x0, ++ SEC_DRV_ALG_BITMAP_HIGH_IDX, ++ SEC_DEV_ALG_BITMAP_LOW_IDX, ++ SEC_DEV_ALG_BITMAP_HIGH_IDX, ++}; ++ + void sec_destroy_qps(struct hisi_qp **qps, int qp_num); + struct hisi_qp **sec_create_qps(void); + int sec_register_to_crypto(struct hisi_qm *qm); +diff --git a/drivers/crypto/hisilicon/sec2/sec_crypto.c b/drivers/crypto/hisilicon/sec2/sec_crypto.c +index 84ae8ddd1a13..cae7c414bdaf 100644 +--- a/drivers/crypto/hisilicon/sec2/sec_crypto.c ++++ b/drivers/crypto/hisilicon/sec2/sec_crypto.c +@@ -2546,8 +2546,12 @@ static int sec_register_aead(u64 alg_mask) + + int sec_register_to_crypto(struct hisi_qm *qm) + { +- u64 alg_mask = sec_get_alg_bitmap(qm, SEC_DRV_ALG_BITMAP_HIGH, SEC_DRV_ALG_BITMAP_LOW); +- int ret; ++ u64 alg_mask; ++ int ret = 0; ++ ++ alg_mask = sec_get_alg_bitmap(qm, SEC_DRV_ALG_BITMAP_HIGH_IDX, ++ SEC_DRV_ALG_BITMAP_LOW_IDX); ++ + + ret = sec_register_skcipher(alg_mask); + if (ret) +@@ -2562,7 +2566,10 @@ int sec_register_to_crypto(struct hisi_qm *qm) + + void sec_unregister_from_crypto(struct hisi_qm *qm) + { +- u64 alg_mask = sec_get_alg_bitmap(qm, SEC_DRV_ALG_BITMAP_HIGH, SEC_DRV_ALG_BITMAP_LOW); ++ u64 alg_mask; ++ ++ alg_mask = sec_get_alg_bitmap(qm, SEC_DRV_ALG_BITMAP_HIGH_IDX, ++ SEC_DRV_ALG_BITMAP_LOW_IDX); + + sec_unregister_aead(alg_mask, ARRAY_SIZE(sec_aeads)); + sec_unregister_skcipher(alg_mask, ARRAY_SIZE(sec_skciphers)); +diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisilicon/sec2/sec_main.c +index 3605f610699c..4bab5000a13e 100644 +--- a/drivers/crypto/hisilicon/sec2/sec_main.c ++++ b/drivers/crypto/hisilicon/sec2/sec_main.c +@@ -168,6 +168,13 @@ static const struct hisi_qm_cap_info sec_basic_info[] = { + {SEC_CORE4_ALG_BITMAP_HIGH, 0x3170, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF}, + }; + ++static const u32 sec_pre_store_caps[] = { ++ SEC_DRV_ALG_BITMAP_LOW, ++ SEC_DRV_ALG_BITMAP_HIGH, ++ SEC_DEV_ALG_BITMAP_LOW, ++ SEC_DEV_ALG_BITMAP_HIGH, ++}; ++ + static const struct qm_dev_alg sec_dev_algs[] = { { + .alg_msk = SEC_CIPHER_BITMAP, + .alg = "cipher\n", +@@ -389,8 +396,8 @@ u64 sec_get_alg_bitmap(struct hisi_qm *qm, u32 high, u32 low) + { + u32 cap_val_h, cap_val_l; + +- cap_val_h = hisi_qm_get_hw_info(qm, sec_basic_info, high, qm->cap_ver); +- cap_val_l = hisi_qm_get_hw_info(qm, sec_basic_info, low, qm->cap_ver); ++ cap_val_h = qm->cap_tables.dev_cap_table[high].cap_val; ++ cap_val_l = qm->cap_tables.dev_cap_table[low].cap_val; + + return ((u64)cap_val_h << SEC_ALG_BITMAP_SHIFT) | (u64)cap_val_l; + } +@@ -1073,6 +1080,28 @@ static int sec_pf_probe_init(struct sec_dev *sec) + return ret; + } + ++static int sec_pre_store_cap_reg(struct hisi_qm *qm) ++{ ++ struct hisi_qm_cap_record *sec_cap; ++ struct pci_dev *pdev = qm->pdev; ++ size_t i, size; ++ ++ size = ARRAY_SIZE(sec_pre_store_caps); ++ sec_cap = devm_kzalloc(&pdev->dev, sizeof(*sec_cap) * size, GFP_KERNEL); ++ if (!sec_cap) ++ return -ENOMEM; ++ ++ for (i = 0; i < size; i++) { ++ sec_cap[i].type = sec_pre_store_caps[i]; ++ sec_cap[i].cap_val = hisi_qm_get_hw_info(qm, sec_basic_info, ++ sec_pre_store_caps[i], qm->cap_ver); ++ } ++ ++ qm->cap_tables.dev_cap_table = sec_cap; ++ ++ return 0; ++} ++ + static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) + { + u64 alg_msk; +@@ -1110,7 +1139,15 @@ static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) + return ret; + } + +- alg_msk = sec_get_alg_bitmap(qm, SEC_DEV_ALG_BITMAP_HIGH, SEC_DEV_ALG_BITMAP_LOW); ++ /* Fetch and save the value of capability registers */ ++ ret = sec_pre_store_cap_reg(qm); ++ if (ret) { ++ pci_err(qm->pdev, "Failed to pre-store capability registers!\n"); ++ hisi_qm_uninit(qm); ++ return ret; ++ } ++ ++ alg_msk = sec_get_alg_bitmap(qm, SEC_DEV_ALG_BITMAP_HIGH_IDX, SEC_DEV_ALG_BITMAP_LOW_IDX); + ret = hisi_qm_set_algs(qm, alg_msk, sec_dev_algs, ARRAY_SIZE(sec_dev_algs)); + if (ret) { + pci_err(qm->pdev, "Failed to set sec algs!\n"); +-- +2.43.0 + diff --git a/queue-6.1/crypto-hisilicon-zip-add-zip-comp-high-perf-mode-con.patch b/queue-6.1/crypto-hisilicon-zip-add-zip-comp-high-perf-mode-con.patch new file mode 100644 index 00000000000..de845eb0b06 --- /dev/null +++ b/queue-6.1/crypto-hisilicon-zip-add-zip-comp-high-perf-mode-con.patch @@ -0,0 +1,125 @@ +From 6f5d234af3ab3c205e51641aefd2e429ece3f511 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 24 Nov 2023 13:49:24 +0800 +Subject: crypto: hisilicon/zip - add zip comp high perf mode configuration + +From: Chenghai Huang + +[ Upstream commit a9864bae1806499ebf3757a9e71dddde5b9c48c6 ] + +To meet specific application scenarios, the function of switching between +the high performance mode and the high compression mode is added. + +Use the perf_mode=0/1 configuration to set the compression high perf mode, +0(default, high compression mode), 1(high performance mode). These two +modes only apply to the compression direction and are compatible with +software algorithm in both directions. + +Signed-off-by: Chenghai Huang +Signed-off-by: Herbert Xu +Stable-dep-of: cf8b5156bbc8 ("crypto: hisilicon/hpre - save capability registers in probe process") +Signed-off-by: Sasha Levin +--- + drivers/crypto/hisilicon/zip/zip_main.c | 65 +++++++++++++++++++++++++ + 1 file changed, 65 insertions(+) + +diff --git a/drivers/crypto/hisilicon/zip/zip_main.c b/drivers/crypto/hisilicon/zip/zip_main.c +index 190b4fecfc74..2c5e805ffdc3 100644 +--- a/drivers/crypto/hisilicon/zip/zip_main.c ++++ b/drivers/crypto/hisilicon/zip/zip_main.c +@@ -107,6 +107,14 @@ + #define HZIP_CLOCK_GATED_EN (HZIP_CORE_GATED_EN | \ + HZIP_CORE_GATED_OOO_EN) + ++/* zip comp high performance */ ++#define HZIP_HIGH_PERF_OFFSET 0x301208 ++ ++enum { ++ HZIP_HIGH_COMP_RATE, ++ HZIP_HIGH_COMP_PERF, ++}; ++ + static const char hisi_zip_name[] = "hisi_zip"; + static struct dentry *hzip_debugfs_root; + +@@ -352,6 +360,37 @@ static int hzip_diff_regs_show(struct seq_file *s, void *unused) + return 0; + } + DEFINE_SHOW_ATTRIBUTE(hzip_diff_regs); ++ ++static int perf_mode_set(const char *val, const struct kernel_param *kp) ++{ ++ int ret; ++ u32 n; ++ ++ if (!val) ++ return -EINVAL; ++ ++ ret = kstrtou32(val, 10, &n); ++ if (ret != 0 || (n != HZIP_HIGH_COMP_PERF && ++ n != HZIP_HIGH_COMP_RATE)) ++ return -EINVAL; ++ ++ return param_set_int(val, kp); ++} ++ ++static const struct kernel_param_ops zip_com_perf_ops = { ++ .set = perf_mode_set, ++ .get = param_get_int, ++}; ++ ++/* ++ * perf_mode = 0 means enable high compression rate mode, ++ * perf_mode = 1 means enable high compression performance mode. ++ * These two modes only apply to the compression direction. ++ */ ++static u32 perf_mode = HZIP_HIGH_COMP_RATE; ++module_param_cb(perf_mode, &zip_com_perf_ops, &perf_mode, 0444); ++MODULE_PARM_DESC(perf_mode, "ZIP high perf mode 0(default), 1(enable)"); ++ + static const struct kernel_param_ops zip_uacce_mode_ops = { + .set = uacce_mode_set, + .get = param_get_int, +@@ -417,6 +456,28 @@ bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg) + return false; + } + ++static int hisi_zip_set_high_perf(struct hisi_qm *qm) ++{ ++ u32 val; ++ int ret; ++ ++ val = readl_relaxed(qm->io_base + HZIP_HIGH_PERF_OFFSET); ++ if (perf_mode == HZIP_HIGH_COMP_PERF) ++ val |= HZIP_HIGH_COMP_PERF; ++ else ++ val &= ~HZIP_HIGH_COMP_PERF; ++ ++ /* Set perf mode */ ++ writel(val, qm->io_base + HZIP_HIGH_PERF_OFFSET); ++ ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_HIGH_PERF_OFFSET, ++ val, val == perf_mode, HZIP_DELAY_1_US, ++ HZIP_POLL_TIMEOUT_US); ++ if (ret) ++ pci_err(qm->pdev, "failed to set perf mode\n"); ++ ++ return ret; ++} ++ + static int hisi_zip_set_qm_algs(struct hisi_qm *qm) + { + struct device *dev = &qm->pdev->dev; +@@ -1115,6 +1176,10 @@ static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip) + if (ret) + return ret; + ++ ret = hisi_zip_set_high_perf(qm); ++ if (ret) ++ return ret; ++ + hisi_zip_open_sva_prefetch(qm); + hisi_qm_dev_err_init(qm); + hisi_zip_debug_regs_clear(qm); +-- +2.43.0 + diff --git a/queue-6.1/crypto-hisilicon-zip-save-capability-registers-in-pr.patch b/queue-6.1/crypto-hisilicon-zip-save-capability-registers-in-pr.patch new file mode 100644 index 00000000000..52bacbc5873 --- /dev/null +++ b/queue-6.1/crypto-hisilicon-zip-save-capability-registers-in-pr.patch @@ -0,0 +1,159 @@ +From ac6d7cc33a7cdad5f8e262c7cd91f3ffa4092932 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 2 Dec 2023 17:17:22 +0800 +Subject: crypto: hisilicon/zip - save capability registers in probe process + +From: Zhiqi Song + +[ Upstream commit 2ff0ad847951d61c2d8b309e1ccefb26c57dcc7b ] + +Pre-store the valid value of the zip alg support related capability +register in hisi_zip_qm_init(), which will be called by hisi_zip_probe(). +It can reduce the number of capability register queries and avoid +obtaining incorrect values in abnormal scenarios, such as reset failed +and the memory space disabled. + +Fixes: db700974b69d ("crypto: hisilicon/zip - support zip capability") +Signed-off-by: Zhiqi Song +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/hisilicon/zip/zip_main.c | 73 ++++++++++++++++++++----- + 1 file changed, 60 insertions(+), 13 deletions(-) + +diff --git a/drivers/crypto/hisilicon/zip/zip_main.c b/drivers/crypto/hisilicon/zip/zip_main.c +index a7a2091b6560..9e3f5bca27de 100644 +--- a/drivers/crypto/hisilicon/zip/zip_main.c ++++ b/drivers/crypto/hisilicon/zip/zip_main.c +@@ -249,6 +249,26 @@ static struct hisi_qm_cap_info zip_basic_cap_info[] = { + {ZIP_CAP_MAX, 0x317c, 0, GENMASK(0, 0), 0x0, 0x0, 0x0} + }; + ++enum zip_pre_store_cap_idx { ++ ZIP_CORE_NUM_CAP_IDX = 0x0, ++ ZIP_CLUSTER_COMP_NUM_CAP_IDX, ++ ZIP_CLUSTER_DECOMP_NUM_CAP_IDX, ++ ZIP_DECOMP_ENABLE_BITMAP_IDX, ++ ZIP_COMP_ENABLE_BITMAP_IDX, ++ ZIP_DRV_ALG_BITMAP_IDX, ++ ZIP_DEV_ALG_BITMAP_IDX, ++}; ++ ++static const u32 zip_pre_store_caps[] = { ++ ZIP_CORE_NUM_CAP, ++ ZIP_CLUSTER_COMP_NUM_CAP, ++ ZIP_CLUSTER_DECOMP_NUM_CAP, ++ ZIP_DECOMP_ENABLE_BITMAP, ++ ZIP_COMP_ENABLE_BITMAP, ++ ZIP_DRV_ALG_BITMAP, ++ ZIP_DEV_ALG_BITMAP, ++}; ++ + enum { + HZIP_COMP_CORE0, + HZIP_COMP_CORE1, +@@ -443,7 +463,7 @@ bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg) + { + u32 cap_val; + +- cap_val = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DRV_ALG_BITMAP, qm->cap_ver); ++ cap_val = qm->cap_tables.dev_cap_table[ZIP_DRV_ALG_BITMAP_IDX].cap_val; + if ((alg & cap_val) == alg) + return true; + +@@ -568,10 +588,8 @@ static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm) + } + + /* let's open all compression/decompression cores */ +- dcomp_bm = hisi_qm_get_hw_info(qm, zip_basic_cap_info, +- ZIP_DECOMP_ENABLE_BITMAP, qm->cap_ver); +- comp_bm = hisi_qm_get_hw_info(qm, zip_basic_cap_info, +- ZIP_COMP_ENABLE_BITMAP, qm->cap_ver); ++ dcomp_bm = qm->cap_tables.dev_cap_table[ZIP_DECOMP_ENABLE_BITMAP_IDX].cap_val; ++ comp_bm = qm->cap_tables.dev_cap_table[ZIP_COMP_ENABLE_BITMAP_IDX].cap_val; + writel(HZIP_DECOMP_CHECK_ENABLE | dcomp_bm | comp_bm, base + HZIP_CLOCK_GATE_CTRL); + + /* enable sqc,cqc writeback */ +@@ -798,9 +816,8 @@ static int hisi_zip_core_debug_init(struct hisi_qm *qm) + char buf[HZIP_BUF_SIZE]; + int i; + +- zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver); +- zip_comp_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CLUSTER_COMP_NUM_CAP, +- qm->cap_ver); ++ zip_core_num = qm->cap_tables.dev_cap_table[ZIP_CORE_NUM_CAP_IDX].cap_val; ++ zip_comp_core_num = qm->cap_tables.dev_cap_table[ZIP_CLUSTER_COMP_NUM_CAP_IDX].cap_val; + + for (i = 0; i < zip_core_num; i++) { + if (i < zip_comp_core_num) +@@ -942,7 +959,7 @@ static int hisi_zip_show_last_regs_init(struct hisi_qm *qm) + u32 zip_core_num; + int i, j, idx; + +- zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver); ++ zip_core_num = qm->cap_tables.dev_cap_table[ZIP_CORE_NUM_CAP_IDX].cap_val; + + debug->last_words = kcalloc(core_dfx_regs_num * zip_core_num + com_dfx_regs_num, + sizeof(unsigned int), GFP_KERNEL); +@@ -998,9 +1015,9 @@ static void hisi_zip_show_last_dfx_regs(struct hisi_qm *qm) + hzip_com_dfx_regs[i].name, debug->last_words[i], val); + } + +- zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver); +- zip_comp_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CLUSTER_COMP_NUM_CAP, +- qm->cap_ver); ++ zip_core_num = qm->cap_tables.dev_cap_table[ZIP_CORE_NUM_CAP_IDX].cap_val; ++ zip_comp_core_num = qm->cap_tables.dev_cap_table[ZIP_CLUSTER_COMP_NUM_CAP_IDX].cap_val; ++ + for (i = 0; i < zip_core_num; i++) { + if (i < zip_comp_core_num) + scnprintf(buf, sizeof(buf), "Comp_core-%d", i); +@@ -1156,6 +1173,28 @@ static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip) + return ret; + } + ++static int zip_pre_store_cap_reg(struct hisi_qm *qm) ++{ ++ struct hisi_qm_cap_record *zip_cap; ++ struct pci_dev *pdev = qm->pdev; ++ size_t i, size; ++ ++ size = ARRAY_SIZE(zip_pre_store_caps); ++ zip_cap = devm_kzalloc(&pdev->dev, sizeof(*zip_cap) * size, GFP_KERNEL); ++ if (!zip_cap) ++ return -ENOMEM; ++ ++ for (i = 0; i < size; i++) { ++ zip_cap[i].type = zip_pre_store_caps[i]; ++ zip_cap[i].cap_val = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ++ zip_pre_store_caps[i], qm->cap_ver); ++ } ++ ++ qm->cap_tables.dev_cap_table = zip_cap; ++ ++ return 0; ++} ++ + static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) + { + u64 alg_msk; +@@ -1194,7 +1233,15 @@ static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) + return ret; + } + +- alg_msk = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DEV_ALG_BITMAP, qm->cap_ver); ++ /* Fetch and save the value of capability registers */ ++ ret = zip_pre_store_cap_reg(qm); ++ if (ret) { ++ pci_err(qm->pdev, "Failed to pre-store capability registers!\n"); ++ hisi_qm_uninit(qm); ++ return ret; ++ } ++ ++ alg_msk = qm->cap_tables.dev_cap_table[ZIP_DEV_ALG_BITMAP_IDX].cap_val; + ret = hisi_qm_set_algs(qm, alg_msk, zip_dev_algs, ARRAY_SIZE(zip_dev_algs)); + if (ret) { + pci_err(qm->pdev, "Failed to set zip algs!\n"); +-- +2.43.0 + diff --git a/queue-6.1/crypto-sa2ul-return-crypto_aead_setkey-to-transfer-t.patch b/queue-6.1/crypto-sa2ul-return-crypto_aead_setkey-to-transfer-t.patch new file mode 100644 index 00000000000..3bbf5c6252c --- /dev/null +++ b/queue-6.1/crypto-sa2ul-return-crypto_aead_setkey-to-transfer-t.patch @@ -0,0 +1,38 @@ +From a433192fa9646fe90c67c975050e4d17154fe564 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 27 Nov 2023 02:03:01 +0000 +Subject: crypto: sa2ul - Return crypto_aead_setkey to transfer the error + +From: Chen Ni + +[ Upstream commit ce852f1308ac738e61c5b2502517deea593a1554 ] + +Return crypto_aead_setkey() in order to transfer the error if +it fails. + +Fixes: d2c8ac187fc9 ("crypto: sa2ul - Add AEAD algorithm support") +Signed-off-by: Chen Ni +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/sa2ul.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/crypto/sa2ul.c b/drivers/crypto/sa2ul.c +index f4bc06c24ad8..e7efebf8127f 100644 +--- a/drivers/crypto/sa2ul.c ++++ b/drivers/crypto/sa2ul.c +@@ -1868,9 +1868,8 @@ static int sa_aead_setkey(struct crypto_aead *authenc, + crypto_aead_set_flags(ctx->fallback.aead, + crypto_aead_get_flags(authenc) & + CRYPTO_TFM_REQ_MASK); +- crypto_aead_setkey(ctx->fallback.aead, key, keylen); + +- return 0; ++ return crypto_aead_setkey(ctx->fallback.aead, key, keylen); + } + + static int sa_aead_setauthsize(struct crypto_aead *tfm, unsigned int authsize) +-- +2.43.0 + diff --git a/queue-6.1/crypto-safexcel-add-error-handling-for-dma_map_sg-ca.patch b/queue-6.1/crypto-safexcel-add-error-handling-for-dma_map_sg-ca.patch new file mode 100644 index 00000000000..dbc966c4d68 --- /dev/null +++ b/queue-6.1/crypto-safexcel-add-error-handling-for-dma_map_sg-ca.patch @@ -0,0 +1,72 @@ +From d07ff8790f876e16759ee211a11e32c63dc815b2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 1 Dec 2023 04:49:29 -0800 +Subject: crypto: safexcel - Add error handling for dma_map_sg() calls + +From: Nikita Zhandarovich + +[ Upstream commit 87e02063d07708cac5bfe9fd3a6a242898758ac8 ] + +Macro dma_map_sg() may return 0 on error. This patch enables +checks in case of the macro failure and ensures unmapping of +previously mapped buffers with dma_unmap_sg(). + +Found by Linux Verification Center (linuxtesting.org) with static +analysis tool SVACE. + +Fixes: 49186a7d9e46 ("crypto: inside_secure - Avoid dma map if size is zero") +Signed-off-by: Nikita Zhandarovich +Reviewed-by: Antoine Tenart +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + .../crypto/inside-secure/safexcel_cipher.c | 19 +++++++++++-------- + 1 file changed, 11 insertions(+), 8 deletions(-) + +diff --git a/drivers/crypto/inside-secure/safexcel_cipher.c b/drivers/crypto/inside-secure/safexcel_cipher.c +index 32a37e3850c5..f59e32115268 100644 +--- a/drivers/crypto/inside-secure/safexcel_cipher.c ++++ b/drivers/crypto/inside-secure/safexcel_cipher.c +@@ -742,9 +742,9 @@ static int safexcel_send_req(struct crypto_async_request *base, int ring, + max(totlen_src, totlen_dst)); + return -EINVAL; + } +- if (sreq->nr_src > 0) +- dma_map_sg(priv->dev, src, sreq->nr_src, +- DMA_BIDIRECTIONAL); ++ if (sreq->nr_src > 0 && ++ !dma_map_sg(priv->dev, src, sreq->nr_src, DMA_BIDIRECTIONAL)) ++ return -EIO; + } else { + if (unlikely(totlen_src && (sreq->nr_src <= 0))) { + dev_err(priv->dev, "Source buffer not large enough (need %d bytes)!", +@@ -752,8 +752,9 @@ static int safexcel_send_req(struct crypto_async_request *base, int ring, + return -EINVAL; + } + +- if (sreq->nr_src > 0) +- dma_map_sg(priv->dev, src, sreq->nr_src, DMA_TO_DEVICE); ++ if (sreq->nr_src > 0 && ++ !dma_map_sg(priv->dev, src, sreq->nr_src, DMA_TO_DEVICE)) ++ return -EIO; + + if (unlikely(totlen_dst && (sreq->nr_dst <= 0))) { + dev_err(priv->dev, "Dest buffer not large enough (need %d bytes)!", +@@ -762,9 +763,11 @@ static int safexcel_send_req(struct crypto_async_request *base, int ring, + goto unmap; + } + +- if (sreq->nr_dst > 0) +- dma_map_sg(priv->dev, dst, sreq->nr_dst, +- DMA_FROM_DEVICE); ++ if (sreq->nr_dst > 0 && ++ !dma_map_sg(priv->dev, dst, sreq->nr_dst, DMA_FROM_DEVICE)) { ++ ret = -EIO; ++ goto unmap; ++ } + } + + memcpy(ctx->base.ctxr->data, ctx->key, ctx->key_len); +-- +2.43.0 + diff --git a/queue-6.1/crypto-sahara-avoid-skcipher-fallback-code-duplicati.patch b/queue-6.1/crypto-sahara-avoid-skcipher-fallback-code-duplicati.patch new file mode 100644 index 00000000000..b884811137a --- /dev/null +++ b/queue-6.1/crypto-sahara-avoid-skcipher-fallback-code-duplicati.patch @@ -0,0 +1,148 @@ +From dc0aee8cb69b5f50382a6b09ba0aa1ee7062429e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 1 Dec 2023 19:06:25 +0200 +Subject: crypto: sahara - avoid skcipher fallback code duplication + +From: Ovidiu Panait + +[ Upstream commit 01d70a4bbff20ea05cadb4c208841985a7cc6596 ] + +Factor out duplicated skcipher fallback handling code to a helper function +sahara_aes_fallback(). Also, keep a single check if fallback is required in +sahara_aes_crypt(). + +Signed-off-by: Ovidiu Panait +Signed-off-by: Herbert Xu +Stable-dep-of: d1d6351e37aa ("crypto: sahara - handle zero-length aes requests") +Signed-off-by: Sasha Levin +--- + drivers/crypto/sahara.c | 85 ++++++++++++----------------------------- + 1 file changed, 25 insertions(+), 60 deletions(-) + +diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c +index 0b7a95dae9fe..89fd54bc0127 100644 +--- a/drivers/crypto/sahara.c ++++ b/drivers/crypto/sahara.c +@@ -649,12 +649,37 @@ static int sahara_aes_setkey(struct crypto_skcipher *tfm, const u8 *key, + return crypto_skcipher_setkey(ctx->fallback, key, keylen); + } + ++static int sahara_aes_fallback(struct skcipher_request *req, unsigned long mode) ++{ ++ struct sahara_aes_reqctx *rctx = skcipher_request_ctx(req); ++ struct sahara_ctx *ctx = crypto_skcipher_ctx( ++ crypto_skcipher_reqtfm(req)); ++ ++ skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback); ++ skcipher_request_set_callback(&rctx->fallback_req, ++ req->base.flags, ++ req->base.complete, ++ req->base.data); ++ skcipher_request_set_crypt(&rctx->fallback_req, req->src, ++ req->dst, req->cryptlen, req->iv); ++ ++ if (mode & FLAGS_ENCRYPT) ++ return crypto_skcipher_encrypt(&rctx->fallback_req); ++ ++ return crypto_skcipher_decrypt(&rctx->fallback_req); ++} ++ + static int sahara_aes_crypt(struct skcipher_request *req, unsigned long mode) + { + struct sahara_aes_reqctx *rctx = skcipher_request_ctx(req); ++ struct sahara_ctx *ctx = crypto_skcipher_ctx( ++ crypto_skcipher_reqtfm(req)); + struct sahara_dev *dev = dev_ptr; + int err = 0; + ++ if (unlikely(ctx->keylen != AES_KEYSIZE_128)) ++ return sahara_aes_fallback(req, mode); ++ + dev_dbg(dev->device, "nbytes: %d, enc: %d, cbc: %d\n", + req->cryptlen, !!(mode & FLAGS_ENCRYPT), !!(mode & FLAGS_CBC)); + +@@ -677,81 +702,21 @@ static int sahara_aes_crypt(struct skcipher_request *req, unsigned long mode) + + static int sahara_aes_ecb_encrypt(struct skcipher_request *req) + { +- struct sahara_aes_reqctx *rctx = skcipher_request_ctx(req); +- struct sahara_ctx *ctx = crypto_skcipher_ctx( +- crypto_skcipher_reqtfm(req)); +- +- if (unlikely(ctx->keylen != AES_KEYSIZE_128)) { +- skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback); +- skcipher_request_set_callback(&rctx->fallback_req, +- req->base.flags, +- req->base.complete, +- req->base.data); +- skcipher_request_set_crypt(&rctx->fallback_req, req->src, +- req->dst, req->cryptlen, req->iv); +- return crypto_skcipher_encrypt(&rctx->fallback_req); +- } +- + return sahara_aes_crypt(req, FLAGS_ENCRYPT); + } + + static int sahara_aes_ecb_decrypt(struct skcipher_request *req) + { +- struct sahara_aes_reqctx *rctx = skcipher_request_ctx(req); +- struct sahara_ctx *ctx = crypto_skcipher_ctx( +- crypto_skcipher_reqtfm(req)); +- +- if (unlikely(ctx->keylen != AES_KEYSIZE_128)) { +- skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback); +- skcipher_request_set_callback(&rctx->fallback_req, +- req->base.flags, +- req->base.complete, +- req->base.data); +- skcipher_request_set_crypt(&rctx->fallback_req, req->src, +- req->dst, req->cryptlen, req->iv); +- return crypto_skcipher_decrypt(&rctx->fallback_req); +- } +- + return sahara_aes_crypt(req, 0); + } + + static int sahara_aes_cbc_encrypt(struct skcipher_request *req) + { +- struct sahara_aes_reqctx *rctx = skcipher_request_ctx(req); +- struct sahara_ctx *ctx = crypto_skcipher_ctx( +- crypto_skcipher_reqtfm(req)); +- +- if (unlikely(ctx->keylen != AES_KEYSIZE_128)) { +- skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback); +- skcipher_request_set_callback(&rctx->fallback_req, +- req->base.flags, +- req->base.complete, +- req->base.data); +- skcipher_request_set_crypt(&rctx->fallback_req, req->src, +- req->dst, req->cryptlen, req->iv); +- return crypto_skcipher_encrypt(&rctx->fallback_req); +- } +- + return sahara_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC); + } + + static int sahara_aes_cbc_decrypt(struct skcipher_request *req) + { +- struct sahara_aes_reqctx *rctx = skcipher_request_ctx(req); +- struct sahara_ctx *ctx = crypto_skcipher_ctx( +- crypto_skcipher_reqtfm(req)); +- +- if (unlikely(ctx->keylen != AES_KEYSIZE_128)) { +- skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback); +- skcipher_request_set_callback(&rctx->fallback_req, +- req->base.flags, +- req->base.complete, +- req->base.data); +- skcipher_request_set_crypt(&rctx->fallback_req, req->src, +- req->dst, req->cryptlen, req->iv); +- return crypto_skcipher_decrypt(&rctx->fallback_req); +- } +- + return sahara_aes_crypt(req, FLAGS_CBC); + } + +-- +2.43.0 + diff --git a/queue-6.1/crypto-sahara-do-not-resize-req-src-when-doing-hash-.patch b/queue-6.1/crypto-sahara-do-not-resize-req-src-when-doing-hash-.patch new file mode 100644 index 00000000000..2ac2e1f9fb0 --- /dev/null +++ b/queue-6.1/crypto-sahara-do-not-resize-req-src-when-doing-hash-.patch @@ -0,0 +1,99 @@ +From bce2755fb6a4a5e8d2299cbbda3a898ffd05797b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 24 Dec 2023 10:21:36 +0200 +Subject: crypto: sahara - do not resize req->src when doing hash operations + +From: Ovidiu Panait + +[ Upstream commit a3c6f4f4d249cecaf2f34471aadbfb4f4ef57298 ] + +When testing sahara sha256 speed performance with tcrypt (mode=404) on +imx53-qsrb board, multiple "Invalid numbers of src SG." errors are +reported. This was traced to sahara_walk_and_recalc() resizing req->src +and causing the subsequent dma_map_sg() call to fail. + +Now that the previous commit fixed sahara_sha_hw_links_create() to take +into account the actual request size, rather than relying on sg->length +values, the resize operation is no longer necessary. + +Therefore, remove sahara_walk_and_recalc() and simplify associated logic. + +Fixes: 5a2bb93f5992 ("crypto: sahara - add support for SHA1/256") +Signed-off-by: Ovidiu Panait +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/sahara.c | 38 ++------------------------------------ + 1 file changed, 2 insertions(+), 36 deletions(-) + +diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c +index b167f92279ad..3b946f1313ed 100644 +--- a/drivers/crypto/sahara.c ++++ b/drivers/crypto/sahara.c +@@ -887,24 +887,6 @@ static int sahara_sha_hw_context_descriptor_create(struct sahara_dev *dev, + return 0; + } + +-static int sahara_walk_and_recalc(struct scatterlist *sg, unsigned int nbytes) +-{ +- if (!sg || !sg->length) +- return nbytes; +- +- while (nbytes && sg) { +- if (nbytes <= sg->length) { +- sg->length = nbytes; +- sg_mark_end(sg); +- break; +- } +- nbytes -= sg->length; +- sg = sg_next(sg); +- } +- +- return nbytes; +-} +- + static int sahara_sha_prepare_request(struct ahash_request *req) + { + struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); +@@ -941,36 +923,20 @@ static int sahara_sha_prepare_request(struct ahash_request *req) + hash_later, 0); + } + +- /* nbytes should now be multiple of blocksize */ +- req->nbytes = req->nbytes - hash_later; +- +- sahara_walk_and_recalc(req->src, req->nbytes); +- ++ rctx->total = len - hash_later; + /* have data from previous operation and current */ + if (rctx->buf_cnt && req->nbytes) { + sg_init_table(rctx->in_sg_chain, 2); + sg_set_buf(rctx->in_sg_chain, rctx->rembuf, rctx->buf_cnt); +- + sg_chain(rctx->in_sg_chain, 2, req->src); +- +- rctx->total = req->nbytes + rctx->buf_cnt; + rctx->in_sg = rctx->in_sg_chain; +- +- req->src = rctx->in_sg_chain; + /* only data from previous operation */ + } else if (rctx->buf_cnt) { +- if (req->src) +- rctx->in_sg = req->src; +- else +- rctx->in_sg = rctx->in_sg_chain; +- /* buf was copied into rembuf above */ ++ rctx->in_sg = rctx->in_sg_chain; + sg_init_one(rctx->in_sg, rctx->rembuf, rctx->buf_cnt); +- rctx->total = rctx->buf_cnt; + /* no data from previous operation */ + } else { + rctx->in_sg = req->src; +- rctx->total = req->nbytes; +- req->src = rctx->in_sg; + } + + /* on next call, we only have the remaining data in the buffer */ +-- +2.43.0 + diff --git a/queue-6.1/crypto-sahara-fix-ahash-reqsize.patch b/queue-6.1/crypto-sahara-fix-ahash-reqsize.patch new file mode 100644 index 00000000000..0f474c9982e --- /dev/null +++ b/queue-6.1/crypto-sahara-fix-ahash-reqsize.patch @@ -0,0 +1,37 @@ +From 077211a9bfd77abf7230a08f00ca8e17078f979e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 24 Dec 2023 10:21:32 +0200 +Subject: crypto: sahara - fix ahash reqsize + +From: Ovidiu Panait + +[ Upstream commit efcb50f41740ac55e6ccc4986c1a7740e21c62b4 ] + +Set the reqsize for sha algorithms to sizeof(struct sahara_sha_reqctx), the +extra space is not needed. + +Fixes: 5a2bb93f5992 ("crypto: sahara - add support for SHA1/256") +Signed-off-by: Ovidiu Panait +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/sahara.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c +index 4b32e96e197d..6e87b108df19 100644 +--- a/drivers/crypto/sahara.c ++++ b/drivers/crypto/sahara.c +@@ -1163,8 +1163,7 @@ static int sahara_sha_import(struct ahash_request *req, const void *in) + static int sahara_sha_cra_init(struct crypto_tfm *tfm) + { + crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), +- sizeof(struct sahara_sha_reqctx) + +- SHA_BUFFER_LEN + SHA256_BLOCK_SIZE); ++ sizeof(struct sahara_sha_reqctx)); + + return 0; + } +-- +2.43.0 + diff --git a/queue-6.1/crypto-sahara-fix-ahash-selftest-failure.patch b/queue-6.1/crypto-sahara-fix-ahash-selftest-failure.patch new file mode 100644 index 00000000000..b6f17160061 --- /dev/null +++ b/queue-6.1/crypto-sahara-fix-ahash-selftest-failure.patch @@ -0,0 +1,41 @@ +From 475d73baa7d875fa63b9eaa4de05880953dce03d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 1 Dec 2023 19:06:21 +0200 +Subject: crypto: sahara - fix ahash selftest failure + +From: Ovidiu Panait + +[ Upstream commit afffcf3db98b9495114b79d5381f8cc3f69476fb ] + +update() calls should not modify the result buffer, so add an additional +check for "rctx->last" to make sure that only the final hash value is +copied into the buffer. + +Fixes the following selftest failure: +alg: ahash: sahara-sha256 update() used result buffer on test vector 3, +cfg="init+update+final aligned buffer" + +Fixes: 5a2bb93f5992 ("crypto: sahara - add support for SHA1/256") +Signed-off-by: Ovidiu Panait +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/sahara.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c +index aa9c45ff0f5a..5e0b26f36319 100644 +--- a/drivers/crypto/sahara.c ++++ b/drivers/crypto/sahara.c +@@ -1048,7 +1048,7 @@ static int sahara_sha_process(struct ahash_request *req) + + memcpy(rctx->context, dev->context_base, rctx->context_size); + +- if (req->result) ++ if (req->result && rctx->last) + memcpy(req->result, rctx->context, rctx->digest_size); + + return 0; +-- +2.43.0 + diff --git a/queue-6.1/crypto-sahara-fix-cbc-selftest-failure.patch b/queue-6.1/crypto-sahara-fix-cbc-selftest-failure.patch new file mode 100644 index 00000000000..b1a41463253 --- /dev/null +++ b/queue-6.1/crypto-sahara-fix-cbc-selftest-failure.patch @@ -0,0 +1,94 @@ +From 36ba6de5590333fbba7c5b30bf1c467eb25df0cc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 1 Dec 2023 19:06:20 +0200 +Subject: crypto: sahara - fix cbc selftest failure + +From: Ovidiu Panait + +[ Upstream commit 9f10bc28c0fb676ae58aa3bfa358db8f5de124bb ] + +The kernel crypto API requires that all CBC implementations update the IV +buffer to contain the last ciphertext block. + +This fixes the following cbc selftest error: +alg: skcipher: sahara-cbc-aes encryption test failed (wrong output IV) on +test vector 0, cfg="in-place (one sglist)" + +Fixes: 5de8875281e1 ("crypto: sahara - Add driver for SAHARA2 accelerator.") +Signed-off-by: Ovidiu Panait +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/sahara.c | 33 +++++++++++++++++++++++++++++++-- + 1 file changed, 31 insertions(+), 2 deletions(-) + +diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c +index 0e30d36b0a71..aa9c45ff0f5a 100644 +--- a/drivers/crypto/sahara.c ++++ b/drivers/crypto/sahara.c +@@ -149,6 +149,7 @@ struct sahara_ctx { + + struct sahara_aes_reqctx { + unsigned long mode; ++ u8 iv_out[AES_BLOCK_SIZE]; + struct skcipher_request fallback_req; // keep at the end + }; + +@@ -542,8 +543,24 @@ static int sahara_hw_descriptor_create(struct sahara_dev *dev) + return -EINVAL; + } + ++static void sahara_aes_cbc_update_iv(struct skcipher_request *req) ++{ ++ struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req); ++ struct sahara_aes_reqctx *rctx = skcipher_request_ctx(req); ++ unsigned int ivsize = crypto_skcipher_ivsize(skcipher); ++ ++ /* Update IV buffer to contain the last ciphertext block */ ++ if (rctx->mode & FLAGS_ENCRYPT) { ++ sg_pcopy_to_buffer(req->dst, sg_nents(req->dst), req->iv, ++ ivsize, req->cryptlen - ivsize); ++ } else { ++ memcpy(req->iv, rctx->iv_out, ivsize); ++ } ++} ++ + static int sahara_aes_process(struct skcipher_request *req) + { ++ struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req); + struct sahara_dev *dev = dev_ptr; + struct sahara_ctx *ctx; + struct sahara_aes_reqctx *rctx; +@@ -565,8 +582,17 @@ static int sahara_aes_process(struct skcipher_request *req) + rctx->mode &= FLAGS_MODE_MASK; + dev->flags = (dev->flags & ~FLAGS_MODE_MASK) | rctx->mode; + +- if ((dev->flags & FLAGS_CBC) && req->iv) +- memcpy(dev->iv_base, req->iv, AES_KEYSIZE_128); ++ if ((dev->flags & FLAGS_CBC) && req->iv) { ++ unsigned int ivsize = crypto_skcipher_ivsize(skcipher); ++ ++ memcpy(dev->iv_base, req->iv, ivsize); ++ ++ if (!(dev->flags & FLAGS_ENCRYPT)) { ++ sg_pcopy_to_buffer(req->src, sg_nents(req->src), ++ rctx->iv_out, ivsize, ++ req->cryptlen - ivsize); ++ } ++ } + + /* assign new context to device */ + dev->ctx = ctx; +@@ -589,6 +615,9 @@ static int sahara_aes_process(struct skcipher_request *req) + dma_unmap_sg(dev->device, dev->in_sg, dev->nb_in_sg, + DMA_TO_DEVICE); + ++ if ((dev->flags & FLAGS_CBC) && req->iv) ++ sahara_aes_cbc_update_iv(req); ++ + return 0; + } + +-- +2.43.0 + diff --git a/queue-6.1/crypto-sahara-fix-error-handling-in-sahara_hw_descri.patch b/queue-6.1/crypto-sahara-fix-error-handling-in-sahara_hw_descri.patch new file mode 100644 index 00000000000..cf8dd0b94bd --- /dev/null +++ b/queue-6.1/crypto-sahara-fix-error-handling-in-sahara_hw_descri.patch @@ -0,0 +1,54 @@ +From fb7419092234efa617d37da49f1d6286ce6b4688 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 1 Dec 2023 19:06:23 +0200 +Subject: crypto: sahara - fix error handling in sahara_hw_descriptor_create() + +From: Ovidiu Panait + +[ Upstream commit ee6e6f0a7f5b39d50a5ef5fcc006f4f693db18a7 ] + +Do not call dma_unmap_sg() for scatterlists that were not mapped +successfully. + +Fixes: 5de8875281e1 ("crypto: sahara - Add driver for SAHARA2 accelerator.") +Signed-off-by: Ovidiu Panait +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/sahara.c | 8 +++----- + 1 file changed, 3 insertions(+), 5 deletions(-) + +diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c +index e25636904aca..0b7a95dae9fe 100644 +--- a/drivers/crypto/sahara.c ++++ b/drivers/crypto/sahara.c +@@ -484,13 +484,14 @@ static int sahara_hw_descriptor_create(struct sahara_dev *dev) + DMA_TO_DEVICE); + if (!ret) { + dev_err(dev->device, "couldn't map in sg\n"); +- goto unmap_in; ++ return -EINVAL; + } ++ + ret = dma_map_sg(dev->device, dev->out_sg, dev->nb_out_sg, + DMA_FROM_DEVICE); + if (!ret) { + dev_err(dev->device, "couldn't map out sg\n"); +- goto unmap_out; ++ goto unmap_in; + } + + /* Create input links */ +@@ -538,9 +539,6 @@ static int sahara_hw_descriptor_create(struct sahara_dev *dev) + + return 0; + +-unmap_out: +- dma_unmap_sg(dev->device, dev->out_sg, dev->nb_out_sg, +- DMA_FROM_DEVICE); + unmap_in: + dma_unmap_sg(dev->device, dev->in_sg, dev->nb_in_sg, + DMA_TO_DEVICE); +-- +2.43.0 + diff --git a/queue-6.1/crypto-sahara-fix-processing-hash-requests-with-req-.patch b/queue-6.1/crypto-sahara-fix-processing-hash-requests-with-req-.patch new file mode 100644 index 00000000000..90d59a54843 --- /dev/null +++ b/queue-6.1/crypto-sahara-fix-processing-hash-requests-with-req-.patch @@ -0,0 +1,56 @@ +From e481f550d2826f36b26dd332c2fc75e7ef3fc567 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 24 Dec 2023 10:21:35 +0200 +Subject: crypto: sahara - fix processing hash requests with req->nbytes < + sg->length + +From: Ovidiu Panait + +[ Upstream commit 7bafa74d1ba35dcc173e1ce915e983d65905f77e ] + +It's not always the case that the entire sg entry needs to be processed. +Currently, when nbytes is less than sg->length, "Descriptor length" errors +are encountered. + +To fix this, take the actual request size into account when populating the +hw links. + +Fixes: 5a2bb93f5992 ("crypto: sahara - add support for SHA1/256") +Signed-off-by: Ovidiu Panait +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/sahara.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c +index 6e112e41a0c7..b167f92279ad 100644 +--- a/drivers/crypto/sahara.c ++++ b/drivers/crypto/sahara.c +@@ -777,6 +777,7 @@ static int sahara_sha_hw_links_create(struct sahara_dev *dev, + int start) + { + struct scatterlist *sg; ++ unsigned int len; + unsigned int i; + int ret; + +@@ -798,12 +799,14 @@ static int sahara_sha_hw_links_create(struct sahara_dev *dev, + if (!ret) + return -EFAULT; + ++ len = rctx->total; + for (i = start; i < dev->nb_in_sg + start; i++) { +- dev->hw_link[i]->len = sg->length; ++ dev->hw_link[i]->len = min(len, sg->length); + dev->hw_link[i]->p = sg->dma_address; + if (i == (dev->nb_in_sg + start - 1)) { + dev->hw_link[i]->next = 0; + } else { ++ len -= min(len, sg->length); + dev->hw_link[i]->next = dev->hw_phys_link[i + 1]; + sg = sg_next(sg); + } +-- +2.43.0 + diff --git a/queue-6.1/crypto-sahara-fix-processing-requests-with-cryptlen-.patch b/queue-6.1/crypto-sahara-fix-processing-requests-with-cryptlen-.patch new file mode 100644 index 00000000000..91c1e2a34e3 --- /dev/null +++ b/queue-6.1/crypto-sahara-fix-processing-requests-with-cryptlen-.patch @@ -0,0 +1,72 @@ +From 65ec03228c2877d9d871926acb183f56868774dd Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 1 Dec 2023 19:06:22 +0200 +Subject: crypto: sahara - fix processing requests with cryptlen < sg->length + +From: Ovidiu Panait + +[ Upstream commit 5b8668ce3452827d27f8c34ff6ba080a8f983ed0 ] + +It's not always the case that the entire sg entry needs to be processed. +Currently, when cryptlen is less than sg->legth, "Descriptor length" errors +are encountered. + +The error was noticed when testing xts(sahara-ecb-aes) with arbitrary sized +input data. To fix this, take the actual request size into account when +populating the hw links. + +Fixes: 5de8875281e1 ("crypto: sahara - Add driver for SAHARA2 accelerator.") +Signed-off-by: Ovidiu Panait +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/sahara.c | 9 +++++++-- + 1 file changed, 7 insertions(+), 2 deletions(-) + +diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c +index 5e0b26f36319..e25636904aca 100644 +--- a/drivers/crypto/sahara.c ++++ b/drivers/crypto/sahara.c +@@ -445,6 +445,7 @@ static int sahara_hw_descriptor_create(struct sahara_dev *dev) + int ret; + int i, j; + int idx = 0; ++ u32 len; + + memcpy(dev->key_base, ctx->key, ctx->keylen); + +@@ -495,12 +496,14 @@ static int sahara_hw_descriptor_create(struct sahara_dev *dev) + /* Create input links */ + dev->hw_desc[idx]->p1 = dev->hw_phys_link[0]; + sg = dev->in_sg; ++ len = dev->total; + for (i = 0; i < dev->nb_in_sg; i++) { +- dev->hw_link[i]->len = sg->length; ++ dev->hw_link[i]->len = min(len, sg->length); + dev->hw_link[i]->p = sg->dma_address; + if (i == (dev->nb_in_sg - 1)) { + dev->hw_link[i]->next = 0; + } else { ++ len -= min(len, sg->length); + dev->hw_link[i]->next = dev->hw_phys_link[i + 1]; + sg = sg_next(sg); + } +@@ -509,12 +512,14 @@ static int sahara_hw_descriptor_create(struct sahara_dev *dev) + /* Create output links */ + dev->hw_desc[idx]->p2 = dev->hw_phys_link[i]; + sg = dev->out_sg; ++ len = dev->total; + for (j = i; j < dev->nb_out_sg + i; j++) { +- dev->hw_link[j]->len = sg->length; ++ dev->hw_link[j]->len = min(len, sg->length); + dev->hw_link[j]->p = sg->dma_address; + if (j == (dev->nb_out_sg + i - 1)) { + dev->hw_link[j]->next = 0; + } else { ++ len -= min(len, sg->length); + dev->hw_link[j]->next = dev->hw_phys_link[j + 1]; + sg = sg_next(sg); + } +-- +2.43.0 + diff --git a/queue-6.1/crypto-sahara-fix-wait_for_completion_timeout-error-.patch b/queue-6.1/crypto-sahara-fix-wait_for_completion_timeout-error-.patch new file mode 100644 index 00000000000..b99de0ab0e9 --- /dev/null +++ b/queue-6.1/crypto-sahara-fix-wait_for_completion_timeout-error-.patch @@ -0,0 +1,70 @@ +From 5696c990f31feb1f6e73132014ad887f2bee4a8f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 24 Dec 2023 10:21:33 +0200 +Subject: crypto: sahara - fix wait_for_completion_timeout() error handling + +From: Ovidiu Panait + +[ Upstream commit 2dba8e1d1a7957dcbe7888846268538847b471d1 ] + +The sg lists are not unmapped in case of timeout errors. Fix this. + +Fixes: 5a2bb93f5992 ("crypto: sahara - add support for SHA1/256") +Fixes: 5de8875281e1 ("crypto: sahara - Add driver for SAHARA2 accelerator.") +Signed-off-by: Ovidiu Panait +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/sahara.c | 18 ++++++++++-------- + 1 file changed, 10 insertions(+), 8 deletions(-) + +diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c +index 6e87b108df19..e2b1880ddeb0 100644 +--- a/drivers/crypto/sahara.c ++++ b/drivers/crypto/sahara.c +@@ -608,16 +608,17 @@ static int sahara_aes_process(struct skcipher_request *req) + + timeout = wait_for_completion_timeout(&dev->dma_completion, + msecs_to_jiffies(SAHARA_TIMEOUT_MS)); +- if (!timeout) { +- dev_err(dev->device, "AES timeout\n"); +- return -ETIMEDOUT; +- } + + dma_unmap_sg(dev->device, dev->out_sg, dev->nb_out_sg, + DMA_FROM_DEVICE); + dma_unmap_sg(dev->device, dev->in_sg, dev->nb_in_sg, + DMA_TO_DEVICE); + ++ if (!timeout) { ++ dev_err(dev->device, "AES timeout\n"); ++ return -ETIMEDOUT; ++ } ++ + if ((dev->flags & FLAGS_CBC) && req->iv) + sahara_aes_cbc_update_iv(req); + +@@ -1008,15 +1009,16 @@ static int sahara_sha_process(struct ahash_request *req) + + timeout = wait_for_completion_timeout(&dev->dma_completion, + msecs_to_jiffies(SAHARA_TIMEOUT_MS)); +- if (!timeout) { +- dev_err(dev->device, "SHA timeout\n"); +- return -ETIMEDOUT; +- } + + if (rctx->sg_in_idx) + dma_unmap_sg(dev->device, dev->in_sg, dev->nb_in_sg, + DMA_TO_DEVICE); + ++ if (!timeout) { ++ dev_err(dev->device, "SHA timeout\n"); ++ return -ETIMEDOUT; ++ } ++ + memcpy(rctx->context, dev->context_base, rctx->context_size); + + if (req->result && rctx->last) +-- +2.43.0 + diff --git a/queue-6.1/crypto-sahara-handle-zero-length-aes-requests.patch b/queue-6.1/crypto-sahara-handle-zero-length-aes-requests.patch new file mode 100644 index 00000000000..b8a45873c37 --- /dev/null +++ b/queue-6.1/crypto-sahara-handle-zero-length-aes-requests.patch @@ -0,0 +1,36 @@ +From fe7b484bf446888c7903c892d6cb7690a48cdda3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 24 Dec 2023 10:21:31 +0200 +Subject: crypto: sahara - handle zero-length aes requests + +From: Ovidiu Panait + +[ Upstream commit d1d6351e37aac14b32a291731d0855996c459d11 ] + +In case of a zero-length input, exit gracefully from sahara_aes_crypt(). + +Fixes: 5de8875281e1 ("crypto: sahara - Add driver for SAHARA2 accelerator.") +Signed-off-by: Ovidiu Panait +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/sahara.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c +index 89fd54bc0127..4b32e96e197d 100644 +--- a/drivers/crypto/sahara.c ++++ b/drivers/crypto/sahara.c +@@ -677,6 +677,9 @@ static int sahara_aes_crypt(struct skcipher_request *req, unsigned long mode) + struct sahara_dev *dev = dev_ptr; + int err = 0; + ++ if (!req->cryptlen) ++ return 0; ++ + if (unlikely(ctx->keylen != AES_KEYSIZE_128)) + return sahara_aes_fallback(req, mode); + +-- +2.43.0 + diff --git a/queue-6.1/crypto-sahara-improve-error-handling-in-sahara_sha_p.patch b/queue-6.1/crypto-sahara-improve-error-handling-in-sahara_sha_p.patch new file mode 100644 index 00000000000..5e878b4bd17 --- /dev/null +++ b/queue-6.1/crypto-sahara-improve-error-handling-in-sahara_sha_p.patch @@ -0,0 +1,51 @@ +From 75288188aa1257c9dcaf4720faf471d2a5aea166 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 24 Dec 2023 10:21:34 +0200 +Subject: crypto: sahara - improve error handling in sahara_sha_process() + +From: Ovidiu Panait + +[ Upstream commit 5deff027fca49a1eb3b20359333cf2ae562a2343 ] + +sahara_sha_hw_data_descriptor_create() returns negative error codes on +failure, so make sure the errors are correctly handled / propagated. + +Fixes: 5a2bb93f5992 ("crypto: sahara - add support for SHA1/256") +Signed-off-by: Ovidiu Panait +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/sahara.c | 10 ++++++++-- + 1 file changed, 8 insertions(+), 2 deletions(-) + +diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c +index e2b1880ddeb0..6e112e41a0c7 100644 +--- a/drivers/crypto/sahara.c ++++ b/drivers/crypto/sahara.c +@@ -988,7 +988,10 @@ static int sahara_sha_process(struct ahash_request *req) + return ret; + + if (rctx->first) { +- sahara_sha_hw_data_descriptor_create(dev, rctx, req, 0); ++ ret = sahara_sha_hw_data_descriptor_create(dev, rctx, req, 0); ++ if (ret) ++ return ret; ++ + dev->hw_desc[0]->next = 0; + rctx->first = 0; + } else { +@@ -996,7 +999,10 @@ static int sahara_sha_process(struct ahash_request *req) + + sahara_sha_hw_context_descriptor_create(dev, rctx, req, 0); + dev->hw_desc[0]->next = dev->hw_phys_desc[1]; +- sahara_sha_hw_data_descriptor_create(dev, rctx, req, 1); ++ ret = sahara_sha_hw_data_descriptor_create(dev, rctx, req, 1); ++ if (ret) ++ return ret; ++ + dev->hw_desc[1]->next = 0; + } + +-- +2.43.0 + diff --git a/queue-6.1/crypto-sahara-remove-flags_new_key-logic.patch b/queue-6.1/crypto-sahara-remove-flags_new_key-logic.patch new file mode 100644 index 00000000000..a17920c9f79 --- /dev/null +++ b/queue-6.1/crypto-sahara-remove-flags_new_key-logic.patch @@ -0,0 +1,105 @@ +From 354c834abc858a5cad05caa5ce7f9e5e4cd58b7b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 1 Dec 2023 19:06:19 +0200 +Subject: crypto: sahara - remove FLAGS_NEW_KEY logic + +From: Ovidiu Panait + +[ Upstream commit 8fd183435728b139248a77978ea3732039341779 ] + +Remove the FLAGS_NEW_KEY logic as it has the following issues: +- the wrong key may end up being used when there are multiple data streams: + t1 t2 + setkey() + encrypt() + setkey() + encrypt() + + encrypt() <--- key from t2 is used +- switching between encryption and decryption with the same key is not + possible, as the hdr flags are only updated when a new setkey() is + performed + +With this change, the key is always sent along with the cryptdata when +performing encryption/decryption operations. + +Fixes: 5de8875281e1 ("crypto: sahara - Add driver for SAHARA2 accelerator.") +Signed-off-by: Ovidiu Panait +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/sahara.c | 34 +++++++++++++--------------------- + 1 file changed, 13 insertions(+), 21 deletions(-) + +diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c +index 7ab20fb95166..0e30d36b0a71 100644 +--- a/drivers/crypto/sahara.c ++++ b/drivers/crypto/sahara.c +@@ -44,7 +44,6 @@ + #define FLAGS_MODE_MASK 0x000f + #define FLAGS_ENCRYPT BIT(0) + #define FLAGS_CBC BIT(1) +-#define FLAGS_NEW_KEY BIT(3) + + #define SAHARA_HDR_BASE 0x00800000 + #define SAHARA_HDR_SKHA_ALG_AES 0 +@@ -142,8 +141,6 @@ struct sahara_hw_link { + }; + + struct sahara_ctx { +- unsigned long flags; +- + /* AES-specific context */ + int keylen; + u8 key[AES_KEYSIZE_128]; +@@ -448,26 +445,22 @@ static int sahara_hw_descriptor_create(struct sahara_dev *dev) + int i, j; + int idx = 0; + +- /* Copy new key if necessary */ +- if (ctx->flags & FLAGS_NEW_KEY) { +- memcpy(dev->key_base, ctx->key, ctx->keylen); +- ctx->flags &= ~FLAGS_NEW_KEY; ++ memcpy(dev->key_base, ctx->key, ctx->keylen); + +- if (dev->flags & FLAGS_CBC) { +- dev->hw_desc[idx]->len1 = AES_BLOCK_SIZE; +- dev->hw_desc[idx]->p1 = dev->iv_phys_base; +- } else { +- dev->hw_desc[idx]->len1 = 0; +- dev->hw_desc[idx]->p1 = 0; +- } +- dev->hw_desc[idx]->len2 = ctx->keylen; +- dev->hw_desc[idx]->p2 = dev->key_phys_base; +- dev->hw_desc[idx]->next = dev->hw_phys_desc[1]; ++ if (dev->flags & FLAGS_CBC) { ++ dev->hw_desc[idx]->len1 = AES_BLOCK_SIZE; ++ dev->hw_desc[idx]->p1 = dev->iv_phys_base; ++ } else { ++ dev->hw_desc[idx]->len1 = 0; ++ dev->hw_desc[idx]->p1 = 0; ++ } ++ dev->hw_desc[idx]->len2 = ctx->keylen; ++ dev->hw_desc[idx]->p2 = dev->key_phys_base; ++ dev->hw_desc[idx]->next = dev->hw_phys_desc[1]; ++ dev->hw_desc[idx]->hdr = sahara_aes_key_hdr(dev); + +- dev->hw_desc[idx]->hdr = sahara_aes_key_hdr(dev); ++ idx++; + +- idx++; +- } + + dev->nb_in_sg = sg_nents_for_len(dev->in_sg, dev->total); + if (dev->nb_in_sg < 0) { +@@ -609,7 +602,6 @@ static int sahara_aes_setkey(struct crypto_skcipher *tfm, const u8 *key, + /* SAHARA only supports 128bit keys */ + if (keylen == AES_KEYSIZE_128) { + memcpy(ctx->key, key, keylen); +- ctx->flags |= FLAGS_NEW_KEY; + return 0; + } + +-- +2.43.0 + diff --git a/queue-6.1/crypto-scomp-fix-req-dst-buffer-overflow.patch b/queue-6.1/crypto-scomp-fix-req-dst-buffer-overflow.patch new file mode 100644 index 00000000000..0c698540ebe --- /dev/null +++ b/queue-6.1/crypto-scomp-fix-req-dst-buffer-overflow.patch @@ -0,0 +1,57 @@ +From 0f2ce02526b73cdcde52cf13f5b2e9fbc77aa7f1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 27 Dec 2023 09:35:23 +0000 +Subject: crypto: scomp - fix req->dst buffer overflow + +From: Chengming Zhou + +[ Upstream commit 744e1885922a9943458954cfea917b31064b4131 ] + +The req->dst buffer size should be checked before copying from the +scomp_scratch->dst to avoid req->dst buffer overflow problem. + +Fixes: 1ab53a77b772 ("crypto: acomp - add driver-side scomp interface") +Reported-by: syzbot+3eff5e51bf1db122a16e@syzkaller.appspotmail.com +Closes: https://lore.kernel.org/all/0000000000000b05cd060d6b5511@google.com/ +Signed-off-by: Chengming Zhou +Reviewed-by: Barry Song +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + crypto/scompress.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/crypto/scompress.c b/crypto/scompress.c +index 738f4f8f0f41..4d6366a44400 100644 +--- a/crypto/scompress.c ++++ b/crypto/scompress.c +@@ -124,6 +124,7 @@ static int scomp_acomp_comp_decomp(struct acomp_req *req, int dir) + struct crypto_scomp *scomp = *tfm_ctx; + void **ctx = acomp_request_ctx(req); + struct scomp_scratch *scratch; ++ unsigned int dlen; + int ret; + + if (!req->src || !req->slen || req->slen > SCOMP_SCRATCH_SIZE) +@@ -135,6 +136,8 @@ static int scomp_acomp_comp_decomp(struct acomp_req *req, int dir) + if (!req->dlen || req->dlen > SCOMP_SCRATCH_SIZE) + req->dlen = SCOMP_SCRATCH_SIZE; + ++ dlen = req->dlen; ++ + scratch = raw_cpu_ptr(&scomp_scratch); + spin_lock(&scratch->lock); + +@@ -152,6 +155,9 @@ static int scomp_acomp_comp_decomp(struct acomp_req *req, int dir) + ret = -ENOMEM; + goto out; + } ++ } else if (req->dlen > dlen) { ++ ret = -ENOSPC; ++ goto out; + } + scatterwalk_map_and_copy(scratch->dst, req->dst, 0, req->dlen, + 1); +-- +2.43.0 + diff --git a/queue-6.1/crypto-virtio-handle-dataq-logic-with-tasklet.patch b/queue-6.1/crypto-virtio-handle-dataq-logic-with-tasklet.patch new file mode 100644 index 00000000000..762db4b7444 --- /dev/null +++ b/queue-6.1/crypto-virtio-handle-dataq-logic-with-tasklet.patch @@ -0,0 +1,99 @@ +From 747ea701398a8c8156ca5ff2daf4fe815214095f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 20 Nov 2023 11:49:45 +0000 +Subject: crypto: virtio - Handle dataq logic with tasklet + +From: Gonglei (Arei) + +[ Upstream commit fed93fb62e05c38152b0fc1dc9609639e63eed76 ] + +Doing ipsec produces a spinlock recursion warning. +This is due to crypto_finalize_request() being called in the upper half. +Move virtual data queue processing of virtio-crypto driver to tasklet. + +Fixes: dbaf0624ffa57 ("crypto: add virtio-crypto driver") +Reported-by: Halil Pasic +Signed-off-by: wangyangxin +Signed-off-by: Gonglei +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/virtio/virtio_crypto_common.h | 2 ++ + drivers/crypto/virtio/virtio_crypto_core.c | 23 +++++++++++--------- + 2 files changed, 15 insertions(+), 10 deletions(-) + +diff --git a/drivers/crypto/virtio/virtio_crypto_common.h b/drivers/crypto/virtio/virtio_crypto_common.h +index 154590e1f764..7059bbe5a2eb 100644 +--- a/drivers/crypto/virtio/virtio_crypto_common.h ++++ b/drivers/crypto/virtio/virtio_crypto_common.h +@@ -10,6 +10,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -28,6 +29,7 @@ struct data_queue { + char name[32]; + + struct crypto_engine *engine; ++ struct tasklet_struct done_task; + }; + + struct virtio_crypto { +diff --git a/drivers/crypto/virtio/virtio_crypto_core.c b/drivers/crypto/virtio/virtio_crypto_core.c +index 3842915ea743..856daf05341c 100644 +--- a/drivers/crypto/virtio/virtio_crypto_core.c ++++ b/drivers/crypto/virtio/virtio_crypto_core.c +@@ -72,27 +72,28 @@ int virtio_crypto_ctrl_vq_request(struct virtio_crypto *vcrypto, struct scatterl + return 0; + } + +-static void virtcrypto_dataq_callback(struct virtqueue *vq) ++static void virtcrypto_done_task(unsigned long data) + { +- struct virtio_crypto *vcrypto = vq->vdev->priv; ++ struct data_queue *data_vq = (struct data_queue *)data; ++ struct virtqueue *vq = data_vq->vq; + struct virtio_crypto_request *vc_req; +- unsigned long flags; + unsigned int len; +- unsigned int qid = vq->index; + +- spin_lock_irqsave(&vcrypto->data_vq[qid].lock, flags); + do { + virtqueue_disable_cb(vq); + while ((vc_req = virtqueue_get_buf(vq, &len)) != NULL) { +- spin_unlock_irqrestore( +- &vcrypto->data_vq[qid].lock, flags); + if (vc_req->alg_cb) + vc_req->alg_cb(vc_req, len); +- spin_lock_irqsave( +- &vcrypto->data_vq[qid].lock, flags); + } + } while (!virtqueue_enable_cb(vq)); +- spin_unlock_irqrestore(&vcrypto->data_vq[qid].lock, flags); ++} ++ ++static void virtcrypto_dataq_callback(struct virtqueue *vq) ++{ ++ struct virtio_crypto *vcrypto = vq->vdev->priv; ++ struct data_queue *dq = &vcrypto->data_vq[vq->index]; ++ ++ tasklet_schedule(&dq->done_task); + } + + static int virtcrypto_find_vqs(struct virtio_crypto *vi) +@@ -150,6 +151,8 @@ static int virtcrypto_find_vqs(struct virtio_crypto *vi) + ret = -ENOMEM; + goto err_engine; + } ++ tasklet_init(&vi->data_vq[i].done_task, virtcrypto_done_task, ++ (unsigned long)&vi->data_vq[i]); + } + + kfree(names); +-- +2.43.0 + diff --git a/queue-6.1/crypto-virtio-wait-for-tasklet-to-complete-on-device.patch b/queue-6.1/crypto-virtio-wait-for-tasklet-to-complete-on-device.patch new file mode 100644 index 00000000000..e130f9d2efc --- /dev/null +++ b/queue-6.1/crypto-virtio-wait-for-tasklet-to-complete-on-device.patch @@ -0,0 +1,43 @@ +From 6d50aa1a3b484539ef73e34ee001a8723e8dccc5 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 11 Dec 2023 19:42:15 +0800 +Subject: crypto: virtio - Wait for tasklet to complete on device remove + +From: wangyangxin + +[ Upstream commit 67cc511e8d436456cc98033e6d4ba83ebfc8e672 ] + +The scheduled tasklet needs to be executed on device remove. + +Fixes: fed93fb62e05 ("crypto: virtio - Handle dataq logic with tasklet") +Signed-off-by: wangyangxin +Signed-off-by: Gonglei +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/virtio/virtio_crypto_core.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/crypto/virtio/virtio_crypto_core.c b/drivers/crypto/virtio/virtio_crypto_core.c +index 856daf05341c..56dc0935c774 100644 +--- a/drivers/crypto/virtio/virtio_crypto_core.c ++++ b/drivers/crypto/virtio/virtio_crypto_core.c +@@ -499,12 +499,15 @@ static void virtcrypto_free_unused_reqs(struct virtio_crypto *vcrypto) + static void virtcrypto_remove(struct virtio_device *vdev) + { + struct virtio_crypto *vcrypto = vdev->priv; ++ int i; + + dev_info(&vdev->dev, "Start virtcrypto_remove.\n"); + + flush_work(&vcrypto->config_work); + if (virtcrypto_dev_started(vcrypto)) + virtcrypto_dev_stop(vcrypto); ++ for (i = 0; i < vcrypto->max_data_queues; i++) ++ tasklet_kill(&vcrypto->data_vq[i].done_task); + virtio_reset_device(vdev); + virtcrypto_free_unused_reqs(vcrypto); + virtcrypto_clear_crypto_engines(vcrypto); +-- +2.43.0 + diff --git a/queue-6.1/csky-fix-arch_jump_label_transform_static-override.patch b/queue-6.1/csky-fix-arch_jump_label_transform_static-override.patch new file mode 100644 index 00000000000..7d8816cf3c7 --- /dev/null +++ b/queue-6.1/csky-fix-arch_jump_label_transform_static-override.patch @@ -0,0 +1,45 @@ +From a5d83457e8f3f4e42250c61f0c5bdcf8462241e1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 6 Nov 2023 22:02:59 +0100 +Subject: csky: fix arch_jump_label_transform_static override + +From: Arnd Bergmann + +[ Upstream commit ca8e45c8048a2c9503c74751d25414601f730580 ] + +The arch_jump_label_transform_static() function in csky was originally meant to +override the generic __weak function, but that got changed to an #ifndef check. + +This showed up as a missing-prototype warning: +arch/csky/kernel/jump_label.c:43:6: error: no previous prototype for 'arch_jump_label_transform_static' [-Werror=missing-prototypes] + +Change the method to use the new method of having a #define and a prototype +for the global function. + +Fixes: 7e6b9db27de9 ("jump_label: make initial NOP patching the special case") +Fixes: 4e8bb4ba5a55 ("csky: Add jump-label implementation") +Reviewed-by: Guo Ren +Signed-off-by: Arnd Bergmann +Signed-off-by: Sasha Levin +--- + arch/csky/include/asm/jump_label.h | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/csky/include/asm/jump_label.h b/arch/csky/include/asm/jump_label.h +index d488ba6084bc..98a3f4b168bd 100644 +--- a/arch/csky/include/asm/jump_label.h ++++ b/arch/csky/include/asm/jump_label.h +@@ -43,5 +43,10 @@ static __always_inline bool arch_static_branch_jump(struct static_key *key, + return true; + } + ++enum jump_label_type; ++void arch_jump_label_transform_static(struct jump_entry *entry, ++ enum jump_label_type type); ++#define arch_jump_label_transform_static arch_jump_label_transform_static ++ + #endif /* __ASSEMBLY__ */ + #endif /* __ASM_CSKY_JUMP_LABEL_H */ +-- +2.43.0 + diff --git a/queue-6.1/dma-mapping-clear-dev-dma_mem-to-null-after-freeing-.patch b/queue-6.1/dma-mapping-clear-dev-dma_mem-to-null-after-freeing-.patch new file mode 100644 index 00000000000..86194733050 --- /dev/null +++ b/queue-6.1/dma-mapping-clear-dev-dma_mem-to-null-after-freeing-.patch @@ -0,0 +1,44 @@ +From 7aa9411719c91fe8b72fe505d72e053e0579512a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 14 Dec 2023 16:25:26 +0800 +Subject: dma-mapping: clear dev->dma_mem to NULL after freeing it + +From: Joakim Zhang + +[ Upstream commit b07bc2347672cc8c7293c64499f1488278c5ca3d ] + +Reproduced with below sequence: +dma_declare_coherent_memory()->dma_release_coherent_memory() +->dma_declare_coherent_memory()->"return -EBUSY" error + +It will return -EBUSY from the dma_assign_coherent_memory() +in dma_declare_coherent_memory(), the reason is that dev->dma_mem +pointer has not been set to NULL after it's freed. + +Fixes: cf65a0f6f6ff ("dma-mapping: move all DMA mapping code to kernel/dma") +Signed-off-by: Joakim Zhang +Signed-off-by: Christoph Hellwig +Signed-off-by: Sasha Levin +--- + kernel/dma/coherent.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/kernel/dma/coherent.c b/kernel/dma/coherent.c +index c21abc77c53e..ff5683a57f77 100644 +--- a/kernel/dma/coherent.c ++++ b/kernel/dma/coherent.c +@@ -132,8 +132,10 @@ int dma_declare_coherent_memory(struct device *dev, phys_addr_t phys_addr, + + void dma_release_coherent_memory(struct device *dev) + { +- if (dev) ++ if (dev) { + _dma_release_coherent_memory(dev->dma_mem); ++ dev->dma_mem = NULL; ++ } + } + + static void *__dma_alloc_from_coherent(struct device *dev, +-- +2.43.0 + diff --git a/queue-6.1/driver-core-remove-config_sysfs_deprecated-and-confi.patch b/queue-6.1/driver-core-remove-config_sysfs_deprecated-and-confi.patch new file mode 100644 index 00000000000..1f73bd1aafa --- /dev/null +++ b/queue-6.1/driver-core-remove-config_sysfs_deprecated-and-confi.patch @@ -0,0 +1,278 @@ +From 59215e74fb040fb277b4635b3a4ad1189a0b5e6e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 23 Feb 2023 08:33:26 +0100 +Subject: driver core: remove CONFIG_SYSFS_DEPRECATED and + CONFIG_SYSFS_DEPRECATED_V2 + +From: Greg Kroah-Hartman + +[ Upstream commit 721da5cee9d43901105f5b8bd33fcb9101b12fc3 ] + +CONFIG_SYSFS_DEPRECATED was added in commit 88a22c985e35 +("CONFIG_SYSFS_DEPRECATED") in 2006 to allow systems with older versions +of some tools (i.e. Fedora 3's version of udev) to boot properly. Four +years later, in 2010, the option was attempted to be removed as most of +userspace should have been fixed up properly by then, but some kernel +developers clung to those old systems and refused to update, so we added +CONFIG_SYSFS_DEPRECATED_V2 in commit e52eec13cd6b ("SYSFS: Allow boot +time switching between deprecated and modern sysfs layout") to allow +them to continue to boot properly, and we allowed a boot time parameter +to be used to switch back to the old format if needed. + +Over time, the logic that was covered under these config options was +slowly removed from individual driver subsystems successfully, removed, +and the only thing that is now left in the kernel are some changes in +the block layer's representation in sysfs where real directories are +used instead of symlinks like normal. + +Because the original changes were done to userspace tools in 2006, and +all distros that use those tools are long end-of-life, and older +non-udev-based systems do not care about the block layer's sysfs +representation, it is time to finally remove this old logic and the +config entries from the kernel. + +Cc: Jonathan Corbet +Cc: "Rafael J. Wysocki" +Cc: linux-block@vger.kernel.org +Cc: linux-doc@vger.kernel.org +Acked-by: Jens Axboe +Link: https://lore.kernel.org/r/20230223073326.2073220-1-gregkh@linuxfoundation.org +Signed-off-by: Greg Kroah-Hartman +Stable-dep-of: 5fa3d1a00c2d ("block: Set memalloc_noio to false on device_add_disk() error path") +Signed-off-by: Sasha Levin +--- + .../admin-guide/kernel-parameters.txt | 9 ----- + block/genhd.c | 19 ++++------ + drivers/base/class.c | 2 +- + drivers/base/core.c | 37 ------------------ + include/linux/device.h | 6 --- + init/Kconfig | 38 ------------------- + 6 files changed, 8 insertions(+), 103 deletions(-) + +diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt +index 4ad60e127e04..d44a25ed43d7 100644 +--- a/Documentation/admin-guide/kernel-parameters.txt ++++ b/Documentation/admin-guide/kernel-parameters.txt +@@ -6127,15 +6127,6 @@ + later by a loaded module cannot be set this way. + Example: sysctl.vm.swappiness=40 + +- sysfs.deprecated=0|1 [KNL] +- Enable/disable old style sysfs layout for old udev +- on older distributions. When this option is enabled +- very new udev will not work anymore. When this option +- is disabled (or CONFIG_SYSFS_DEPRECATED not compiled) +- in older udev will not work anymore. +- Default depends on CONFIG_SYSFS_DEPRECATED_V2 set in +- the kernel configuration. +- + sysrq_always_enabled + [KNL] + Ignore sysrq setting - this boot parameter will +diff --git a/block/genhd.c b/block/genhd.c +index afab646d12c8..886e75213f6a 100644 +--- a/block/genhd.c ++++ b/block/genhd.c +@@ -473,12 +473,10 @@ int __must_check device_add_disk(struct device *parent, struct gendisk *disk, + if (ret) + goto out_device_del; + +- if (!sysfs_deprecated) { +- ret = sysfs_create_link(block_depr, &ddev->kobj, +- kobject_name(&ddev->kobj)); +- if (ret) +- goto out_device_del; +- } ++ ret = sysfs_create_link(block_depr, &ddev->kobj, ++ kobject_name(&ddev->kobj)); ++ if (ret) ++ goto out_device_del; + + /* + * avoid probable deadlock caused by allocating memory with +@@ -565,8 +563,7 @@ int __must_check device_add_disk(struct device *parent, struct gendisk *disk, + out_del_integrity: + blk_integrity_del(disk); + out_del_block_link: +- if (!sysfs_deprecated) +- sysfs_remove_link(block_depr, dev_name(ddev)); ++ sysfs_remove_link(block_depr, dev_name(ddev)); + out_device_del: + device_del(ddev); + out_free_ext_minor: +@@ -663,8 +660,7 @@ void del_gendisk(struct gendisk *disk) + + part_stat_set_all(disk->part0, 0); + disk->part0->bd_stamp = 0; +- if (!sysfs_deprecated) +- sysfs_remove_link(block_depr, dev_name(disk_to_dev(disk))); ++ sysfs_remove_link(block_depr, dev_name(disk_to_dev(disk))); + pm_runtime_set_memalloc_noio(disk_to_dev(disk), false); + device_del(disk_to_dev(disk)); + +@@ -916,8 +912,7 @@ static int __init genhd_device_init(void) + register_blkdev(BLOCK_EXT_MAJOR, "blkext"); + + /* create top-level block dir */ +- if (!sysfs_deprecated) +- block_depr = kobject_create_and_add("block", NULL); ++ block_depr = kobject_create_and_add("block", NULL); + return 0; + } + +diff --git a/drivers/base/class.c b/drivers/base/class.c +index 8ceafb7d0203..254963a226ba 100644 +--- a/drivers/base/class.c ++++ b/drivers/base/class.c +@@ -176,7 +176,7 @@ int __class_register(struct class *cls, struct lock_class_key *key) + + #if defined(CONFIG_BLOCK) + /* let the block class directory show up in the root of sysfs */ +- if (!sysfs_deprecated || cls != &block_class) ++ if (cls != &block_class) + cp->subsys.kobj.kset = class_kset; + #else + cp->subsys.kobj.kset = class_kset; +diff --git a/drivers/base/core.c b/drivers/base/core.c +index af90bfb0cc3d..578b21f08763 100644 +--- a/drivers/base/core.c ++++ b/drivers/base/core.c +@@ -35,19 +35,6 @@ + #include "physical_location.h" + #include "power/power.h" + +-#ifdef CONFIG_SYSFS_DEPRECATED +-#ifdef CONFIG_SYSFS_DEPRECATED_V2 +-long sysfs_deprecated = 1; +-#else +-long sysfs_deprecated = 0; +-#endif +-static int __init sysfs_deprecated_setup(char *arg) +-{ +- return kstrtol(arg, 10, &sysfs_deprecated); +-} +-early_param("sysfs.deprecated", sysfs_deprecated_setup); +-#endif +- + /* Device links support. */ + static LIST_HEAD(deferred_sync); + static unsigned int defer_sync_state_count = 1; +@@ -3216,15 +3203,6 @@ static struct kobject *get_device_parent(struct device *dev, + struct kobject *parent_kobj; + struct kobject *k; + +-#ifdef CONFIG_BLOCK +- /* block disks show up in /sys/block */ +- if (sysfs_deprecated && dev->class == &block_class) { +- if (parent && parent->class == &block_class) +- return &parent->kobj; +- return &block_class.p->subsys.kobj; +- } +-#endif +- + /* + * If we have no parent, we live in "virtual". + * Class-devices with a non class-device as parent, live +@@ -3396,12 +3374,6 @@ static int device_add_class_symlinks(struct device *dev) + goto out_subsys; + } + +-#ifdef CONFIG_BLOCK +- /* /sys/block has directories and does not need symlinks */ +- if (sysfs_deprecated && dev->class == &block_class) +- return 0; +-#endif +- + /* link in the class directory pointing to the device */ + error = sysfs_create_link(&dev->class->p->subsys.kobj, + &dev->kobj, dev_name(dev)); +@@ -3431,10 +3403,6 @@ static void device_remove_class_symlinks(struct device *dev) + if (dev->parent && device_is_not_partition(dev)) + sysfs_remove_link(&dev->kobj, "device"); + sysfs_remove_link(&dev->kobj, "subsystem"); +-#ifdef CONFIG_BLOCK +- if (sysfs_deprecated && dev->class == &block_class) +- return; +-#endif + sysfs_delete_link(&dev->class->p->subsys.kobj, &dev->kobj, dev_name(dev)); + } + +@@ -4742,11 +4710,6 @@ int device_change_owner(struct device *dev, kuid_t kuid, kgid_t kgid) + if (error) + goto out; + +-#ifdef CONFIG_BLOCK +- if (sysfs_deprecated && dev->class == &block_class) +- goto out; +-#endif +- + /* + * Change the owner of the symlink located in the class directory of + * the device class associated with @dev which points to the actual +diff --git a/include/linux/device.h b/include/linux/device.h +index 7cf24330d681..a46b3b4e3126 100644 +--- a/include/linux/device.h ++++ b/include/linux/device.h +@@ -1102,10 +1102,4 @@ int dev_err_probe(const struct device *dev, int err, const char *fmt, ...); + #define MODULE_ALIAS_CHARDEV_MAJOR(major) \ + MODULE_ALIAS("char-major-" __stringify(major) "-*") + +-#ifdef CONFIG_SYSFS_DEPRECATED +-extern long sysfs_deprecated; +-#else +-#define sysfs_deprecated 0 +-#endif +- + #endif /* _DEVICE_H_ */ +diff --git a/init/Kconfig b/init/Kconfig +index 148704640252..8219099a0326 100644 +--- a/init/Kconfig ++++ b/init/Kconfig +@@ -1292,44 +1292,6 @@ config SCHED_AUTOGROUP + desktop applications. Task group autogeneration is currently based + upon task session. + +-config SYSFS_DEPRECATED +- bool "Enable deprecated sysfs features to support old userspace tools" +- depends on SYSFS +- default n +- help +- This option adds code that switches the layout of the "block" class +- devices, to not show up in /sys/class/block/, but only in +- /sys/block/. +- +- This switch is only active when the sysfs.deprecated=1 boot option is +- passed or the SYSFS_DEPRECATED_V2 option is set. +- +- This option allows new kernels to run on old distributions and tools, +- which might get confused by /sys/class/block/. Since 2007/2008 all +- major distributions and tools handle this just fine. +- +- Recent distributions and userspace tools after 2009/2010 depend on +- the existence of /sys/class/block/, and will not work with this +- option enabled. +- +- Only if you are using a new kernel on an old distribution, you might +- need to say Y here. +- +-config SYSFS_DEPRECATED_V2 +- bool "Enable deprecated sysfs features by default" +- default n +- depends on SYSFS +- depends on SYSFS_DEPRECATED +- help +- Enable deprecated sysfs by default. +- +- See the CONFIG_SYSFS_DEPRECATED option for more details about this +- option. +- +- Only if you are using a new kernel on an old distribution, you might +- need to say Y here. Even then, odds are you would not need it +- enabled, you can always pass the boot option if absolutely necessary. +- + config RELAY + bool "Kernel->user space relay support (formerly relayfs)" + select IRQ_WORK +-- +2.43.0 + diff --git a/queue-6.1/drivers-amd-pm-fix-a-use-after-free-in-kv_parse_powe.patch b/queue-6.1/drivers-amd-pm-fix-a-use-after-free-in-kv_parse_powe.patch new file mode 100644 index 00000000000..a8497568bfd --- /dev/null +++ b/queue-6.1/drivers-amd-pm-fix-a-use-after-free-in-kv_parse_powe.patch @@ -0,0 +1,48 @@ +From beac9b1debc6aa9629e09bd01a203b1a16cd7239 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 15 Dec 2023 00:24:58 +0800 +Subject: drivers/amd/pm: fix a use-after-free in kv_parse_power_table + +From: Zhipeng Lu + +[ Upstream commit 28dd788382c43b330480f57cd34cde0840896743 ] + +When ps allocated by kzalloc equals to NULL, kv_parse_power_table +frees adev->pm.dpm.ps that allocated before. However, after the control +flow goes through the following call chains: + +kv_parse_power_table + |-> kv_dpm_init + |-> kv_dpm_sw_init + |-> kv_dpm_fini + +The adev->pm.dpm.ps is used in the for loop of kv_dpm_fini after its +first free in kv_parse_power_table and causes a use-after-free bug. + +Fixes: a2e73f56fa62 ("drm/amdgpu: Add support for CIK parts") +Signed-off-by: Zhipeng Lu +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c +index f5e08b60f66e..d17bfa111aa7 100644 +--- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c ++++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c +@@ -2748,10 +2748,8 @@ static int kv_parse_power_table(struct amdgpu_device *adev) + non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) + &non_clock_info_array->nonClockInfo[non_clock_array_index]; + ps = kzalloc(sizeof(struct kv_ps), GFP_KERNEL); +- if (ps == NULL) { +- kfree(adev->pm.dpm.ps); ++ if (ps == NULL) + return -ENOMEM; +- } + adev->pm.dpm.ps[i].ps_priv = ps; + k = 0; + idx = (u8 *)&power_state->v2.clockInfoIndex[0]; +-- +2.43.0 + diff --git a/queue-6.1/drivers-clk-zynqmp-calculate-closest-mux-rate.patch b/queue-6.1/drivers-clk-zynqmp-calculate-closest-mux-rate.patch new file mode 100644 index 00000000000..2b2fd5379fb --- /dev/null +++ b/queue-6.1/drivers-clk-zynqmp-calculate-closest-mux-rate.patch @@ -0,0 +1,61 @@ +From 3c39565ca936cd8a9f92cd424f9dcf0e7b8e24af Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 29 Nov 2023 03:29:15 -0800 +Subject: drivers: clk: zynqmp: calculate closest mux rate + +From: Jay Buddhabhatti + +[ Upstream commit b782921ddd7f84f524723090377903f399fdbbcb ] + +Currently zynqmp clock driver is not calculating closest mux rate and +because of that Linux is not setting proper frequency for CPU and +not able to set given frequency for dynamic frequency scaling. + +E.g., In current logic initial acpu clock parent and frequency as below +apll1 0 0 0 2199999978 0 0 50000 Y + acpu0_mux 0 0 0 2199999978 0 0 50000 Y + acpu0_idiv1 0 0 0 2199999978 0 0 50000 Y + acpu0 0 0 0 2199999978 0 0 50000 Y + +After changing acpu frequency to 549999994 Hz using CPU freq scaling its +selecting incorrect parent which is not closest frequency. +rpll_to_xpd 0 0 0 1599999984 0 0 50000 Y + acpu0_mux 0 0 0 1599999984 0 0 50000 Y + acpu0_div1 0 0 0 533333328 0 0 50000 Y + acpu0 0 0 0 533333328 0 0 50000 Y + +Parent should remain same since 549999994 = 2199999978 / 4. + +So use __clk_mux_determine_rate_closest() generic function to calculate +closest rate for mux clock. After this change its selecting correct +parent and correct clock rate. +apll1 0 0 0 2199999978 0 0 50000 Y + acpu0_mux 0 0 0 2199999978 0 0 50000 Y + acpu0_div1 0 0 0 549999995 0 0 50000 Y + acpu0 0 0 0 549999995 0 0 50000 Y + +Fixes: 3fde0e16d016 ("drivers: clk: Add ZynqMP clock driver") +Signed-off-by: Jay Buddhabhatti +Link: https://lore.kernel.org/r/20231129112916.23125-2-jay.buddhabhatti@amd.com +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/zynqmp/clk-mux-zynqmp.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/zynqmp/clk-mux-zynqmp.c b/drivers/clk/zynqmp/clk-mux-zynqmp.c +index 60359333f26d..9b5d3050b742 100644 +--- a/drivers/clk/zynqmp/clk-mux-zynqmp.c ++++ b/drivers/clk/zynqmp/clk-mux-zynqmp.c +@@ -89,7 +89,7 @@ static int zynqmp_clk_mux_set_parent(struct clk_hw *hw, u8 index) + static const struct clk_ops zynqmp_clk_mux_ops = { + .get_parent = zynqmp_clk_mux_get_parent, + .set_parent = zynqmp_clk_mux_set_parent, +- .determine_rate = __clk_mux_determine_rate, ++ .determine_rate = __clk_mux_determine_rate_closest, + }; + + static const struct clk_ops zynqmp_clk_mux_ro_ops = { +-- +2.43.0 + diff --git a/queue-6.1/drivers-clk-zynqmp-update-divider-round-rate-logic.patch b/queue-6.1/drivers-clk-zynqmp-update-divider-round-rate-logic.patch new file mode 100644 index 00000000000..2cb228e857f --- /dev/null +++ b/queue-6.1/drivers-clk-zynqmp-update-divider-round-rate-logic.patch @@ -0,0 +1,121 @@ +From 22eb36784eade42dfb64ceae2d628e8bf0b19e1f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 29 Nov 2023 03:29:16 -0800 +Subject: drivers: clk: zynqmp: update divider round rate logic + +From: Jay Buddhabhatti + +[ Upstream commit 1fe15be1fb613534ecbac5f8c3f8744f757d237d ] + +Currently zynqmp divider round rate is considering single parent and +calculating rate and parent rate accordingly. But if divider clock flag +is set to SET_RATE_PARENT then its not trying to traverse through all +parent rate and not selecting best parent rate from that. So use common +divider_round_rate() which is traversing through all clock parents and +its rate and calculating proper parent rate. + +Fixes: 3fde0e16d016 ("drivers: clk: Add ZynqMP clock driver") +Signed-off-by: Jay Buddhabhatti +Link: https://lore.kernel.org/r/20231129112916.23125-3-jay.buddhabhatti@amd.com +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/zynqmp/divider.c | 66 +++--------------------------------- + 1 file changed, 5 insertions(+), 61 deletions(-) + +diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c +index 33a3b2a22659..5a00487ae408 100644 +--- a/drivers/clk/zynqmp/divider.c ++++ b/drivers/clk/zynqmp/divider.c +@@ -110,52 +110,6 @@ static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw, + return DIV_ROUND_UP_ULL(parent_rate, value); + } + +-static void zynqmp_get_divider2_val(struct clk_hw *hw, +- unsigned long rate, +- struct zynqmp_clk_divider *divider, +- u32 *bestdiv) +-{ +- int div1; +- int div2; +- long error = LONG_MAX; +- unsigned long div1_prate; +- struct clk_hw *div1_parent_hw; +- struct zynqmp_clk_divider *pdivider; +- struct clk_hw *div2_parent_hw = clk_hw_get_parent(hw); +- +- if (!div2_parent_hw) +- return; +- +- pdivider = to_zynqmp_clk_divider(div2_parent_hw); +- if (!pdivider) +- return; +- +- div1_parent_hw = clk_hw_get_parent(div2_parent_hw); +- if (!div1_parent_hw) +- return; +- +- div1_prate = clk_hw_get_rate(div1_parent_hw); +- *bestdiv = 1; +- for (div1 = 1; div1 <= pdivider->max_div;) { +- for (div2 = 1; div2 <= divider->max_div;) { +- long new_error = ((div1_prate / div1) / div2) - rate; +- +- if (abs(new_error) < abs(error)) { +- *bestdiv = div2; +- error = new_error; +- } +- if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) +- div2 = div2 << 1; +- else +- div2++; +- } +- if (pdivider->flags & CLK_DIVIDER_POWER_OF_TWO) +- div1 = div1 << 1; +- else +- div1++; +- } +-} +- + /** + * zynqmp_clk_divider_round_rate() - Round rate of divider clock + * @hw: handle between common and hardware-specific interfaces +@@ -174,6 +128,7 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, + u32 div_type = divider->div_type; + u32 bestdiv; + int ret; ++ u8 width; + + /* if read only, just return current value */ + if (divider->flags & CLK_DIVIDER_READ_ONLY) { +@@ -193,23 +148,12 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, + return DIV_ROUND_UP_ULL((u64)*prate, bestdiv); + } + +- bestdiv = zynqmp_divider_get_val(*prate, rate, divider->flags); +- +- /* +- * In case of two divisors, compute best divider values and return +- * divider2 value based on compute value. div1 will be automatically +- * set to optimum based on required total divider value. +- */ +- if (div_type == TYPE_DIV2 && +- (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { +- zynqmp_get_divider2_val(hw, rate, divider, &bestdiv); +- } ++ width = fls(divider->max_div); + +- if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac) +- bestdiv = rate % *prate ? 1 : bestdiv; ++ rate = divider_round_rate(hw, rate, prate, NULL, width, divider->flags); + +- bestdiv = min_t(u32, bestdiv, divider->max_div); +- *prate = rate * bestdiv; ++ if (divider->is_frac && (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && (rate % *prate)) ++ *prate = rate; + + return rate; + } +-- +2.43.0 + diff --git a/queue-6.1/drm-amd-pm-fix-a-double-free-in-amdgpu_parse_extende.patch b/queue-6.1/drm-amd-pm-fix-a-double-free-in-amdgpu_parse_extende.patch new file mode 100644 index 00000000000..7ed7e778dd6 --- /dev/null +++ b/queue-6.1/drm-amd-pm-fix-a-double-free-in-amdgpu_parse_extende.patch @@ -0,0 +1,198 @@ +From b16854e6c3631d3412cb7a3adbd9d284d416752f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 15 Dec 2023 00:59:38 +0800 +Subject: drm/amd/pm: fix a double-free in amdgpu_parse_extended_power_table + +From: Zhipeng Lu + +[ Upstream commit a6582701178a47c4d0cb2188c965c59c0c0647c8 ] + +The amdgpu_free_extended_power_table is called in every error-handling +paths of amdgpu_parse_extended_power_table. However, after the following +call chain of returning: + +amdgpu_parse_extended_power_table + |-> kv_dpm_init / si_dpm_init + (the only two caller of amdgpu_parse_extended_power_table) + |-> kv_dpm_sw_init / si_dpm_sw_init + (the only caller of kv_dpm_init / si_dpm_init, accordingly) + |-> kv_dpm_fini / si_dpm_fini + (goto dpm_failed in xx_dpm_sw_init) + |-> amdgpu_free_extended_power_table + +As above, the amdgpu_free_extended_power_table is called twice in this +returning chain and thus a double-free is triggered. Similarily, the +last kfree in amdgpu_parse_extended_power_table also cause a double free +with amdgpu_free_extended_power_table in kv_dpm_fini. + +Fixes: 84176663e70d ("drm/amd/pm: create a new holder for those APIs used only by legacy ASICs(si/kv)") +Signed-off-by: Zhipeng Lu +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + .../gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c | 52 +++++-------------- + 1 file changed, 13 insertions(+), 39 deletions(-) + +diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c +index d3fe149d8476..291223ea7ba7 100644 +--- a/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c ++++ b/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c +@@ -272,10 +272,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) + le16_to_cpu(power_info->pplib4.usVddcDependencyOnSCLKOffset)); + ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, + dep_table); +- if (ret) { +- amdgpu_free_extended_power_table(adev); ++ if (ret) + return ret; +- } + } + if (power_info->pplib4.usVddciDependencyOnMCLKOffset) { + dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *) +@@ -283,10 +281,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) + le16_to_cpu(power_info->pplib4.usVddciDependencyOnMCLKOffset)); + ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, + dep_table); +- if (ret) { +- amdgpu_free_extended_power_table(adev); ++ if (ret) + return ret; +- } + } + if (power_info->pplib4.usVddcDependencyOnMCLKOffset) { + dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *) +@@ -294,10 +290,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) + le16_to_cpu(power_info->pplib4.usVddcDependencyOnMCLKOffset)); + ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, + dep_table); +- if (ret) { +- amdgpu_free_extended_power_table(adev); ++ if (ret) + return ret; +- } + } + if (power_info->pplib4.usMvddDependencyOnMCLKOffset) { + dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *) +@@ -305,10 +299,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) + le16_to_cpu(power_info->pplib4.usMvddDependencyOnMCLKOffset)); + ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, + dep_table); +- if (ret) { +- amdgpu_free_extended_power_table(adev); ++ if (ret) + return ret; +- } + } + if (power_info->pplib4.usMaxClockVoltageOnDCOffset) { + ATOM_PPLIB_Clock_Voltage_Limit_Table *clk_v = +@@ -339,10 +331,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) + kcalloc(psl->ucNumEntries, + sizeof(struct amdgpu_phase_shedding_limits_entry), + GFP_KERNEL); +- if (!adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries) { +- amdgpu_free_extended_power_table(adev); ++ if (!adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries) + return -ENOMEM; +- } + + entry = &psl->entries[0]; + for (i = 0; i < psl->ucNumEntries; i++) { +@@ -383,10 +373,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) + ATOM_PPLIB_CAC_Leakage_Record *entry; + u32 size = cac_table->ucNumEntries * sizeof(struct amdgpu_cac_leakage_table); + adev->pm.dpm.dyn_state.cac_leakage_table.entries = kzalloc(size, GFP_KERNEL); +- if (!adev->pm.dpm.dyn_state.cac_leakage_table.entries) { +- amdgpu_free_extended_power_table(adev); ++ if (!adev->pm.dpm.dyn_state.cac_leakage_table.entries) + return -ENOMEM; +- } + entry = &cac_table->entries[0]; + for (i = 0; i < cac_table->ucNumEntries; i++) { + if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { +@@ -438,10 +426,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) + sizeof(struct amdgpu_vce_clock_voltage_dependency_entry); + adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries = + kzalloc(size, GFP_KERNEL); +- if (!adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries) { +- amdgpu_free_extended_power_table(adev); ++ if (!adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries) + return -ENOMEM; +- } + adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count = + limits->numEntries; + entry = &limits->entries[0]; +@@ -493,10 +479,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) + sizeof(struct amdgpu_uvd_clock_voltage_dependency_entry); + adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries = + kzalloc(size, GFP_KERNEL); +- if (!adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries) { +- amdgpu_free_extended_power_table(adev); ++ if (!adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries) + return -ENOMEM; +- } + adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count = + limits->numEntries; + entry = &limits->entries[0]; +@@ -525,10 +509,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) + sizeof(struct amdgpu_clock_voltage_dependency_entry); + adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries = + kzalloc(size, GFP_KERNEL); +- if (!adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries) { +- amdgpu_free_extended_power_table(adev); ++ if (!adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries) + return -ENOMEM; +- } + adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count = + limits->numEntries; + entry = &limits->entries[0]; +@@ -548,10 +530,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) + le16_to_cpu(ext_hdr->usPPMTableOffset)); + adev->pm.dpm.dyn_state.ppm_table = + kzalloc(sizeof(struct amdgpu_ppm_table), GFP_KERNEL); +- if (!adev->pm.dpm.dyn_state.ppm_table) { +- amdgpu_free_extended_power_table(adev); ++ if (!adev->pm.dpm.dyn_state.ppm_table) + return -ENOMEM; +- } + adev->pm.dpm.dyn_state.ppm_table->ppm_design = ppm->ucPpmDesign; + adev->pm.dpm.dyn_state.ppm_table->cpu_core_number = + le16_to_cpu(ppm->usCpuCoreNumber); +@@ -583,10 +563,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) + sizeof(struct amdgpu_clock_voltage_dependency_entry); + adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries = + kzalloc(size, GFP_KERNEL); +- if (!adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries) { +- amdgpu_free_extended_power_table(adev); ++ if (!adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries) + return -ENOMEM; +- } + adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count = + limits->numEntries; + entry = &limits->entries[0]; +@@ -606,10 +584,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) + ATOM_PowerTune_Table *pt; + adev->pm.dpm.dyn_state.cac_tdp_table = + kzalloc(sizeof(struct amdgpu_cac_tdp_table), GFP_KERNEL); +- if (!adev->pm.dpm.dyn_state.cac_tdp_table) { +- amdgpu_free_extended_power_table(adev); ++ if (!adev->pm.dpm.dyn_state.cac_tdp_table) + return -ENOMEM; +- } + if (rev > 0) { + ATOM_PPLIB_POWERTUNE_Table_V1 *ppt = (ATOM_PPLIB_POWERTUNE_Table_V1 *) + (mode_info->atom_context->bios + data_offset + +@@ -645,10 +621,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) + ret = amdgpu_parse_clk_voltage_dep_table( + &adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk, + dep_table); +- if (ret) { +- kfree(adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk.entries); ++ if (ret) + return ret; +- } + } + } + +-- +2.43.0 + diff --git a/queue-6.1/drm-amd-pm-fix-a-double-free-in-si_dpm_init.patch b/queue-6.1/drm-amd-pm-fix-a-double-free-in-si_dpm_init.patch new file mode 100644 index 00000000000..53c5e0cff97 --- /dev/null +++ b/queue-6.1/drm-amd-pm-fix-a-double-free-in-si_dpm_init.patch @@ -0,0 +1,45 @@ +From 98daddb0b369995391a70fb6136c87b7f59e930a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 14 Dec 2023 23:24:11 +0800 +Subject: drm/amd/pm: fix a double-free in si_dpm_init + +From: Zhipeng Lu + +[ Upstream commit ac16667237a82e2597e329eb9bc520d1cf9dff30 ] + +When the allocation of +adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries fails, +amdgpu_free_extended_power_table is called to free some fields of adev. +However, when the control flow returns to si_dpm_sw_init, it goes to +label dpm_failed and calls si_dpm_fini, which calls +amdgpu_free_extended_power_table again and free those fields again. Thus +a double-free is triggered. + +Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)") +Signed-off-by: Zhipeng Lu +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 5 ++--- + 1 file changed, 2 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +index c89cfef7cafa..dc0a6fba7050 100644 +--- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c ++++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +@@ -7379,10 +7379,9 @@ static int si_dpm_init(struct amdgpu_device *adev) + kcalloc(4, + sizeof(struct amdgpu_clock_voltage_dependency_entry), + GFP_KERNEL); +- if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { +- amdgpu_free_extended_power_table(adev); ++ if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) + return -ENOMEM; +- } ++ + adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; + adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; + adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; +-- +2.43.0 + diff --git a/queue-6.1/drm-amd-pm-smu7-fix-a-memleak-in-smu7_hwmgr_backend_.patch b/queue-6.1/drm-amd-pm-smu7-fix-a-memleak-in-smu7_hwmgr_backend_.patch new file mode 100644 index 00000000000..931dc65f37b --- /dev/null +++ b/queue-6.1/drm-amd-pm-smu7-fix-a-memleak-in-smu7_hwmgr_backend_.patch @@ -0,0 +1,53 @@ +From 3b0df803f427ec6985a815d22fe5cc0bf2b6a83e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 24 Dec 2023 16:22:47 +0800 +Subject: drm/amd/pm/smu7: fix a memleak in smu7_hwmgr_backend_init + +From: Zhipeng Lu + +[ Upstream commit 2f3be3ca779b11c332441b10e00443a2510f4d7b ] + +The hwmgr->backend, (i.e. data) allocated by kzalloc is not freed in +the error-handling paths of smu7_get_evv_voltages and +smu7_update_edc_leakage_table. However, it did be freed in the +error-handling of phm_initializa_dynamic_state_adjustment_rule_settings, +by smu7_hwmgr_backend_fini. So the lack of free in smu7_get_evv_voltages +and smu7_update_edc_leakage_table is considered a memleak in this patch. + +Fixes: 599a7e9fe1b6 ("drm/amd/powerplay: implement smu7 hwmgr to manager asics with smu ip version 7.") +Fixes: 8f0804c6b7d0 ("drm/amd/pm: add edc leakage controller setting") +Signed-off-by: Zhipeng Lu +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c +index a31a62a1ce0b..5e9410117712 100644 +--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c ++++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c +@@ -2987,6 +2987,8 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr) + result = smu7_get_evv_voltages(hwmgr); + if (result) { + pr_info("Get EVV Voltage Failed. Abort Driver loading!\n"); ++ kfree(hwmgr->backend); ++ hwmgr->backend = NULL; + return -EINVAL; + } + } else { +@@ -3032,8 +3034,10 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr) + } + + result = smu7_update_edc_leakage_table(hwmgr); +- if (result) ++ if (result) { ++ smu7_hwmgr_backend_fini(hwmgr); + return result; ++ } + + return 0; + } +-- +2.43.0 + diff --git a/queue-6.1/drm-amdgpu-debugfs-fix-error-code-when-smc-register-.patch b/queue-6.1/drm-amdgpu-debugfs-fix-error-code-when-smc-register-.patch new file mode 100644 index 00000000000..59502642938 --- /dev/null +++ b/queue-6.1/drm-amdgpu-debugfs-fix-error-code-when-smc-register-.patch @@ -0,0 +1,48 @@ +From 6637415ab8ed69a50aef3247f215d85de25d32cd Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 27 Nov 2023 17:26:29 -0500 +Subject: drm/amdgpu/debugfs: fix error code when smc register accessors are + NULL +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Alex Deucher + +[ Upstream commit afe58346d5d3887b3e49ff623d2f2e471f232a8d ] + +Should be -EOPNOTSUPP. + +Fixes: 5104fdf50d32 ("drm/amdgpu: Fix a null pointer access when the smc_rreg pointer is NULL") +Reviewed-by: Christian König +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +index 8123feb1a116..06ab6066da61 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +@@ -596,7 +596,7 @@ static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf, + int r; + + if (!adev->smc_rreg) +- return -EPERM; ++ return -EOPNOTSUPP; + + if (size & 0x3 || *pos & 0x3) + return -EINVAL; +@@ -655,7 +655,7 @@ static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user * + int r; + + if (!adev->smc_wreg) +- return -EPERM; ++ return -EOPNOTSUPP; + + if (size & 0x3 || *pos & 0x3) + return -EINVAL; +-- +2.43.0 + diff --git a/queue-6.1/drm-amdkfd-confirm-list-is-non-empty-before-utilizin.patch b/queue-6.1/drm-amdkfd-confirm-list-is-non-empty-before-utilizin.patch new file mode 100644 index 00000000000..3f5b6a67784 --- /dev/null +++ b/queue-6.1/drm-amdkfd-confirm-list-is-non-empty-before-utilizin.patch @@ -0,0 +1,81 @@ +From d1fa2b88398eea58286800cd42f1b85a56ff37dc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 21 Dec 2023 07:16:23 +0530 +Subject: drm/amdkfd: Confirm list is non-empty before utilizing + list_first_entry in kfd_topology.c +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Srinivasan Shanmugam + +[ Upstream commit 499839eca34ad62d43025ec0b46b80e77065f6d8 ] + +Before using list_first_entry, make sure to check that list is not +empty, if list is empty return -ENODATA. + +Fixes the below: +drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.c:1347 kfd_create_indirect_link_prop() warn: can 'gpu_link' even be NULL? +drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.c:1428 kfd_add_peer_prop() warn: can 'iolink1' even be NULL? +drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.c:1433 kfd_add_peer_prop() warn: can 'iolink2' even be NULL? + +Fixes: 0f28cca87e9a ("drm/amdkfd: Extend KFD device topology to surface peer-to-peer links") +Cc: Felix Kuehling +Cc: Christian König +Cc: Alex Deucher +Signed-off-by: Srinivasan Shanmugam +Suggested-by: Felix Kuehling +Suggested-by: Lijo Lazar +Reviewed-by: Felix Kuehling +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 21 ++++++++++++--------- + 1 file changed, 12 insertions(+), 9 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +index 713f893d2530..705d9e91b5aa 100644 +--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c ++++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +@@ -1403,10 +1403,11 @@ static int kfd_create_indirect_link_prop(struct kfd_topology_device *kdev, int g + num_cpu++; + } + ++ if (list_empty(&kdev->io_link_props)) ++ return -ENODATA; ++ + gpu_link = list_first_entry(&kdev->io_link_props, +- struct kfd_iolink_properties, list); +- if (!gpu_link) +- return -ENOMEM; ++ struct kfd_iolink_properties, list); + + for (i = 0; i < num_cpu; i++) { + /* CPU <--> GPU */ +@@ -1484,15 +1485,17 @@ static int kfd_add_peer_prop(struct kfd_topology_device *kdev, + peer->gpu->adev)) + return ret; + ++ if (list_empty(&kdev->io_link_props)) ++ return -ENODATA; ++ + iolink1 = list_first_entry(&kdev->io_link_props, +- struct kfd_iolink_properties, list); +- if (!iolink1) +- return -ENOMEM; ++ struct kfd_iolink_properties, list); ++ ++ if (list_empty(&peer->io_link_props)) ++ return -ENODATA; + + iolink2 = list_first_entry(&peer->io_link_props, +- struct kfd_iolink_properties, list); +- if (!iolink2) +- return -ENOMEM; ++ struct kfd_iolink_properties, list); + + props = kfd_alloc_struct(props); + if (!props) +-- +2.43.0 + diff --git a/queue-6.1/drm-bridge-cdns-mhdp8546-fix-use-of-uninitialized-va.patch b/queue-6.1/drm-bridge-cdns-mhdp8546-fix-use-of-uninitialized-va.patch new file mode 100644 index 00000000000..5ce48f13f09 --- /dev/null +++ b/queue-6.1/drm-bridge-cdns-mhdp8546-fix-use-of-uninitialized-va.patch @@ -0,0 +1,38 @@ +From 294286ac3b6d814914a2c7efbe4ac33528371c93 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 3 Nov 2023 15:14:05 +0200 +Subject: drm/bridge: cdns-mhdp8546: Fix use of uninitialized variable + +From: Tomi Valkeinen + +[ Upstream commit 155d6fb61270dd297f128731cd155080deee8f3a ] + +'ret' could be uninitialized at the end of the function, although it's +not clear if that can happen in practice. + +Fixes: 6a3608eae6d3 ("drm: bridge: cdns-mhdp8546: Enable HDCP") +Acked-by: Maxime Ripard +Signed-off-by: Tomi Valkeinen +Link: https://patchwork.freedesktop.org/patch/msgid/20231103-uninit-fixes-v2-3-c22b2444f5f5@ideasonboard.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.c +index 946212a95598..5e3b8edcf794 100644 +--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.c ++++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.c +@@ -403,7 +403,8 @@ static int _cdns_mhdp_hdcp_disable(struct cdns_mhdp_device *mhdp) + + static int _cdns_mhdp_hdcp_enable(struct cdns_mhdp_device *mhdp, u8 content_type) + { +- int ret, tries = 3; ++ int ret = -EINVAL; ++ int tries = 3; + u32 i; + + for (i = 0; i < tries; i++) { +-- +2.43.0 + diff --git a/queue-6.1/drm-bridge-fix-typo-in-post_disable-description.patch b/queue-6.1/drm-bridge-fix-typo-in-post_disable-description.patch new file mode 100644 index 00000000000..e31ad58168a --- /dev/null +++ b/queue-6.1/drm-bridge-fix-typo-in-post_disable-description.patch @@ -0,0 +1,36 @@ +From 34ce5d893738f479609fa0c30f927a3e734176d5 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 24 Nov 2023 10:42:30 +0100 +Subject: drm/bridge: Fix typo in post_disable() description + +From: Dario Binacchi + +[ Upstream commit 288b039db225676e0c520c981a1b5a2562d893a3 ] + +s/singals/signals/ + +Fixes: 199e4e967af4 ("drm: Extract drm_bridge.h") +Signed-off-by: Dario Binacchi +Signed-off-by: Robert Foss +Link: https://patchwork.freedesktop.org/patch/msgid/20231124094253.658064-1-dario.binacchi@amarulasolutions.com +Signed-off-by: Sasha Levin +--- + include/drm/drm_bridge.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/include/drm/drm_bridge.h b/include/drm/drm_bridge.h +index 6b656ea23b96..a76f4103d48b 100644 +--- a/include/drm/drm_bridge.h ++++ b/include/drm/drm_bridge.h +@@ -191,7 +191,7 @@ struct drm_bridge_funcs { + * or &drm_encoder_helper_funcs.dpms hook. + * + * The bridge must assume that the display pipe (i.e. clocks and timing +- * singals) feeding it is no longer running when this callback is ++ * signals) feeding it is no longer running when this callback is + * called. + * + * The @post_disable callback is optional. +-- +2.43.0 + diff --git a/queue-6.1/drm-bridge-tc358767-fix-return-value-on-error-case.patch b/queue-6.1/drm-bridge-tc358767-fix-return-value-on-error-case.patch new file mode 100644 index 00000000000..425d7006366 --- /dev/null +++ b/queue-6.1/drm-bridge-tc358767-fix-return-value-on-error-case.patch @@ -0,0 +1,39 @@ +From 74cddb357e3d05db5c6a6318d9bd1a41dd559ed4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 3 Nov 2023 15:14:06 +0200 +Subject: drm/bridge: tc358767: Fix return value on error case + +From: Tomi Valkeinen + +[ Upstream commit 32bd29b619638256c5b75fb021d6d9f12fc4a984 ] + +If the hpd_pin is invalid, the driver returns 'ret'. But 'ret' contains +0, instead of an error value. + +Return -EINVAL instead. + +Fixes: f25ee5017e4f ("drm/bridge: tc358767: add IRQ and HPD support") +Acked-by: Maxime Ripard +Signed-off-by: Tomi Valkeinen +Link: https://patchwork.freedesktop.org/patch/msgid/20231103-uninit-fixes-v2-4-c22b2444f5f5@ideasonboard.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/bridge/tc358767.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c +index 7ef78283e3d3..926ab5c3c31a 100644 +--- a/drivers/gpu/drm/bridge/tc358767.c ++++ b/drivers/gpu/drm/bridge/tc358767.c +@@ -2097,7 +2097,7 @@ static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id) + } else { + if (tc->hpd_pin < 0 || tc->hpd_pin > 1) { + dev_err(dev, "failed to parse HPD number\n"); +- return ret; ++ return -EINVAL; + } + } + +-- +2.43.0 + diff --git a/queue-6.1/drm-bridge-tpd12s015-drop-buggy-__exit-annotation-fo.patch b/queue-6.1/drm-bridge-tpd12s015-drop-buggy-__exit-annotation-fo.patch new file mode 100644 index 00000000000..03a902b1e98 --- /dev/null +++ b/queue-6.1/drm-bridge-tpd12s015-drop-buggy-__exit-annotation-fo.patch @@ -0,0 +1,52 @@ +From dc2faa1f601141c7802a7df746315775c181a805 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 2 Nov 2023 17:56:42 +0100 +Subject: drm/bridge: tpd12s015: Drop buggy __exit annotation for remove + function +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Uwe Kleine-König + +[ Upstream commit ce3e112e7ae854249d8755906acc5f27e1542114 ] + +With tpd12s015_remove() marked with __exit this function is discarded +when the driver is compiled as a built-in. The result is that when the +driver unbinds there is no cleanup done which results in resource +leakage or worse. + +Fixes: cff5e6f7e83f ("drm/bridge: Add driver for the TI TPD12S015 HDMI level shifter") +Signed-off-by: Uwe Kleine-König +Signed-off-by: Thomas Zimmermann +Link: https://patchwork.freedesktop.org/patch/msgid/20231102165640.3307820-19-u.kleine-koenig@pengutronix.de +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/bridge/ti-tpd12s015.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/ti-tpd12s015.c b/drivers/gpu/drm/bridge/ti-tpd12s015.c +index e0e015243a60..b588fea12502 100644 +--- a/drivers/gpu/drm/bridge/ti-tpd12s015.c ++++ b/drivers/gpu/drm/bridge/ti-tpd12s015.c +@@ -179,7 +179,7 @@ static int tpd12s015_probe(struct platform_device *pdev) + return 0; + } + +-static int __exit tpd12s015_remove(struct platform_device *pdev) ++static int tpd12s015_remove(struct platform_device *pdev) + { + struct tpd12s015_device *tpd = platform_get_drvdata(pdev); + +@@ -197,7 +197,7 @@ MODULE_DEVICE_TABLE(of, tpd12s015_of_match); + + static struct platform_driver tpd12s015_driver = { + .probe = tpd12s015_probe, +- .remove = __exit_p(tpd12s015_remove), ++ .remove = tpd12s015_remove, + .driver = { + .name = "tpd12s015", + .of_match_table = tpd12s015_of_match, +-- +2.43.0 + diff --git a/queue-6.1/drm-drv-propagate-errors-from-drm_modeset_register_a.patch b/queue-6.1/drm-drv-propagate-errors-from-drm_modeset_register_a.patch new file mode 100644 index 00000000000..368db96c754 --- /dev/null +++ b/queue-6.1/drm-drv-propagate-errors-from-drm_modeset_register_a.patch @@ -0,0 +1,54 @@ +From 3f05ba2a45d6e15d2062a5a5ff62bf801f841763 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 3 Dec 2023 01:55:52 +0300 +Subject: drm/drv: propagate errors from drm_modeset_register_all() + +From: Dmitry Baryshkov + +[ Upstream commit 5f8dec200923a76dc57187965fd59c1136f5d085 ] + +In case the drm_modeset_register_all() function fails, its error code +will be ignored. Instead make the drm_dev_register() bail out in case of +such an error. + +Fixes: 79190ea2658a ("drm: Add callbacks for late registering") +Reviewed-by: Neil Armstrong +Signed-off-by: Dmitry Baryshkov +Signed-off-by: Maxime Ripard +Link: https://patchwork.freedesktop.org/patch/msgid/20231202225552.1283638-1-dmitry.baryshkov@linaro.org +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/drm_drv.c | 10 ++++++++-- + 1 file changed, 8 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c +index 203bf8d6c34c..d41a5eaa3e89 100644 +--- a/drivers/gpu/drm/drm_drv.c ++++ b/drivers/gpu/drm/drm_drv.c +@@ -895,8 +895,11 @@ int drm_dev_register(struct drm_device *dev, unsigned long flags) + goto err_minors; + } + +- if (drm_core_check_feature(dev, DRIVER_MODESET)) +- drm_modeset_register_all(dev); ++ if (drm_core_check_feature(dev, DRIVER_MODESET)) { ++ ret = drm_modeset_register_all(dev); ++ if (ret) ++ goto err_unload; ++ } + + DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n", + driver->name, driver->major, driver->minor, +@@ -906,6 +909,9 @@ int drm_dev_register(struct drm_device *dev, unsigned long flags) + + goto out_unlock; + ++err_unload: ++ if (dev->driver->unload) ++ dev->driver->unload(dev); + err_minors: + remove_compat_control_link(dev); + drm_minor_unregister(dev, DRM_MINOR_PRIMARY); +-- +2.43.0 + diff --git a/queue-6.1/drm-mediatek-dp-add-phy_mtk_dp-module-as-pre-depende.patch b/queue-6.1/drm-mediatek-dp-add-phy_mtk_dp-module-as-pre-depende.patch new file mode 100644 index 00000000000..05476a650ea --- /dev/null +++ b/queue-6.1/drm-mediatek-dp-add-phy_mtk_dp-module-as-pre-depende.patch @@ -0,0 +1,48 @@ +From de676391fc162429c3f06c98018dc4406f31aaf7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 21 Nov 2023 09:29:27 -0500 +Subject: drm/mediatek: dp: Add phy_mtk_dp module as pre-dependency +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Nícolas F. R. A. Prado + +[ Upstream commit c8048dd0b07df68724805254b9e994d99e9a7af4 ] + +The mtk_dp driver registers a phy device which is handled by the +phy_mtk_dp driver and assumes that the phy probe will complete +synchronously, proceeding to make use of functionality exposed by that +driver right away. This assumption however is false when the phy driver +is built as a module, causing the mtk_dp driver to fail probe in this +case. + +Add the phy_mtk_dp module as a pre-dependency to the mtk_dp module to +ensure the phy module has been loaded before the dp, so that the phy +probe happens synchrounously and the mtk_dp driver can probe +successfully even with the phy driver built as a module. + +Suggested-by: AngeloGioacchino Del Regno +Fixes: f70ac097a2cf ("drm/mediatek: Add MT8195 Embedded DisplayPort driver") +Signed-off-by: Nícolas F. R. A. Prado +Reviewed-by: AngeloGioacchino Del Regno +Reviewed-by: Guillaume Ranquet +Link: https://patchwork.kernel.org/project/dri-devel/patch/20231121142938.460846-1-nfraprado@collabora.com/ +Signed-off-by: Chun-Kuang Hu +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/mediatek/mtk_dp.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c +index 2c850b6d945b..519e23a2a017 100644 +--- a/drivers/gpu/drm/mediatek/mtk_dp.c ++++ b/drivers/gpu/drm/mediatek/mtk_dp.c +@@ -2669,3 +2669,4 @@ MODULE_AUTHOR("Markus Schneider-Pargmann "); + MODULE_AUTHOR("Bo-Chen Chen "); + MODULE_DESCRIPTION("MediaTek DisplayPort Driver"); + MODULE_LICENSE("GPL"); ++MODULE_SOFTDEP("pre: phy_mtk_dp"); +-- +2.43.0 + diff --git a/queue-6.1/drm-mediatek-fix-underrun-in-vdo1-when-switches-off-.patch b/queue-6.1/drm-mediatek-fix-underrun-in-vdo1-when-switches-off-.patch new file mode 100644 index 00000000000..39d0450552c --- /dev/null +++ b/queue-6.1/drm-mediatek-fix-underrun-in-vdo1-when-switches-off-.patch @@ -0,0 +1,41 @@ +From 65d79d15171c14f583c7850f84c237ce0ff621cd Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 14 Dec 2023 13:58:46 +0800 +Subject: drm/mediatek: Fix underrun in VDO1 when switches off the layer + +From: Hsiao Chien Sung + +[ Upstream commit 73b5ab27ab2ee616f2709dc212c2b0007894a12e ] + +Do not reset Merge while using CMDQ because reset API doesn't +wait for frame done event as CMDQ does and could lead to +underrun when the layer is switching off. + +Fixes: aaf94f7c3ae6 ("drm/mediatek: Add display merge async reset control") + +Reviewed-by: CK Hu +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Hsiao Chien Sung +Link: https://patchwork.kernel.org/project/dri-devel/patch/20231214055847.4936-23-shawn.sung@mediatek.com/ +Signed-off-by: Chun-Kuang Hu +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/mediatek/mtk_disp_merge.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c +index 6428b6203ffe..211140e87568 100644 +--- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c ++++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c +@@ -104,7 +104,7 @@ void mtk_merge_stop_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt) + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, + DISP_REG_MERGE_CTRL); + +- if (priv->async_clk) ++ if (!cmdq_pkt && priv->async_clk) + reset_control_reset(priv->reset_ctl); + } + +-- +2.43.0 + diff --git a/queue-6.1/drm-mediatek-return-error-if-mdp-rdma-failed-to-enab.patch b/queue-6.1/drm-mediatek-return-error-if-mdp-rdma-failed-to-enab.patch new file mode 100644 index 00000000000..5a8edd6e68d --- /dev/null +++ b/queue-6.1/drm-mediatek-return-error-if-mdp-rdma-failed-to-enab.patch @@ -0,0 +1,41 @@ +From 21b2220381ea1e5e5fc9d1d27b66985233f6be7f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 14 Dec 2023 13:58:44 +0800 +Subject: drm/mediatek: Return error if MDP RDMA failed to enable the clock + +From: Hsiao Chien Sung + +[ Upstream commit 21b287146adf39304193e4c49198021e06a28ded ] + +Return the result of clk_prepare_enable() instead of +always returns 0. + +Fixes: f8946e2b6bb2 ("drm/mediatek: Add display MDP RDMA support for MT8195") + +Reviewed-by: CK Hu +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Hsiao Chien Sung +Link: https://patchwork.kernel.org/project/dri-devel/patch/20231214055847.4936-21-shawn.sung@mediatek.com/ +Signed-off-by: Chun-Kuang Hu +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c +index eecfa98ff52e..b288bb6eeecc 100644 +--- a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c ++++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c +@@ -223,8 +223,7 @@ int mtk_mdp_rdma_clk_enable(struct device *dev) + { + struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev); + +- clk_prepare_enable(rdma->clk); +- return 0; ++ return clk_prepare_enable(rdma->clk); + } + + void mtk_mdp_rdma_clk_disable(struct device *dev) +-- +2.43.0 + diff --git a/queue-6.1/drm-msm-dpu-drop-enable-and-frame_count-parameters-f.patch b/queue-6.1/drm-msm-dpu-drop-enable-and-frame_count-parameters-f.patch new file mode 100644 index 00000000000..c34b4dcbe57 --- /dev/null +++ b/queue-6.1/drm-msm-dpu-drop-enable-and-frame_count-parameters-f.patch @@ -0,0 +1,246 @@ +From 3c7061016d2e637eb9c1b28f98a44d70d30af6e6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 13 Dec 2023 13:30:18 -0800 +Subject: drm/msm/dpu: Drop enable and frame_count parameters from + dpu_hw_setup_misr() + +From: Jessica Zhang + +[ Upstream commit 3313c23f3eab698bc6b904520ee608fc0f7b03d0 ] + +Drop the enable and frame_count parameters from dpu_hw_setup_misr() as they +are always set to the same values. + +In addition, replace MISR_FRAME_COUNT_MASK with MISR_FRAME_COUNT as +frame_count is always set to the same value. + +Fixes: 7b37523fb1d1 ("drm/msm/dpu: Move MISR methods to dpu_hw_util") +Signed-off-by: Jessica Zhang +Reviewed-by: Abhinav Kumar +Reviewed-by: Dmitry Baryshkov +Patchwork: https://patchwork.freedesktop.org/patch/572009/ +Link: https://lore.kernel.org/r/20231213-encoder-fixup-v4-2-6da6cd1bf118@quicinc.com +Signed-off-by: Dmitry Baryshkov +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 ++-- + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 ++-- + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 6 +++--- + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 4 ++-- + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 6 +++--- + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 3 ++- + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 19 +++++-------------- + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 9 +++------ + 8 files changed, 22 insertions(+), 33 deletions(-) + +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +index 6c0ffe8e4adb..5a5821e59dc1 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +@@ -1,6 +1,6 @@ + // SPDX-License-Identifier: GPL-2.0-only + /* +- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved. + * Copyright (C) 2013 Red Hat + * Author: Rob Clark +@@ -124,7 +124,7 @@ static void dpu_crtc_setup_lm_misr(struct dpu_crtc_state *crtc_state) + continue; + + /* Calculate MISR over 1 frame */ +- m->hw_lm->ops.setup_misr(m->hw_lm, true, 1); ++ m->hw_lm->ops.setup_misr(m->hw_lm); + } + } + +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +index 547f9f2b9fcb..b0eb881f8af1 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +@@ -2,7 +2,7 @@ + /* + * Copyright (C) 2013 Red Hat + * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved. +- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Author: Rob Clark + */ +@@ -257,7 +257,7 @@ void dpu_encoder_setup_misr(const struct drm_encoder *drm_enc) + if (!phys->hw_intf || !phys->hw_intf->ops.setup_misr) + continue; + +- phys->hw_intf->ops.setup_misr(phys->hw_intf, true, 1); ++ phys->hw_intf->ops.setup_misr(phys->hw_intf); + } + } + +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +index 7e210ba0b104..384558d2f960 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +@@ -1,6 +1,6 @@ + // SPDX-License-Identifier: GPL-2.0-only + /* +- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. + */ + +@@ -322,9 +322,9 @@ static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf) + return DPU_REG_READ(c, INTF_LINE_COUNT); + } + +-static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf, bool enable, u32 frame_count) ++static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf) + { +- dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, enable, frame_count, 0x1); ++ dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, 0x1); + } + + static int dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf, u32 *misr_value) +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +index 643dd10bc030..e75339b96a1d 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +@@ -1,6 +1,6 @@ + /* SPDX-License-Identifier: GPL-2.0-only */ + /* +- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. + */ + +@@ -80,7 +80,7 @@ struct dpu_hw_intf_ops { + void (*bind_pingpong_blk)(struct dpu_hw_intf *intf, + bool enable, + const enum dpu_pingpong pp); +- void (*setup_misr)(struct dpu_hw_intf *intf, bool enable, u32 frame_count); ++ void (*setup_misr)(struct dpu_hw_intf *intf); + int (*collect_misr)(struct dpu_hw_intf *intf, u32 *misr_value); + }; + +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +index 2dd9f9185cfc..cc04fb979fb5 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +@@ -1,6 +1,6 @@ + // SPDX-License-Identifier: GPL-2.0-only + /* +- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. + */ + +@@ -99,9 +99,9 @@ static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx, + } + } + +-static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx, bool enable, u32 frame_count) ++static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx) + { +- dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, enable, frame_count, 0x0); ++ dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, 0x0); + } + + static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx, u32 *misr_value) +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h +index 652ddfdedec3..0a050eb247b9 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h +@@ -1,5 +1,6 @@ + /* SPDX-License-Identifier: GPL-2.0-only */ + /* ++ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. + */ + +@@ -57,7 +58,7 @@ struct dpu_hw_lm_ops { + /** + * setup_misr: Enable/disable MISR + */ +- void (*setup_misr)(struct dpu_hw_mixer *ctx, bool enable, u32 frame_count); ++ void (*setup_misr)(struct dpu_hw_mixer *ctx); + + /** + * collect_misr: Read MISR signature +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c +index 119dc07d6ab5..1b7439ae686a 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c +@@ -1,6 +1,6 @@ + // SPDX-License-Identifier: GPL-2.0-only + /* +- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. + */ + #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ +@@ -454,9 +454,7 @@ u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl, + * note: Aside from encoders, input_sel should be set to 0x0 by default + */ + void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c, +- u32 misr_ctrl_offset, +- bool enable, u32 frame_count, +- u8 input_sel) ++ u32 misr_ctrl_offset, u8 input_sel) + { + u32 config = 0; + +@@ -465,16 +463,9 @@ void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c, + /* Clear old MISR value (in case it's read before a new value is calculated)*/ + wmb(); + +- if (enable) { +- config = (frame_count & MISR_FRAME_COUNT_MASK) | +- MISR_CTRL_ENABLE | MISR_CTRL_FREE_RUN_MASK | +- ((input_sel & 0xF) << 24); +- +- DPU_REG_WRITE(c, misr_ctrl_offset, config); +- } else { +- DPU_REG_WRITE(c, misr_ctrl_offset, 0); +- } +- ++ config = MISR_FRAME_COUNT | MISR_CTRL_ENABLE | MISR_CTRL_FREE_RUN_MASK | ++ ((input_sel & 0xF) << 24); ++ DPU_REG_WRITE(c, misr_ctrl_offset, config); + } + + int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c, +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h +index dffad0a83781..4ae2a434372c 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h +@@ -1,6 +1,6 @@ + /* SPDX-License-Identifier: GPL-2.0-only */ + /* +- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. + */ + +@@ -13,7 +13,7 @@ + #include "dpu_hw_catalog.h" + + #define REG_MASK(n) ((BIT(n)) - 1) +-#define MISR_FRAME_COUNT_MASK 0xFF ++#define MISR_FRAME_COUNT 0x1 + #define MISR_CTRL_ENABLE BIT(8) + #define MISR_CTRL_STATUS BIT(9) + #define MISR_CTRL_STATUS_CLEAR BIT(10) +@@ -350,10 +350,7 @@ u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl, + u32 total_fl); + + void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c, +- u32 misr_ctrl_offset, +- bool enable, +- u32 frame_count, +- u8 input_sel); ++ u32 misr_ctrl_offset, u8 input_sel); + + int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c, + u32 misr_ctrl_offset, +-- +2.43.0 + diff --git a/queue-6.1/drm-msm-dpu-set-input_sel-bit-for-intf.patch b/queue-6.1/drm-msm-dpu-set-input_sel-bit-for-intf.patch new file mode 100644 index 00000000000..a64c32cfd90 --- /dev/null +++ b/queue-6.1/drm-msm-dpu-set-input_sel-bit-for-intf.patch @@ -0,0 +1,100 @@ +From 2f3a6a63046a1bfc11fb60d3e9efd3ef4046dcf2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 13 Dec 2023 13:30:17 -0800 +Subject: drm/msm/dpu: Set input_sel bit for INTF + +From: Jessica Zhang + +[ Upstream commit 980fffd0c69e5df0f67ee089d405899d532aeeab ] + +Set the input_sel bit for encoders as it was missed in the initial +implementation. + +Reported-by: Rob Clark +Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/39 +Fixes: 91143873a05d ("drm/msm/dpu: Add MISR register support for interface") +Signed-off-by: Jessica Zhang +Reviewed-by: Abhinav Kumar +Patchwork: https://patchwork.freedesktop.org/patch/572007/ +Link: https://lore.kernel.org/r/20231213-encoder-fixup-v4-1-6da6cd1bf118@quicinc.com +Signed-off-by: Dmitry Baryshkov +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 2 +- + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 2 +- + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 9 +++++++-- + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 3 ++- + 4 files changed, 11 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +index b9dddf576c02..7e210ba0b104 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +@@ -324,7 +324,7 @@ static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf) + + static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf, bool enable, u32 frame_count) + { +- dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, enable, frame_count); ++ dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, enable, frame_count, 0x1); + } + + static int dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf, u32 *misr_value) +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +index f5120ea91ede..2dd9f9185cfc 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +@@ -101,7 +101,7 @@ static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx, + + static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx, bool enable, u32 frame_count) + { +- dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, enable, frame_count); ++ dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, enable, frame_count, 0x0); + } + + static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx, u32 *misr_value) +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c +index 8062228eada6..119dc07d6ab5 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c +@@ -450,9 +450,13 @@ u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl, + return 0; + } + ++/* ++ * note: Aside from encoders, input_sel should be set to 0x0 by default ++ */ + void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c, + u32 misr_ctrl_offset, +- bool enable, u32 frame_count) ++ bool enable, u32 frame_count, ++ u8 input_sel) + { + u32 config = 0; + +@@ -463,7 +467,8 @@ void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c, + + if (enable) { + config = (frame_count & MISR_FRAME_COUNT_MASK) | +- MISR_CTRL_ENABLE | MISR_CTRL_FREE_RUN_MASK; ++ MISR_CTRL_ENABLE | MISR_CTRL_FREE_RUN_MASK | ++ ((input_sel & 0xF) << 24); + + DPU_REG_WRITE(c, misr_ctrl_offset, config); + } else { +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h +index 27f4c39e35ab..dffad0a83781 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h +@@ -352,7 +352,8 @@ u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl, + void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c, + u32 misr_ctrl_offset, + bool enable, +- u32 frame_count); ++ u32 frame_count, ++ u8 input_sel); + + int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c, + u32 misr_ctrl_offset, +-- +2.43.0 + diff --git a/queue-6.1/drm-msm-dsi-use-pm_runtime_resume_and_get-to-prevent.patch b/queue-6.1/drm-msm-dsi-use-pm_runtime_resume_and_get-to-prevent.patch new file mode 100644 index 00000000000..0210d5a6ab5 --- /dev/null +++ b/queue-6.1/drm-msm-dsi-use-pm_runtime_resume_and_get-to-prevent.patch @@ -0,0 +1,43 @@ +From 34b0007b25ec6b07de19466154bc8e5398a3986a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 20 Jun 2023 13:43:20 +0200 +Subject: drm/msm/dsi: Use pm_runtime_resume_and_get to prevent refcnt leaks + +From: Konrad Dybcio + +[ Upstream commit 3d07a411b4faaf2b498760ccf12888f8de529de0 ] + +This helper has been introduced to avoid programmer errors (missing +_put calls leading to dangling refcnt) when using pm_runtime_get, use it. + +While at it, start checking the return value. + +Signed-off-by: Konrad Dybcio +Reviewed-by: Dmitry Baryshkov +Fixes: 5c8290284402 ("drm/msm/dsi: Split PHY drivers to separate files") +Patchwork: https://patchwork.freedesktop.org/patch/543350/ +Link: https://lore.kernel.org/r/20230620-topic-dsiphy_rpm-v2-1-a11a751f34f0@linaro.org +Signed-off-by: Dmitry Baryshkov +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +index 7fc0975cb869..62bc3756f2e2 100644 +--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c ++++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +@@ -512,7 +512,9 @@ static int dsi_phy_enable_resource(struct msm_dsi_phy *phy) + struct device *dev = &phy->pdev->dev; + int ret; + +- pm_runtime_get_sync(dev); ++ ret = pm_runtime_resume_and_get(dev); ++ if (ret) ++ return ret; + + ret = clk_prepare_enable(phy->ahb_clk); + if (ret) { +-- +2.43.0 + diff --git a/queue-6.1/drm-msm-mdp4-flush-vblank-event-on-disable.patch b/queue-6.1/drm-msm-mdp4-flush-vblank-event-on-disable.patch new file mode 100644 index 00000000000..321e5a9d205 --- /dev/null +++ b/queue-6.1/drm-msm-mdp4-flush-vblank-event-on-disable.patch @@ -0,0 +1,53 @@ +From 376cd830d73dbfc8c52fdc6e50175b483e6e3446 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Nov 2023 00:54:01 +0300 +Subject: drm/msm/mdp4: flush vblank event on disable + +From: Dmitry Baryshkov + +[ Upstream commit c6721b3c6423d8a348ae885a0f4c85e14f9bf85c ] + +Flush queued events when disabling the crtc. This avoids timeouts when +we come back and wait for dependencies (like the previous frame's +flip_done). + +Fixes: c8afe684c95c ("drm/msm: basic KMS driver for snapdragon") +Signed-off-by: Dmitry Baryshkov +Reviewed-by: Abhinav Kumar +Patchwork: https://patchwork.freedesktop.org/patch/569127/ +Link: https://lore.kernel.org/r/20231127215401.4064128-1-dmitry.baryshkov@linaro.org +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c +index 169f9de4a12a..3100957225a7 100644 +--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c ++++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c +@@ -269,6 +269,7 @@ static void mdp4_crtc_atomic_disable(struct drm_crtc *crtc, + { + struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); + struct mdp4_kms *mdp4_kms = get_kms(crtc); ++ unsigned long flags; + + DBG("%s", mdp4_crtc->name); + +@@ -281,6 +282,14 @@ static void mdp4_crtc_atomic_disable(struct drm_crtc *crtc, + mdp_irq_unregister(&mdp4_kms->base, &mdp4_crtc->err); + mdp4_disable(mdp4_kms); + ++ if (crtc->state->event && !crtc->state->active) { ++ WARN_ON(mdp4_crtc->event); ++ spin_lock_irqsave(&mdp4_kms->dev->event_lock, flags); ++ drm_crtc_send_vblank_event(crtc, crtc->state->event); ++ crtc->state->event = NULL; ++ spin_unlock_irqrestore(&mdp4_kms->dev->event_lock, flags); ++ } ++ + mdp4_crtc->enabled = false; + } + +-- +2.43.0 + diff --git a/queue-6.1/drm-nouveau-fence-fix-warning-directly-dereferencing.patch b/queue-6.1/drm-nouveau-fence-fix-warning-directly-dereferencing.patch new file mode 100644 index 00000000000..fa458aaa214 --- /dev/null +++ b/queue-6.1/drm-nouveau-fence-fix-warning-directly-dereferencing.patch @@ -0,0 +1,58 @@ +From ea650db1d4e8514c1ae1690e3e4d117952ac9698 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 14 Nov 2023 00:43:03 +0530 +Subject: drm/nouveau/fence:: fix warning directly dereferencing a rcu pointer + +From: Abhinav Singh + +[ Upstream commit 5f35a624c1e30b5bae5023b3c256e94e0ad4f806 ] + +Fix a sparse warning with this message +"warning:dereference of noderef expression". In this context it means we +are dereferencing a __rcu tagged pointer directly. + +We should not be directly dereferencing a rcu pointer. To get a normal +(non __rcu tagged pointer) from a __rcu tagged pointer we are using the +function unrcu_pointer(...). The non __rcu tagged pointer then can be +dereferenced just like a normal pointer. + +I tested with qemu with this command +qemu-system-x86_64 \ + -m 2G \ + -smp 2 \ + -kernel bzImage \ + -append "console=ttyS0 root=/dev/sda earlyprintk=serial net.ifnames=0" \ + -drive file=bullseye.img,format=raw \ + -net user,host=10.0.2.10,hostfwd=tcp:127.0.0.1:10021-:22 \ + -net nic,model=e1000 \ + -enable-kvm \ + -nographic \ + -pidfile vm.pid \ + 2>&1 | tee vm.log +with lockdep enabled. + +Fixes: 0ec5f02f0e2c ("drm/nouveau: prevent stale fence->channel pointers, and protect with rcu") +Signed-off-by: Abhinav Singh +Signed-off-by: Danilo Krummrich +Link: https://patchwork.freedesktop.org/patch/msgid/20231113191303.3277733-1-singhabhinav9051571833@gmail.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/nouveau/nv04_fence.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/nouveau/nv04_fence.c b/drivers/gpu/drm/nouveau/nv04_fence.c +index 5b71a5a5cd85..cdbc75e3d1f6 100644 +--- a/drivers/gpu/drm/nouveau/nv04_fence.c ++++ b/drivers/gpu/drm/nouveau/nv04_fence.c +@@ -39,7 +39,7 @@ struct nv04_fence_priv { + static int + nv04_fence_emit(struct nouveau_fence *fence) + { +- struct nvif_push *push = fence->channel->chan.push; ++ struct nvif_push *push = unrcu_pointer(fence->channel)->chan.push; + int ret = PUSH_WAIT(push, 2); + if (ret == 0) { + PUSH_NVSQ(push, NV_SW, 0x0150, fence->base.seqno); +-- +2.43.0 + diff --git a/queue-6.1/drm-panel-elida-kd35t133-hold-panel-in-reset-for-unp.patch b/queue-6.1/drm-panel-elida-kd35t133-hold-panel-in-reset-for-unp.patch new file mode 100644 index 00000000000..562bf877adf --- /dev/null +++ b/queue-6.1/drm-panel-elida-kd35t133-hold-panel-in-reset-for-unp.patch @@ -0,0 +1,42 @@ +From c26d90e0cbbb5bcb96ce7f82e04b43e3e23bb8a0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 17 Nov 2023 13:44:02 -0600 +Subject: drm/panel-elida-kd35t133: hold panel in reset for unprepare + +From: Chris Morgan + +[ Upstream commit 03c5b2a5f6c39fe4e090346536cf1c14ee18b61e ] + +For devices like the Anbernic RG351M and RG351P the panel is wired to +an always on regulator. When the device suspends and wakes up, there +are some slight artifacts on the screen that go away over time. If +instead we hold the panel in reset status after it is unprepared, +this does not happen. + +Fixes: 5b6603360c12 ("drm/panel: add panel driver for Elida KD35T133 panels") +Signed-off-by: Chris Morgan +Reviewed-by: Jessica Zhang +Link: https://lore.kernel.org/r/20231117194405.1386265-3-macroalpha82@gmail.com +Signed-off-by: Neil Armstrong +Link: https://patchwork.freedesktop.org/patch/msgid/20231117194405.1386265-3-macroalpha82@gmail.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/panel/panel-elida-kd35t133.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/gpu/drm/panel/panel-elida-kd35t133.c b/drivers/gpu/drm/panel/panel-elida-kd35t133.c +index eee714cf3f49..3a7fc3ca6a6f 100644 +--- a/drivers/gpu/drm/panel/panel-elida-kd35t133.c ++++ b/drivers/gpu/drm/panel/panel-elida-kd35t133.c +@@ -112,6 +112,8 @@ static int kd35t133_unprepare(struct drm_panel *panel) + return ret; + } + ++ gpiod_set_value_cansleep(ctx->reset_gpio, 1); ++ + regulator_disable(ctx->iovcc); + regulator_disable(ctx->vdd); + +-- +2.43.0 + diff --git a/queue-6.1/drm-panel-st7701-fix-avcl-calculation.patch b/queue-6.1/drm-panel-st7701-fix-avcl-calculation.patch new file mode 100644 index 00000000000..9681a6dc996 --- /dev/null +++ b/queue-6.1/drm-panel-st7701-fix-avcl-calculation.patch @@ -0,0 +1,46 @@ +From c665084149d2719deda5b726aef9c9c4fcd57d08 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 8 Dec 2023 09:48:45 -0600 +Subject: drm/panel: st7701: Fix AVCL calculation + +From: Chris Morgan + +[ Upstream commit 799825aa87200ade1ba21db853d1c2ff720dcfe0 ] + +The AVCL register, according to the datasheet, comes in increments +of -0.2v between -4.4v (represented by 0x0) to -5.0v (represented +by 0x3). The current calculation is done by adding the defined +AVCL value in mV to -4400 and then dividing by 200 to get the register +value. Unfortunately if I subtract -4400 from -4400 I get -8800, which +divided by 200 gives me -44. If I instead subtract -4400 from -4400 +I get 0, which divided by 200 gives me 0. Based on the datasheet this +is the expected register value. + +Fixes: 83b7a8e7e88e ("drm/panel/panel-sitronix-st7701: Parametrize voltage and timing") + +Signed-off-by: Chris Morgan +Reviewed-by: Neil Armstrong +Link: https://lore.kernel.org/r/20231208154847.130615-2-macroalpha82@gmail.com +Signed-off-by: Neil Armstrong +Link: https://patchwork.freedesktop.org/patch/msgid/20231208154847.130615-2-macroalpha82@gmail.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/panel/panel-sitronix-st7701.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7701.c b/drivers/gpu/drm/panel/panel-sitronix-st7701.c +index 225b9884f61a..54b28992db5d 100644 +--- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c ++++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c +@@ -288,7 +288,7 @@ static void st7701_init_sequence(struct st7701 *st7701) + FIELD_PREP(DSI_CMD2_BK1_PWRCTRL2_AVDD_MASK, + DIV_ROUND_CLOSEST(desc->avdd_mv - 6200, 200)) | + FIELD_PREP(DSI_CMD2_BK1_PWRCTRL2_AVCL_MASK, +- DIV_ROUND_CLOSEST(-4400 + desc->avcl_mv, 200))); ++ DIV_ROUND_CLOSEST(-4400 - desc->avcl_mv, 200))); + + /* T2D = 0.2us * T2D[3:0] */ + ST7701_DSI(st7701, DSI_CMD2_BK1_SPD1, +-- +2.43.0 + diff --git a/queue-6.1/drm-panfrost-ignore-core_mask-for-poweroff-and-disab.patch b/queue-6.1/drm-panfrost-ignore-core_mask-for-poweroff-and-disab.patch new file mode 100644 index 00000000000..b3415465676 --- /dev/null +++ b/queue-6.1/drm-panfrost-ignore-core_mask-for-poweroff-and-disab.patch @@ -0,0 +1,84 @@ +From fd84ff8d45d779747bee37a71fae2786ecc90fe0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Dec 2023 12:42:13 +0100 +Subject: drm/panfrost: Ignore core_mask for poweroff and disable PWRTRANS irq + +From: AngeloGioacchino Del Regno + +[ Upstream commit a4f5892914ca7709ea6d191f0edace93a5935966 ] + +Some SoCs may be equipped with a GPU containing two core groups +and this is exactly the case of Samsung's Exynos 5422 featuring +an ARM Mali-T628 MP6 GPU: the support for this GPU in Panfrost +is partial, as this driver currently supports using only one +core group and that's reflected on all parts of it, including +the power on (and power off, previously to this patch) function. + +The issue with this is that even though executing the soft reset +operation should power off all cores unconditionally, on at least +one platform we're seeing a crash that seems to be happening due +to an interrupt firing which may be because we are calling power +transition only on the first core group, leaving the second one +unchanged, or because ISR execution was pending before entering +the panfrost_gpu_power_off() function and executed after powering +off the GPU cores, or all of the above. + +Finally, solve this by: + - Avoid to enable the power transition interrupt on reset; and + - Ignoring the core_mask and ask the GPU to poweroff both core groups + +Fixes: 22aa1a209018 ("drm/panfrost: Really power off GPU cores in panfrost_gpu_power_off()") +Reviewed-by: Boris Brezillon +Reviewed-by: Steven Price +Signed-off-by: AngeloGioacchino Del Regno +Tested-by: Marek Szyprowski +Signed-off-by: Boris Brezillon +Link: https://patchwork.freedesktop.org/patch/msgid/20231204114215.54575-2-angelogioacchino.delregno@collabora.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/panfrost/panfrost_gpu.c | 12 ++++++++---- + 1 file changed, 8 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panfrost/panfrost_gpu.c +index c08715f033c5..55d243048516 100644 +--- a/drivers/gpu/drm/panfrost/panfrost_gpu.c ++++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c +@@ -71,7 +71,12 @@ int panfrost_gpu_soft_reset(struct panfrost_device *pfdev) + } + + gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_MASK_ALL); +- gpu_write(pfdev, GPU_INT_MASK, GPU_IRQ_MASK_ALL); ++ ++ /* Only enable the interrupts we care about */ ++ gpu_write(pfdev, GPU_INT_MASK, ++ GPU_IRQ_MASK_ERROR | ++ GPU_IRQ_PERFCNT_SAMPLE_COMPLETED | ++ GPU_IRQ_CLEAN_CACHES_COMPLETED); + + return 0; + } +@@ -369,11 +374,10 @@ void panfrost_gpu_power_on(struct panfrost_device *pfdev) + + void panfrost_gpu_power_off(struct panfrost_device *pfdev) + { +- u64 core_mask = panfrost_get_core_mask(pfdev); + int ret; + u32 val; + +- gpu_write(pfdev, SHADER_PWROFF_LO, pfdev->features.shader_present & core_mask); ++ gpu_write(pfdev, SHADER_PWROFF_LO, pfdev->features.shader_present); + ret = readl_relaxed_poll_timeout(pfdev->iomem + SHADER_PWRTRANS_LO, + val, !val, 1, 1000); + if (ret) +@@ -385,7 +389,7 @@ void panfrost_gpu_power_off(struct panfrost_device *pfdev) + if (ret) + dev_err(pfdev->dev, "tiler power transition timeout"); + +- gpu_write(pfdev, L2_PWROFF_LO, pfdev->features.l2_present & core_mask); ++ gpu_write(pfdev, L2_PWROFF_LO, pfdev->features.l2_present); + ret = readl_poll_timeout(pfdev->iomem + L2_PWRTRANS_LO, + val, !val, 0, 1000); + if (ret) +-- +2.43.0 + diff --git a/queue-6.1/drm-panfrost-really-power-off-gpu-cores-in-panfrost_.patch b/queue-6.1/drm-panfrost-really-power-off-gpu-cores-in-panfrost_.patch new file mode 100644 index 00000000000..59138dcc48d --- /dev/null +++ b/queue-6.1/drm-panfrost-really-power-off-gpu-cores-in-panfrost_.patch @@ -0,0 +1,127 @@ +From e43d52760aa6b2926a18f38f9135819cad5fa2f7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 2 Nov 2023 15:15:07 +0100 +Subject: drm/panfrost: Really power off GPU cores in panfrost_gpu_power_off() + +From: AngeloGioacchino Del Regno + +[ Upstream commit 22aa1a209018dc2eca78745f7666db63637cd5dc ] + +The layout of the registers {TILER,SHADER,L2}_PWROFF_LO, used to request +powering off cores, is the same as the {TILER,SHADER,L2}_PWRON_LO ones: +this means that in order to request poweroff of cores, we are supposed +to write a bitmask of cores that should be powered off! +This means that the panfrost_gpu_power_off() function has always been +doing nothing. + +Fix powering off the GPU by writing a bitmask of the cores to poweroff +to the relevant PWROFF_LO registers and then check that the transition +(from ON to OFF) has finished by polling the relevant PWRTRANS_LO +registers. + +While at it, in order to avoid code duplication, move the core mask +logic from panfrost_gpu_power_on() to a new panfrost_get_core_mask() +function, used in both poweron and poweroff. + +Fixes: f3ba91228e8e ("drm/panfrost: Add initial panfrost driver") +Signed-off-by: AngeloGioacchino Del Regno +Reviewed-by: Steven Price +Signed-off-by: Steven Price +Link: https://patchwork.freedesktop.org/patch/msgid/20231102141507.73481-1-angelogioacchino.delregno@collabora.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/panfrost/panfrost_gpu.c | 64 ++++++++++++++++++------- + 1 file changed, 46 insertions(+), 18 deletions(-) + +diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panfrost/panfrost_gpu.c +index 6452e4e900dd..c08715f033c5 100644 +--- a/drivers/gpu/drm/panfrost/panfrost_gpu.c ++++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c +@@ -313,28 +313,38 @@ static void panfrost_gpu_init_features(struct panfrost_device *pfdev) + pfdev->features.shader_present, pfdev->features.l2_present); + } + ++static u64 panfrost_get_core_mask(struct panfrost_device *pfdev) ++{ ++ u64 core_mask; ++ ++ if (pfdev->features.l2_present == 1) ++ return U64_MAX; ++ ++ /* ++ * Only support one core group now. ++ * ~(l2_present - 1) unsets all bits in l2_present except ++ * the bottom bit. (l2_present - 2) has all the bits in ++ * the first core group set. AND them together to generate ++ * a mask of cores in the first core group. ++ */ ++ core_mask = ~(pfdev->features.l2_present - 1) & ++ (pfdev->features.l2_present - 2); ++ dev_info_once(pfdev->dev, "using only 1st core group (%lu cores from %lu)\n", ++ hweight64(core_mask), ++ hweight64(pfdev->features.shader_present)); ++ ++ return core_mask; ++} ++ + void panfrost_gpu_power_on(struct panfrost_device *pfdev) + { + int ret; + u32 val; +- u64 core_mask = U64_MAX; ++ u64 core_mask; + + panfrost_gpu_init_quirks(pfdev); ++ core_mask = panfrost_get_core_mask(pfdev); + +- if (pfdev->features.l2_present != 1) { +- /* +- * Only support one core group now. +- * ~(l2_present - 1) unsets all bits in l2_present except +- * the bottom bit. (l2_present - 2) has all the bits in +- * the first core group set. AND them together to generate +- * a mask of cores in the first core group. +- */ +- core_mask = ~(pfdev->features.l2_present - 1) & +- (pfdev->features.l2_present - 2); +- dev_info_once(pfdev->dev, "using only 1st core group (%lu cores from %lu)\n", +- hweight64(core_mask), +- hweight64(pfdev->features.shader_present)); +- } + gpu_write(pfdev, L2_PWRON_LO, pfdev->features.l2_present & core_mask); + ret = readl_relaxed_poll_timeout(pfdev->iomem + L2_READY_LO, + val, val == (pfdev->features.l2_present & core_mask), +@@ -359,9 +369,27 @@ void panfrost_gpu_power_on(struct panfrost_device *pfdev) + + void panfrost_gpu_power_off(struct panfrost_device *pfdev) + { +- gpu_write(pfdev, TILER_PWROFF_LO, 0); +- gpu_write(pfdev, SHADER_PWROFF_LO, 0); +- gpu_write(pfdev, L2_PWROFF_LO, 0); ++ u64 core_mask = panfrost_get_core_mask(pfdev); ++ int ret; ++ u32 val; ++ ++ gpu_write(pfdev, SHADER_PWROFF_LO, pfdev->features.shader_present & core_mask); ++ ret = readl_relaxed_poll_timeout(pfdev->iomem + SHADER_PWRTRANS_LO, ++ val, !val, 1, 1000); ++ if (ret) ++ dev_err(pfdev->dev, "shader power transition timeout"); ++ ++ gpu_write(pfdev, TILER_PWROFF_LO, pfdev->features.tiler_present); ++ ret = readl_relaxed_poll_timeout(pfdev->iomem + TILER_PWRTRANS_LO, ++ val, !val, 1, 1000); ++ if (ret) ++ dev_err(pfdev->dev, "tiler power transition timeout"); ++ ++ gpu_write(pfdev, L2_PWROFF_LO, pfdev->features.l2_present & core_mask); ++ ret = readl_poll_timeout(pfdev->iomem + L2_PWRTRANS_LO, ++ val, !val, 0, 1000); ++ if (ret) ++ dev_err(pfdev->dev, "l2 power transition timeout"); + } + + int panfrost_gpu_init(struct panfrost_device *pfdev) +-- +2.43.0 + diff --git a/queue-6.1/drm-radeon-check-return-value-of-radeon_ring_lock.patch b/queue-6.1/drm-radeon-check-return-value-of-radeon_ring_lock.patch new file mode 100644 index 00000000000..db116989376 --- /dev/null +++ b/queue-6.1/drm-radeon-check-return-value-of-radeon_ring_lock.patch @@ -0,0 +1,42 @@ +From 8151a5cd114a20ab83387df476fcd98bbd212978 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 8 Aug 2023 11:04:16 -0700 +Subject: drm/radeon: check return value of radeon_ring_lock() + +From: Nikita Zhandarovich + +[ Upstream commit 71225e1c930942cb1e042fc08c5cc0c4ef30e95e ] + +In the unlikely event of radeon_ring_lock() failing, its errno return +value should be processed. This patch checks said return value and +prints a debug message in case of an error. + +Found by Linux Verification Center (linuxtesting.org) with static +analysis tool SVACE. + +Fixes: 48c0c902e2e6 ("drm/radeon/kms: add support for CP setup on SI") +Signed-off-by: Nikita Zhandarovich +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/radeon/si.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c +index a91012447b56..85e9cba49cec 100644 +--- a/drivers/gpu/drm/radeon/si.c ++++ b/drivers/gpu/drm/radeon/si.c +@@ -3611,6 +3611,10 @@ static int si_cp_start(struct radeon_device *rdev) + for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) { + ring = &rdev->ring[i]; + r = radeon_ring_lock(rdev, ring, 2); ++ if (r) { ++ DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); ++ return r; ++ } + + /* clear the compute context state */ + radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0)); +-- +2.43.0 + diff --git a/queue-6.1/drm-radeon-check-the-alloc_workqueue-return-value-in.patch b/queue-6.1/drm-radeon-check-the-alloc_workqueue-return-value-in.patch new file mode 100644 index 00000000000..ebcb2271993 --- /dev/null +++ b/queue-6.1/drm-radeon-check-the-alloc_workqueue-return-value-in.patch @@ -0,0 +1,46 @@ +From d5cbb1e84a7f08b36f2c9bf632684d260ec0da8b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 30 Nov 2023 15:50:16 +0800 +Subject: drm/radeon: check the alloc_workqueue return value in + radeon_crtc_init() + +From: Yang Yingliang + +[ Upstream commit 7a2464fac80d42f6f8819fed97a553e9c2f43310 ] + +check the alloc_workqueue return value in radeon_crtc_init() +to avoid null-ptr-deref. + +Fixes: fa7f517cb26e ("drm/radeon: rework page flip handling v4") +Signed-off-by: Yang Yingliang +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/radeon/radeon_display.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c +index ca5598ae8bfc..1814bb8e14f1 100644 +--- a/drivers/gpu/drm/radeon/radeon_display.c ++++ b/drivers/gpu/drm/radeon/radeon_display.c +@@ -687,11 +687,16 @@ static void radeon_crtc_init(struct drm_device *dev, int index) + if (radeon_crtc == NULL) + return; + ++ radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0); ++ if (!radeon_crtc->flip_queue) { ++ kfree(radeon_crtc); ++ return; ++ } ++ + drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); + + drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); + radeon_crtc->crtc_id = index; +- radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0); + rdev->mode_info.crtcs[index] = radeon_crtc; + + if (rdev->family >= CHIP_BONAIRE) { +-- +2.43.0 + diff --git a/queue-6.1/drm-radeon-dpm-fix-a-memleak-in-sumo_parse_power_tab.patch b/queue-6.1/drm-radeon-dpm-fix-a-memleak-in-sumo_parse_power_tab.patch new file mode 100644 index 00000000000..99bef02cd80 --- /dev/null +++ b/queue-6.1/drm-radeon-dpm-fix-a-memleak-in-sumo_parse_power_tab.patch @@ -0,0 +1,41 @@ +From 1cce30d04f7e1f7b000afc59def7cd3ed307894d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Dec 2023 16:57:56 +0800 +Subject: drm/radeon/dpm: fix a memleak in sumo_parse_power_table + +From: Zhipeng Lu + +[ Upstream commit 0737df9ed0997f5b8addd6e2b9699a8c6edba2e4 ] + +The rdev->pm.dpm.ps allocated by kcalloc should be freed in every +following error-handling path. However, in the error-handling of +rdev->pm.power_state[i].clock_info the rdev->pm.dpm.ps is not freed, +resulting in a memleak in this function. + +Fixes: 80ea2c129c76 ("drm/radeon/kms: add dpm support for sumo asics (v2)") +Signed-off-by: Zhipeng Lu +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/radeon/sumo_dpm.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c b/drivers/gpu/drm/radeon/sumo_dpm.c +index f74f381af05f..d49c145db437 100644 +--- a/drivers/gpu/drm/radeon/sumo_dpm.c ++++ b/drivers/gpu/drm/radeon/sumo_dpm.c +@@ -1493,8 +1493,10 @@ static int sumo_parse_power_table(struct radeon_device *rdev) + non_clock_array_index = power_state->v2.nonClockInfoIndex; + non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) + &non_clock_info_array->nonClockInfo[non_clock_array_index]; +- if (!rdev->pm.power_state[i].clock_info) ++ if (!rdev->pm.power_state[i].clock_info) { ++ kfree(rdev->pm.dpm.ps); + return -EINVAL; ++ } + ps = kzalloc(sizeof(struct sumo_ps), GFP_KERNEL); + if (ps == NULL) { + kfree(rdev->pm.dpm.ps); +-- +2.43.0 + diff --git a/queue-6.1/drm-radeon-r100-fix-integer-overflow-issues-in-r100_.patch b/queue-6.1/drm-radeon-r100-fix-integer-overflow-issues-in-r100_.patch new file mode 100644 index 00000000000..787ffcdb75b --- /dev/null +++ b/queue-6.1/drm-radeon-r100-fix-integer-overflow-issues-in-r100_.patch @@ -0,0 +1,52 @@ +From 4187ca50829c07b24f826284d67a379e354ad88c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 29 Nov 2023 07:22:12 -0800 +Subject: drm/radeon/r100: Fix integer overflow issues in r100_cs_track_check() + +From: Nikita Zhandarovich + +[ Upstream commit b5c5baa458faa5430c445acd9a17481274d77ccf ] + +It may be possible, albeit unlikely, to encounter integer overflow +during the multiplication of several unsigned int variables, the +result being assigned to a variable 'size' of wider type. + +Prevent this potential behaviour by converting one of the multiples +to unsigned long. + +Found by Linux Verification Center (linuxtesting.org) with static +analysis tool SVACE. + +Fixes: 0242f74d29df ("drm/radeon: clean up CS functions in r100.c") +Signed-off-by: Nikita Zhandarovich +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/radeon/r100.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c +index d4f09ecc3d22..f336b5b3b11f 100644 +--- a/drivers/gpu/drm/radeon/r100.c ++++ b/drivers/gpu/drm/radeon/r100.c +@@ -2321,7 +2321,7 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) + switch (prim_walk) { + case 1: + for (i = 0; i < track->num_arrays; i++) { +- size = track->arrays[i].esize * track->max_indx * 4; ++ size = track->arrays[i].esize * track->max_indx * 4UL; + if (track->arrays[i].robj == NULL) { + DRM_ERROR("(PW %u) Vertex array %u no buffer " + "bound\n", prim_walk, i); +@@ -2340,7 +2340,7 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) + break; + case 2: + for (i = 0; i < track->num_arrays; i++) { +- size = track->arrays[i].esize * (nverts - 1) * 4; ++ size = track->arrays[i].esize * (nverts - 1) * 4UL; + if (track->arrays[i].robj == NULL) { + DRM_ERROR("(PW %u) Vertex array %u no buffer " + "bound\n", prim_walk, i); +-- +2.43.0 + diff --git a/queue-6.1/drm-radeon-r600_cs-fix-possible-int-overflows-in-r60.patch b/queue-6.1/drm-radeon-r600_cs-fix-possible-int-overflows-in-r60.patch new file mode 100644 index 00000000000..de1aada97c0 --- /dev/null +++ b/queue-6.1/drm-radeon-r600_cs-fix-possible-int-overflows-in-r60.patch @@ -0,0 +1,51 @@ +From c732ebedba9181eed30013b1091831f28a53fe8f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 29 Nov 2023 07:22:30 -0800 +Subject: drm/radeon/r600_cs: Fix possible int overflows in r600_cs_check_reg() + +From: Nikita Zhandarovich + +[ Upstream commit 39c960bbf9d9ea862398759e75736cfb68c3446f ] + +While improbable, there may be a chance of hitting integer +overflow when the result of radeon_get_ib_value() gets shifted +left. + +Avoid it by casting one of the operands to larger data type (u64). + +Found by Linux Verification Center (linuxtesting.org) with static +analysis tool SVACE. + +Fixes: 1729dd33d20b ("drm/radeon/kms: r600 CS parser fixes") +Signed-off-by: Nikita Zhandarovich +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/radeon/r600_cs.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c +index 638f861af80f..6cf54a747749 100644 +--- a/drivers/gpu/drm/radeon/r600_cs.c ++++ b/drivers/gpu/drm/radeon/r600_cs.c +@@ -1275,7 +1275,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) + return -EINVAL; + } + tmp = (reg - CB_COLOR0_BASE) / 4; +- track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; ++ track->cb_color_bo_offset[tmp] = (u64)radeon_get_ib_value(p, idx) << 8; + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); + track->cb_color_base_last[tmp] = ib[idx]; + track->cb_color_bo[tmp] = reloc->robj; +@@ -1302,7 +1302,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) + "0x%04X\n", reg); + return -EINVAL; + } +- track->htile_offset = radeon_get_ib_value(p, idx) << 8; ++ track->htile_offset = (u64)radeon_get_ib_value(p, idx) << 8; + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); + track->htile_bo = reloc->robj; + track->db_dirty = true; +-- +2.43.0 + diff --git a/queue-6.1/drm-radeon-trinity_dpm-fix-a-memleak-in-trinity_pars.patch b/queue-6.1/drm-radeon-trinity_dpm-fix-a-memleak-in-trinity_pars.patch new file mode 100644 index 00000000000..d36cd4a2e80 --- /dev/null +++ b/queue-6.1/drm-radeon-trinity_dpm-fix-a-memleak-in-trinity_pars.patch @@ -0,0 +1,41 @@ +From b9ce290126ef51c8722a0e7a807d0df5d385e0ad Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Dec 2023 18:21:54 +0800 +Subject: drm/radeon/trinity_dpm: fix a memleak in trinity_parse_power_table + +From: Zhipeng Lu + +[ Upstream commit 28c28d7f77c06ac2c0b8f9c82bc04eba22912b3b ] + +The rdev->pm.dpm.ps allocated by kcalloc should be freed in every +following error-handling path. However, in the error-handling of +rdev->pm.power_state[i].clock_info the rdev->pm.dpm.ps is not freed, +resulting in a memleak in this function. + +Fixes: d70229f70447 ("drm/radeon/kms: add dpm support for trinity asics") +Signed-off-by: Zhipeng Lu +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/radeon/trinity_dpm.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/radeon/trinity_dpm.c b/drivers/gpu/drm/radeon/trinity_dpm.c +index 08ea1c864cb2..ef1cc7bad20a 100644 +--- a/drivers/gpu/drm/radeon/trinity_dpm.c ++++ b/drivers/gpu/drm/radeon/trinity_dpm.c +@@ -1726,8 +1726,10 @@ static int trinity_parse_power_table(struct radeon_device *rdev) + non_clock_array_index = power_state->v2.nonClockInfoIndex; + non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) + &non_clock_info_array->nonClockInfo[non_clock_array_index]; +- if (!rdev->pm.power_state[i].clock_info) ++ if (!rdev->pm.power_state[i].clock_info) { ++ kfree(rdev->pm.dpm.ps); + return -EINVAL; ++ } + ps = kzalloc(sizeof(struct sumo_ps), GFP_KERNEL); + if (ps == NULL) { + kfree(rdev->pm.dpm.ps); +-- +2.43.0 + diff --git a/queue-6.1/drm-tidss-check-for-k2g-in-in-dispc_softreset.patch b/queue-6.1/drm-tidss-check-for-k2g-in-in-dispc_softreset.patch new file mode 100644 index 00000000000..2ca85c650b2 --- /dev/null +++ b/queue-6.1/drm-tidss-check-for-k2g-in-in-dispc_softreset.patch @@ -0,0 +1,57 @@ +From 97b187483c18e07b971e5f27de52e3a8073d7758 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 9 Nov 2023 09:37:59 +0200 +Subject: drm/tidss: Check for K2G in in dispc_softreset() + +From: Tomi Valkeinen + +[ Upstream commit 151825150cf9c2e9fb90763d35b9dff3783628ac ] + +K2G doesn't have softreset feature. Instead of having every caller of +dispc_softreset() check for K2G, move the check into dispc_softreset(), +and make dispc_softreset() return 0 in case of K2G. + +Reviewed-by: Laurent Pinchart +Reviewed-by: Aradhya Bhatia +Link: https://lore.kernel.org/r/20231109-tidss-probe-v2-6-ac91b5ea35c0@ideasonboard.com +Signed-off-by: Tomi Valkeinen +Stable-dep-of: bc288a927815 ("drm/tidss: Fix dss reset") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/tidss/tidss_dispc.c | 13 +++++++------ + 1 file changed, 7 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c +index 591f0606f7f8..4bdd4c7b4991 100644 +--- a/drivers/gpu/drm/tidss/tidss_dispc.c ++++ b/drivers/gpu/drm/tidss/tidss_dispc.c +@@ -2658,6 +2658,10 @@ static int dispc_softreset(struct dispc_device *dispc) + u32 val; + int ret = 0; + ++ /* K2G display controller does not support soft reset */ ++ if (dispc->feat->subrev == DISPC_K2G) ++ return 0; ++ + /* Soft reset */ + REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, 1, 1); + /* Wait for reset to complete */ +@@ -2778,12 +2782,9 @@ int dispc_init(struct tidss_device *tidss) + of_property_read_u32(dispc->dev->of_node, "max-memory-bandwidth", + &dispc->memory_bandwidth_limit); + +- /* K2G display controller does not support soft reset */ +- if (feat->subrev != DISPC_K2G) { +- r = dispc_softreset(dispc); +- if (r) +- return r; +- } ++ r = dispc_softreset(dispc); ++ if (r) ++ return r; + + tidss->dispc = dispc; + +-- +2.43.0 + diff --git a/queue-6.1/drm-tidss-fix-dss-reset.patch b/queue-6.1/drm-tidss-fix-dss-reset.patch new file mode 100644 index 00000000000..a618c54c660 --- /dev/null +++ b/queue-6.1/drm-tidss-fix-dss-reset.patch @@ -0,0 +1,106 @@ +From 5a0495490066e05b9caa7dbd9c3d44c6df27ae3e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 9 Nov 2023 09:38:01 +0200 +Subject: drm/tidss: Fix dss reset + +From: Tomi Valkeinen + +[ Upstream commit bc288a927815efcf9d7f4a54d4d89c5df478c635 ] + +The probe function calls dispc_softreset() before runtime PM is enabled +and without enabling any of the DSS clocks. This happens to work by +luck, and we need to make sure the DSS HW is active and the fclk is +enabled. + +To fix the above, add a new function, dispc_init_hw(), which does: + +- pm_runtime_set_active() +- clk_prepare_enable(fclk) +- dispc_softreset(). + +This ensures that the reset can be successfully accomplished. + +Note that we use pm_runtime_set_active(), not the normal +pm_runtime_get(). The reason for this is that at this point we haven't +enabled the runtime PM yet and also we don't want the normal resume +callback to be called: the dispc resume callback does some initial HW +setup, and it expects that the HW was off (no video ports are +streaming). If the bootloader has enabled the DSS and has set up a +boot time splash-screen, the DSS would be enabled and streaming which +might lead to issues with the normal resume callback. + +Fixes: c9b2d923befd ("drm/tidss: Soft Reset DISPC on startup") +Reviewed-by: Aradhya Bhatia +Link: https://lore.kernel.org/r/20231109-tidss-probe-v2-8-ac91b5ea35c0@ideasonboard.com +Signed-off-by: Tomi Valkeinen +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/tidss/tidss_dispc.c | 45 ++++++++++++++++++++++++++++- + 1 file changed, 44 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c +index 4bdd4c7b4991..95b75236fe5e 100644 +--- a/drivers/gpu/drm/tidss/tidss_dispc.c ++++ b/drivers/gpu/drm/tidss/tidss_dispc.c +@@ -2675,6 +2675,49 @@ static int dispc_softreset(struct dispc_device *dispc) + return 0; + } + ++static int dispc_init_hw(struct dispc_device *dispc) ++{ ++ struct device *dev = dispc->dev; ++ int ret; ++ ++ ret = pm_runtime_set_active(dev); ++ if (ret) { ++ dev_err(dev, "Failed to set DSS PM to active\n"); ++ return ret; ++ } ++ ++ ret = clk_prepare_enable(dispc->fclk); ++ if (ret) { ++ dev_err(dev, "Failed to enable DSS fclk\n"); ++ goto err_runtime_suspend; ++ } ++ ++ ret = dispc_softreset(dispc); ++ if (ret) ++ goto err_clk_disable; ++ ++ clk_disable_unprepare(dispc->fclk); ++ ret = pm_runtime_set_suspended(dev); ++ if (ret) { ++ dev_err(dev, "Failed to set DSS PM to suspended\n"); ++ return ret; ++ } ++ ++ return 0; ++ ++err_clk_disable: ++ clk_disable_unprepare(dispc->fclk); ++ ++err_runtime_suspend: ++ ret = pm_runtime_set_suspended(dev); ++ if (ret) { ++ dev_err(dev, "Failed to set DSS PM to suspended\n"); ++ return ret; ++ } ++ ++ return ret; ++} ++ + int dispc_init(struct tidss_device *tidss) + { + struct device *dev = tidss->dev; +@@ -2782,7 +2825,7 @@ int dispc_init(struct tidss_device *tidss) + of_property_read_u32(dispc->dev->of_node, "max-memory-bandwidth", + &dispc->memory_bandwidth_limit); + +- r = dispc_softreset(dispc); ++ r = dispc_init_hw(dispc); + if (r) + return r; + +-- +2.43.0 + diff --git a/queue-6.1/drm-tidss-move-reset-to-the-end-of-dispc_init.patch b/queue-6.1/drm-tidss-move-reset-to-the-end-of-dispc_init.patch new file mode 100644 index 00000000000..47a56b94211 --- /dev/null +++ b/queue-6.1/drm-tidss-move-reset-to-the-end-of-dispc_init.patch @@ -0,0 +1,55 @@ +From b973165b2b3a8da5f3ee9c5569f37d27f44da06d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 9 Nov 2023 09:37:57 +0200 +Subject: drm/tidss: Move reset to the end of dispc_init() + +From: Tomi Valkeinen + +[ Upstream commit 36d1e0852680aa038e2428d450673390111b165c ] + +We do a DSS reset in the middle of the dispc_init(). While that happens +to work now, we should really make sure that e..g the fclk, which is +acquired only later in the function, is enabled when doing a reset. This +will be handled in a later patch, but for now, let's move the +dispc_softreset() call to the end of dispc_init(), which is a sensible +place for it anyway. + +Reviewed-by: Laurent Pinchart +Reviewed-by: Aradhya Bhatia +Link: https://lore.kernel.org/r/20231109-tidss-probe-v2-4-ac91b5ea35c0@ideasonboard.com +Signed-off-by: Tomi Valkeinen +Stable-dep-of: bc288a927815 ("drm/tidss: Fix dss reset") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/tidss/tidss_dispc.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c +index 16301bdfead1..9ce452288c9e 100644 +--- a/drivers/gpu/drm/tidss/tidss_dispc.c ++++ b/drivers/gpu/drm/tidss/tidss_dispc.c +@@ -2726,10 +2726,6 @@ int dispc_init(struct tidss_device *tidss) + return r; + } + +- /* K2G display controller does not support soft reset */ +- if (feat->subrev != DISPC_K2G) +- dispc_softreset(dispc); +- + for (i = 0; i < dispc->feat->num_vps; i++) { + u32 gamma_size = dispc->feat->vp_feat.color.gamma_size; + u32 *gamma_table; +@@ -2778,6 +2774,10 @@ int dispc_init(struct tidss_device *tidss) + of_property_read_u32(dispc->dev->of_node, "max-memory-bandwidth", + &dispc->memory_bandwidth_limit); + ++ /* K2G display controller does not support soft reset */ ++ if (feat->subrev != DISPC_K2G) ++ dispc_softreset(dispc); ++ + tidss->dispc = dispc; + + return 0; +-- +2.43.0 + diff --git a/queue-6.1/drm-tidss-return-error-value-from-from-softreset.patch b/queue-6.1/drm-tidss-return-error-value-from-from-softreset.patch new file mode 100644 index 00000000000..a2320b77817 --- /dev/null +++ b/queue-6.1/drm-tidss-return-error-value-from-from-softreset.patch @@ -0,0 +1,66 @@ +From f21a62e7fddb649c7de9c3a8aa0c572408c0233a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 9 Nov 2023 09:37:58 +0200 +Subject: drm/tidss: Return error value from from softreset + +From: Tomi Valkeinen + +[ Upstream commit aceafbb5035c4bfc75a321863ed1e393d644d2d2 ] + +Return an error value from dispc_softreset() so that the caller can +handle the errors. + +Reviewed-by: Aradhya Bhatia +Link: https://lore.kernel.org/r/20231109-tidss-probe-v2-5-ac91b5ea35c0@ideasonboard.com +Signed-off-by: Tomi Valkeinen +Stable-dep-of: bc288a927815 ("drm/tidss: Fix dss reset") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/tidss/tidss_dispc.c | 17 ++++++++++++----- + 1 file changed, 12 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c +index 9ce452288c9e..591f0606f7f8 100644 +--- a/drivers/gpu/drm/tidss/tidss_dispc.c ++++ b/drivers/gpu/drm/tidss/tidss_dispc.c +@@ -2653,7 +2653,7 @@ static void dispc_init_errata(struct dispc_device *dispc) + } + } + +-static void dispc_softreset(struct dispc_device *dispc) ++static int dispc_softreset(struct dispc_device *dispc) + { + u32 val; + int ret = 0; +@@ -2663,8 +2663,12 @@ static void dispc_softreset(struct dispc_device *dispc) + /* Wait for reset to complete */ + ret = readl_poll_timeout(dispc->base_common + DSS_SYSSTATUS, + val, val & 1, 100, 5000); +- if (ret) +- dev_warn(dispc->dev, "failed to reset dispc\n"); ++ if (ret) { ++ dev_err(dispc->dev, "failed to reset dispc\n"); ++ return ret; ++ } ++ ++ return 0; + } + + int dispc_init(struct tidss_device *tidss) +@@ -2775,8 +2779,11 @@ int dispc_init(struct tidss_device *tidss) + &dispc->memory_bandwidth_limit); + + /* K2G display controller does not support soft reset */ +- if (feat->subrev != DISPC_K2G) +- dispc_softreset(dispc); ++ if (feat->subrev != DISPC_K2G) { ++ r = dispc_softreset(dispc); ++ if (r) ++ return r; ++ } + + tidss->dispc = dispc; + +-- +2.43.0 + diff --git a/queue-6.1/drm-tilcdc-fix-irq-free-on-unload.patch b/queue-6.1/drm-tilcdc-fix-irq-free-on-unload.patch new file mode 100644 index 00000000000..b6aea8550db --- /dev/null +++ b/queue-6.1/drm-tilcdc-fix-irq-free-on-unload.patch @@ -0,0 +1,40 @@ +From 2c76bdb56cd6902796fd3b44f5db5f71868a2f27 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 19 Sep 2023 10:12:50 +0300 +Subject: drm/tilcdc: Fix irq free on unload + +From: Tomi Valkeinen + +[ Upstream commit 38360bf96d816e175bc602c4ee76953cd303b71d ] + +The driver only frees the reserved irq if priv->irq_enabled is set to +true. However, the driver mistakenly sets priv->irq_enabled to false, +instead of true, in tilcdc_irq_install(), and thus the driver never +frees the irq, causing issues on loading the driver a second time. + +Fixes: b6366814fa77 ("drm/tilcdc: Convert to Linux IRQ interfaces") +Cc: Thomas Zimmermann +Reviewed-by: Aradhya Bhatia +Signed-off-by: Tomi Valkeinen +Link: https://patchwork.freedesktop.org/patch/msgid/20230919-lcdc-v1-1-ba60da7421e1@ideasonboard.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/tilcdc/tilcdc_drv.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c b/drivers/gpu/drm/tilcdc/tilcdc_drv.c +index f72755b8ea14..86d34b77b37d 100644 +--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c ++++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c +@@ -138,7 +138,7 @@ static int tilcdc_irq_install(struct drm_device *dev, unsigned int irq) + if (ret) + return ret; + +- priv->irq_enabled = false; ++ priv->irq_enabled = true; + + return 0; + } +-- +2.43.0 + diff --git a/queue-6.1/dt-bindings-clock-update-the-videocc-resets-for-sm81.patch b/queue-6.1/dt-bindings-clock-update-the-videocc-resets-for-sm81.patch new file mode 100644 index 00000000000..07a09868c73 --- /dev/null +++ b/queue-6.1/dt-bindings-clock-update-the-videocc-resets-for-sm81.patch @@ -0,0 +1,40 @@ +From 3ceb5711636fd8a9d902f6836bcd55570f019ac9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 1 Dec 2023 15:20:24 +0530 +Subject: dt-bindings: clock: Update the videocc resets for sm8150 + +From: Satya Priya Kakitapalli + +[ Upstream commit 3185f96968eedd117ec72ee7b87ead44b6d1bbbd ] + +Add all the available resets for the video clock controller +on sm8150. + +Signed-off-by: Satya Priya Kakitapalli +Acked-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20231201-videocc-8150-v3-1-56bec3a5e443@quicinc.com +Signed-off-by: Bjorn Andersson +Stable-dep-of: 1fd9a939db24 ("clk: qcom: videocc-sm8150: Update the videocc resets") +Signed-off-by: Sasha Levin +--- + include/dt-bindings/clock/qcom,videocc-sm8150.h | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/include/dt-bindings/clock/qcom,videocc-sm8150.h b/include/dt-bindings/clock/qcom,videocc-sm8150.h +index e24ee840cfdb..c557b78dc572 100644 +--- a/include/dt-bindings/clock/qcom,videocc-sm8150.h ++++ b/include/dt-bindings/clock/qcom,videocc-sm8150.h +@@ -16,6 +16,10 @@ + + /* VIDEO_CC Resets */ + #define VIDEO_CC_MVSC_CORE_CLK_BCR 0 ++#define VIDEO_CC_INTERFACE_BCR 1 ++#define VIDEO_CC_MVS0_BCR 2 ++#define VIDEO_CC_MVS1_BCR 3 ++#define VIDEO_CC_MVSC_BCR 4 + + /* VIDEO_CC GDSCRs */ + #define VENUS_GDSC 0 +-- +2.43.0 + diff --git a/queue-6.1/dt-bindings-media-mediatek-mdp3-correct-rdma-and-wro.patch b/queue-6.1/dt-bindings-media-mediatek-mdp3-correct-rdma-and-wro.patch new file mode 100644 index 00000000000..7a534b92fe4 --- /dev/null +++ b/queue-6.1/dt-bindings-media-mediatek-mdp3-correct-rdma-and-wro.patch @@ -0,0 +1,125 @@ +From c562b166a229bc3acebb7c21da10be8b58876e3b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 31 Oct 2023 16:33:42 +0800 +Subject: dt-bindings: media: mediatek: mdp3: correct RDMA and WROT node with + generic names + +From: Moudy Ho + +[ Upstream commit f5f185bf7c42f6ca885202fefc40fc871d08a722 ] + +The DMA-related nodes RDMA/WROT in MDP3 should be changed to generic names. +In addition, fix improper space indent in example. + +Fixes: 4ad7b39623ab ("media: dt-binding: mediatek: add bindings for MediaTek MDP3 components") +Signed-off-by: Moudy Ho +Acked-by: Rob Herring +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: AngeloGioacchino Del Regno +Signed-off-by: Sasha Levin +--- + .../bindings/media/mediatek,mdp3-rdma.yaml | 29 +++++++++++-------- + .../bindings/media/mediatek,mdp3-wrot.yaml | 23 +++++++++------ + 2 files changed, 31 insertions(+), 21 deletions(-) + +diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml +index 9cfc0c7d23e0..46730687c662 100644 +--- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml ++++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml +@@ -61,6 +61,9 @@ properties: + - description: used for 1st data pipe from RDMA + - description: used for 2nd data pipe from RDMA + ++ '#dma-cells': ++ const: 1 ++ + required: + - compatible + - reg +@@ -70,6 +73,7 @@ required: + - clocks + - iommus + - mboxes ++ - '#dma-cells' + + additionalProperties: false + +@@ -80,16 +84,17 @@ examples: + #include + #include + +- mdp3_rdma0: mdp3-rdma0@14001000 { +- compatible = "mediatek,mt8183-mdp3-rdma"; +- reg = <0x14001000 0x1000>; +- mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; +- mediatek,gce-events = , +- ; +- power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; +- clocks = <&mmsys CLK_MM_MDP_RDMA0>, +- <&mmsys CLK_MM_MDP_RSZ1>; +- iommus = <&iommu>; +- mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>, +- <&gce 21 CMDQ_THR_PRIO_LOWEST>; ++ dma-controller@14001000 { ++ compatible = "mediatek,mt8183-mdp3-rdma"; ++ reg = <0x14001000 0x1000>; ++ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; ++ mediatek,gce-events = , ++ ; ++ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; ++ clocks = <&mmsys CLK_MM_MDP_RDMA0>, ++ <&mmsys CLK_MM_MDP_RSZ1>; ++ iommus = <&iommu>; ++ mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>, ++ <&gce 21 CMDQ_THR_PRIO_LOWEST>; ++ #dma-cells = <1>; + }; +diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml +index 0baa77198fa2..64ea98aa0592 100644 +--- a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml ++++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml +@@ -50,6 +50,9 @@ properties: + iommus: + maxItems: 1 + ++ '#dma-cells': ++ const: 1 ++ + required: + - compatible + - reg +@@ -58,6 +61,7 @@ required: + - power-domains + - clocks + - iommus ++ - '#dma-cells' + + additionalProperties: false + +@@ -68,13 +72,14 @@ examples: + #include + #include + +- mdp3_wrot0: mdp3-wrot0@14005000 { +- compatible = "mediatek,mt8183-mdp3-wrot"; +- reg = <0x14005000 0x1000>; +- mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; +- mediatek,gce-events = , +- ; +- power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; +- clocks = <&mmsys CLK_MM_MDP_WROT0>; +- iommus = <&iommu>; ++ dma-controller@14005000 { ++ compatible = "mediatek,mt8183-mdp3-wrot"; ++ reg = <0x14005000 0x1000>; ++ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; ++ mediatek,gce-events = , ++ ; ++ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; ++ clocks = <&mmsys CLK_MM_MDP_WROT0>; ++ iommus = <&iommu>; ++ #dma-cells = <1>; + }; +-- +2.43.0 + diff --git a/queue-6.1/edac-thunderx-fix-possible-out-of-bounds-string-acce.patch b/queue-6.1/edac-thunderx-fix-possible-out-of-bounds-string-acce.patch new file mode 100644 index 00000000000..47b3504d56c --- /dev/null +++ b/queue-6.1/edac-thunderx-fix-possible-out-of-bounds-string-acce.patch @@ -0,0 +1,91 @@ +From ab32c506485eedf3bd21621a404303fb0c812d08 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 22 Nov 2023 23:19:53 +0100 +Subject: EDAC/thunderx: Fix possible out-of-bounds string access + +From: Arnd Bergmann + +[ Upstream commit 475c58e1a471e9b873e3e39958c64a2d278275c8 ] + +Enabling -Wstringop-overflow globally exposes a warning for a common bug +in the usage of strncat(): + + drivers/edac/thunderx_edac.c: In function 'thunderx_ocx_com_threaded_isr': + drivers/edac/thunderx_edac.c:1136:17: error: 'strncat' specified bound 1024 equals destination size [-Werror=stringop-overflow=] + 1136 | strncat(msg, other, OCX_MESSAGE_SIZE); + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + ... + 1145 | strncat(msg, other, OCX_MESSAGE_SIZE); + ... + 1150 | strncat(msg, other, OCX_MESSAGE_SIZE); + + ... + +Apparently the author of this driver expected strncat() to behave the +way that strlcat() does, which uses the size of the destination buffer +as its third argument rather than the length of the source buffer. The +result is that there is no check on the size of the allocated buffer. + +Change it to strlcat(). + + [ bp: Trim compiler output, fixup commit message. ] + +Fixes: 41003396f932 ("EDAC, thunderx: Add Cavium ThunderX EDAC driver") +Signed-off-by: Arnd Bergmann +Signed-off-by: Borislav Petkov (AMD) +Reviewed-by: Gustavo A. R. Silva +Link: https://lore.kernel.org/r/20231122222007.3199885-1-arnd@kernel.org +Signed-off-by: Sasha Levin +--- + drivers/edac/thunderx_edac.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/drivers/edac/thunderx_edac.c b/drivers/edac/thunderx_edac.c +index f13674081cb6..4dca21b39bf7 100644 +--- a/drivers/edac/thunderx_edac.c ++++ b/drivers/edac/thunderx_edac.c +@@ -1133,7 +1133,7 @@ static irqreturn_t thunderx_ocx_com_threaded_isr(int irq, void *irq_id) + decode_register(other, OCX_OTHER_SIZE, + ocx_com_errors, ctx->reg_com_int); + +- strncat(msg, other, OCX_MESSAGE_SIZE); ++ strlcat(msg, other, OCX_MESSAGE_SIZE); + + for (lane = 0; lane < OCX_RX_LANES; lane++) + if (ctx->reg_com_int & BIT(lane)) { +@@ -1142,12 +1142,12 @@ static irqreturn_t thunderx_ocx_com_threaded_isr(int irq, void *irq_id) + lane, ctx->reg_lane_int[lane], + lane, ctx->reg_lane_stat11[lane]); + +- strncat(msg, other, OCX_MESSAGE_SIZE); ++ strlcat(msg, other, OCX_MESSAGE_SIZE); + + decode_register(other, OCX_OTHER_SIZE, + ocx_lane_errors, + ctx->reg_lane_int[lane]); +- strncat(msg, other, OCX_MESSAGE_SIZE); ++ strlcat(msg, other, OCX_MESSAGE_SIZE); + } + + if (ctx->reg_com_int & OCX_COM_INT_CE) +@@ -1217,7 +1217,7 @@ static irqreturn_t thunderx_ocx_lnk_threaded_isr(int irq, void *irq_id) + decode_register(other, OCX_OTHER_SIZE, + ocx_com_link_errors, ctx->reg_com_link_int); + +- strncat(msg, other, OCX_MESSAGE_SIZE); ++ strlcat(msg, other, OCX_MESSAGE_SIZE); + + if (ctx->reg_com_link_int & OCX_COM_LINK_INT_UE) + edac_device_handle_ue(ocx->edac_dev, 0, 0, msg); +@@ -1896,7 +1896,7 @@ static irqreturn_t thunderx_l2c_threaded_isr(int irq, void *irq_id) + + decode_register(other, L2C_OTHER_SIZE, l2_errors, ctx->reg_int); + +- strncat(msg, other, L2C_MESSAGE_SIZE); ++ strlcat(msg, other, L2C_MESSAGE_SIZE); + + if (ctx->reg_int & mask_ue) + edac_device_handle_ue(l2c->edac_dev, 0, 0, msg); +-- +2.43.0 + diff --git a/queue-6.1/efivarfs-force-ro-when-remounting-if-setvariable-is-.patch b/queue-6.1/efivarfs-force-ro-when-remounting-if-setvariable-is-.patch new file mode 100644 index 00000000000..18444d356bd --- /dev/null +++ b/queue-6.1/efivarfs-force-ro-when-remounting-if-setvariable-is-.patch @@ -0,0 +1,108 @@ +From 43bb0d3a47d0a852d189793fe1142f4de4d6050b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 7 Nov 2023 14:40:56 +0900 +Subject: efivarfs: force RO when remounting if SetVariable is not supported + +From: Ilias Apalodimas + +[ Upstream commit 0e8d2444168dd519fea501599d150e62718ed2fe ] + +If SetVariable at runtime is not supported by the firmware we never assign +a callback for that function. At the same time mount the efivarfs as +RO so no one can call that. However, we never check the permission flags +when someone remounts the filesystem as RW. As a result this leads to a +crash looking like this: + +$ mount -o remount,rw /sys/firmware/efi/efivars +$ efi-updatevar -f PK.auth PK + +[ 303.279166] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000 +[ 303.280482] Mem abort info: +[ 303.280854] ESR = 0x0000000086000004 +[ 303.281338] EC = 0x21: IABT (current EL), IL = 32 bits +[ 303.282016] SET = 0, FnV = 0 +[ 303.282414] EA = 0, S1PTW = 0 +[ 303.282821] FSC = 0x04: level 0 translation fault +[ 303.283771] user pgtable: 4k pages, 48-bit VAs, pgdp=000000004258c000 +[ 303.284913] [0000000000000000] pgd=0000000000000000, p4d=0000000000000000 +[ 303.286076] Internal error: Oops: 0000000086000004 [#1] PREEMPT SMP +[ 303.286936] Modules linked in: qrtr tpm_tis tpm_tis_core crct10dif_ce arm_smccc_trng rng_core drm fuse ip_tables x_tables ipv6 +[ 303.288586] CPU: 1 PID: 755 Comm: efi-updatevar Not tainted 6.3.0-rc1-00108-gc7d0c4695c68 #1 +[ 303.289748] Hardware name: Unknown Unknown Product/Unknown Product, BIOS 2023.04-00627-g88336918701d 04/01/2023 +[ 303.291150] pstate: 60400005 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) +[ 303.292123] pc : 0x0 +[ 303.292443] lr : efivar_set_variable_locked+0x74/0xec +[ 303.293156] sp : ffff800008673c10 +[ 303.293619] x29: ffff800008673c10 x28: ffff0000037e8000 x27: 0000000000000000 +[ 303.294592] x26: 0000000000000800 x25: ffff000002467400 x24: 0000000000000027 +[ 303.295572] x23: ffffd49ea9832000 x22: ffff0000020c9800 x21: ffff000002467000 +[ 303.296566] x20: 0000000000000001 x19: 00000000000007fc x18: 0000000000000000 +[ 303.297531] x17: 0000000000000000 x16: 0000000000000000 x15: 0000aaaac807ab54 +[ 303.298495] x14: ed37489f673633c0 x13: 71c45c606de13f80 x12: 47464259e219acf4 +[ 303.299453] x11: ffff000002af7b01 x10: 0000000000000003 x9 : 0000000000000002 +[ 303.300431] x8 : 0000000000000010 x7 : ffffd49ea8973230 x6 : 0000000000a85201 +[ 303.301412] x5 : 0000000000000000 x4 : ffff0000020c9800 x3 : 00000000000007fc +[ 303.302370] x2 : 0000000000000027 x1 : ffff000002467400 x0 : ffff000002467000 +[ 303.303341] Call trace: +[ 303.303679] 0x0 +[ 303.303938] efivar_entry_set_get_size+0x98/0x16c +[ 303.304585] efivarfs_file_write+0xd0/0x1a4 +[ 303.305148] vfs_write+0xc4/0x2e4 +[ 303.305601] ksys_write+0x70/0x104 +[ 303.306073] __arm64_sys_write+0x1c/0x28 +[ 303.306622] invoke_syscall+0x48/0x114 +[ 303.307156] el0_svc_common.constprop.0+0x44/0xec +[ 303.307803] do_el0_svc+0x38/0x98 +[ 303.308268] el0_svc+0x2c/0x84 +[ 303.308702] el0t_64_sync_handler+0xf4/0x120 +[ 303.309293] el0t_64_sync+0x190/0x194 +[ 303.309794] Code: ???????? ???????? ???????? ???????? (????????) +[ 303.310612] ---[ end trace 0000000000000000 ]--- + +Fix this by adding a .reconfigure() function to the fs operations which +we can use to check the requested flags and deny anything that's not RO +if the firmware doesn't implement SetVariable at runtime. + +Fixes: f88814cc2578 ("efi/efivars: Expose RT service availability via efivars abstraction") +Signed-off-by: Ilias Apalodimas +Signed-off-by: Ard Biesheuvel +Signed-off-by: Sasha Levin +--- + fs/efivarfs/super.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/fs/efivarfs/super.c b/fs/efivarfs/super.c +index 6780fc81cc11..f5966cd95918 100644 +--- a/fs/efivarfs/super.c ++++ b/fs/efivarfs/super.c +@@ -13,6 +13,7 @@ + #include + #include + #include ++#include + + #include "internal.h" + +@@ -226,8 +227,19 @@ static int efivarfs_get_tree(struct fs_context *fc) + return get_tree_single(fc, efivarfs_fill_super); + } + ++static int efivarfs_reconfigure(struct fs_context *fc) ++{ ++ if (!efivar_supports_writes() && !(fc->sb_flags & SB_RDONLY)) { ++ pr_err("Firmware does not support SetVariableRT. Can not remount with rw\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ + static const struct fs_context_operations efivarfs_context_ops = { + .get_tree = efivarfs_get_tree, ++ .reconfigure = efivarfs_reconfigure, + }; + + static int efivarfs_init_fs_context(struct fs_context *fc) +-- +2.43.0 + diff --git a/queue-6.1/efivarfs-free-s_fs_info-on-unmount.patch b/queue-6.1/efivarfs-free-s_fs_info-on-unmount.patch new file mode 100644 index 00000000000..80463160a04 --- /dev/null +++ b/queue-6.1/efivarfs-free-s_fs_info-on-unmount.patch @@ -0,0 +1,40 @@ +From 7ef43c5114d1adfea92dc9c013b3c3bdba2d0555 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 8 Dec 2023 17:39:28 +0100 +Subject: efivarfs: Free s_fs_info on unmount + +From: Ard Biesheuvel + +[ Upstream commit 547713d502f7b4b8efccd409cff84d731a23853b ] + +Now that we allocate a s_fs_info struct on fs context creation, we +should ensure that we free it again when the superblock goes away. + +Fixes: 5329aa5101f7 ("efivarfs: Add uid/gid mount options") +Signed-off-by: Ard Biesheuvel +Signed-off-by: Sasha Levin +--- + fs/efivarfs/super.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/fs/efivarfs/super.c b/fs/efivarfs/super.c +index f5966cd95918..77c7615bba5e 100644 +--- a/fs/efivarfs/super.c ++++ b/fs/efivarfs/super.c +@@ -250,10 +250,13 @@ static int efivarfs_init_fs_context(struct fs_context *fc) + + static void efivarfs_kill_sb(struct super_block *sb) + { ++ struct efivarfs_fs_info *sfi = sb->s_fs_info; ++ + kill_litter_super(sb); + + /* Remove all entries and destroy */ + efivar_entry_iter(efivarfs_destroy, &efivarfs_list, NULL); ++ kfree(sfi); + } + + static struct file_system_type efivarfs_type = { +-- +2.43.0 + diff --git a/queue-6.1/erofs-fix-memory-leak-on-short-lived-bounced-pages.patch b/queue-6.1/erofs-fix-memory-leak-on-short-lived-bounced-pages.patch new file mode 100644 index 00000000000..b6a46c198bb --- /dev/null +++ b/queue-6.1/erofs-fix-memory-leak-on-short-lived-bounced-pages.patch @@ -0,0 +1,50 @@ +From 1d93436916867fef5d1a0c4c2a56226b77dceda2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 29 Nov 2023 02:04:31 +0800 +Subject: erofs: fix memory leak on short-lived bounced pages + +From: Gao Xiang + +[ Upstream commit 93d6fda7f926451a0fa1121b9558d75ca47e861e ] + +Both MicroLZMA and DEFLATE algorithms can use short-lived pages on +demand for the overlapped inplace I/O decompression. + +However, those short-lived pages are actually added to +`be->compressed_pages`. Thus, it should be checked instead of +`pcl->compressed_bvecs`. + +The LZ4 algorithm doesn't work like this, so it won't be impacted. + +Fixes: 67139e36d970 ("erofs: introduce `z_erofs_parse_in_bvecs'") +Reviewed-by: Yue Hu +Reviewed-by: Chao Yu +Signed-off-by: Gao Xiang +Link: https://lore.kernel.org/r/20231128180431.4116991-1-hsiangkao@linux.alibaba.com +Signed-off-by: Sasha Levin +--- + fs/erofs/zdata.c | 5 ++--- + 1 file changed, 2 insertions(+), 3 deletions(-) + +diff --git a/fs/erofs/zdata.c b/fs/erofs/zdata.c +index 1b91ac5be961..cf9a2fa7f55d 100644 +--- a/fs/erofs/zdata.c ++++ b/fs/erofs/zdata.c +@@ -1192,12 +1192,11 @@ static int z_erofs_decompress_pcluster(struct z_erofs_decompress_backend *be, + put_page(page); + } else { + for (i = 0; i < pclusterpages; ++i) { +- page = pcl->compressed_bvecs[i].page; ++ /* consider shortlived pages added when decompressing */ ++ page = be->compressed_pages[i]; + + if (erofs_page_is_managed(sbi, page)) + continue; +- +- /* recycle all individual short-lived pages */ + (void)z_erofs_put_shortlivedpage(be->pagepool, page); + WRITE_ONCE(pcl->compressed_bvecs[i].page, NULL); + } +-- +2.43.0 + diff --git a/queue-6.1/f2fs-fix-to-avoid-dirent-corruption.patch b/queue-6.1/f2fs-fix-to-avoid-dirent-corruption.patch new file mode 100644 index 00000000000..c82cd4d2c26 --- /dev/null +++ b/queue-6.1/f2fs-fix-to-avoid-dirent-corruption.patch @@ -0,0 +1,60 @@ +From e441dee4496de1faf45f40dcb3bbaefa6ab7d38a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Nov 2023 17:25:16 +0800 +Subject: f2fs: fix to avoid dirent corruption + +From: Chao Yu + +[ Upstream commit 53edb549565f55ccd0bdf43be3d66ce4c2d48b28 ] + +As Al reported in link[1]: + +f2fs_rename() +... + if (old_dir != new_dir && !whiteout) + f2fs_set_link(old_inode, old_dir_entry, + old_dir_page, new_dir); + else + f2fs_put_page(old_dir_page, 0); + +You want correct inumber in the ".." link. And cross-directory +rename does move the source to new parent, even if you'd been asked +to leave a whiteout in the old place. + +[1] https://lore.kernel.org/all/20231017055040.GN800259@ZenIV/ + +With below testcase, it may cause dirent corruption, due to it missed +to call f2fs_set_link() to update ".." link to new directory. +- mkdir -p dir/foo +- renameat2 -w dir/foo bar + +[ASSERT] (__chk_dots_dentries:1421) --> Bad inode number[0x4] for '..', parent parent ino is [0x3] +[FSCK] other corrupted bugs [Fail] + +Fixes: 7e01e7ad746b ("f2fs: support RENAME_WHITEOUT") +Cc: Jan Kara +Reported-by: Al Viro +Signed-off-by: Chao Yu +Reviewed-by: Jan Kara +Signed-off-by: Jaegeuk Kim +Signed-off-by: Sasha Levin +--- + fs/f2fs/namei.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/fs/f2fs/namei.c b/fs/f2fs/namei.c +index bd020a992c2e..328cd20b16a5 100644 +--- a/fs/f2fs/namei.c ++++ b/fs/f2fs/namei.c +@@ -1099,7 +1099,7 @@ static int f2fs_rename(struct user_namespace *mnt_userns, struct inode *old_dir, + } + + if (old_dir_entry) { +- if (old_dir != new_dir && !whiteout) ++ if (old_dir != new_dir) + f2fs_set_link(old_inode, old_dir_entry, + old_dir_page, new_dir); + else +-- +2.43.0 + diff --git a/queue-6.1/f2fs-fix-to-check-compress-file-in-f2fs_move_file_ra.patch b/queue-6.1/f2fs-fix-to-check-compress-file-in-f2fs_move_file_ra.patch new file mode 100644 index 00000000000..f01c579267a --- /dev/null +++ b/queue-6.1/f2fs-fix-to-check-compress-file-in-f2fs_move_file_ra.patch @@ -0,0 +1,40 @@ +From da56614beb61c5a282280a9b1f052c6e4f4b9c1a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 10 Dec 2023 19:35:44 +0800 +Subject: f2fs: fix to check compress file in f2fs_move_file_range() + +From: Chao Yu + +[ Upstream commit fb9b65340c818875ea86464faf3c744bdce0055c ] + +f2fs_move_file_range() doesn't support migrating compressed cluster +data, let's add the missing check condition and return -EOPNOTSUPP +for the case until we support it. + +Fixes: 4c8ff7095bef ("f2fs: support data compression") +Signed-off-by: Chao Yu +Signed-off-by: Jaegeuk Kim +Signed-off-by: Sasha Levin +--- + fs/f2fs/file.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/fs/f2fs/file.c b/fs/f2fs/file.c +index 9b9fb3c57ec6..3f2c55b9aa8a 100644 +--- a/fs/f2fs/file.c ++++ b/fs/f2fs/file.c +@@ -2821,6 +2821,11 @@ static int f2fs_move_file_range(struct file *file_in, loff_t pos_in, + goto out; + } + ++ if (f2fs_compressed_file(src) || f2fs_compressed_file(dst)) { ++ ret = -EOPNOTSUPP; ++ goto out_unlock; ++ } ++ + ret = -EINVAL; + if (pos_in + len > src->i_size || pos_in + len < pos_in) + goto out_unlock; +-- +2.43.0 + diff --git a/queue-6.1/f2fs-fix-to-check-return-value-of-f2fs_recover_xattr.patch b/queue-6.1/f2fs-fix-to-check-return-value-of-f2fs_recover_xattr.patch new file mode 100644 index 00000000000..a0bdeb2af27 --- /dev/null +++ b/queue-6.1/f2fs-fix-to-check-return-value-of-f2fs_recover_xattr.patch @@ -0,0 +1,70 @@ +From 95729c4e74ea4317db1a9d3e3aa849940eaf3749 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 12 Dec 2023 10:15:27 +0800 +Subject: f2fs: fix to check return value of f2fs_recover_xattr_data + +From: Zhiguo Niu + +[ Upstream commit 86d7d57a3f096c8349b32a0cd5f6f314e4416a6d ] + +Should check return value of f2fs_recover_xattr_data in +__f2fs_setxattr rather than doing invalid retry if error happen. + +Also just do set_page_dirty in f2fs_recover_xattr_data when +page is changed really. + +Fixes: 50a472bbc79f ("f2fs: do not return EFSCORRUPTED, but try to run online repair") +Signed-off-by: Zhiguo Niu +Reviewed-by: Chao Yu +Signed-off-by: Jaegeuk Kim +Signed-off-by: Sasha Levin +--- + fs/f2fs/node.c | 6 +++--- + fs/f2fs/xattr.c | 11 +++++++---- + 2 files changed, 10 insertions(+), 7 deletions(-) + +diff --git a/fs/f2fs/node.c b/fs/f2fs/node.c +index 6efccd7ccfe1..c6d0e0709632 100644 +--- a/fs/f2fs/node.c ++++ b/fs/f2fs/node.c +@@ -2738,11 +2738,11 @@ int f2fs_recover_xattr_data(struct inode *inode, struct page *page) + f2fs_update_inode_page(inode); + + /* 3: update and set xattr node page dirty */ +- if (page) ++ if (page) { + memcpy(F2FS_NODE(xpage), F2FS_NODE(page), + VALID_XATTR_BLOCK_SIZE); +- +- set_page_dirty(xpage); ++ set_page_dirty(xpage); ++ } + f2fs_put_page(xpage, 1); + + return 0; +diff --git a/fs/f2fs/xattr.c b/fs/f2fs/xattr.c +index 8816e13ca7c9..0631b383e21f 100644 +--- a/fs/f2fs/xattr.c ++++ b/fs/f2fs/xattr.c +@@ -660,11 +660,14 @@ static int __f2fs_setxattr(struct inode *inode, int index, + here = __find_xattr(base_addr, last_base_addr, NULL, index, len, name); + if (!here) { + if (!F2FS_I(inode)->i_xattr_nid) { ++ error = f2fs_recover_xattr_data(inode, NULL); + f2fs_notice(F2FS_I_SB(inode), +- "recover xattr in inode (%lu)", inode->i_ino); +- f2fs_recover_xattr_data(inode, NULL); +- kfree(base_addr); +- goto retry; ++ "recover xattr in inode (%lu), error(%d)", ++ inode->i_ino, error); ++ if (!error) { ++ kfree(base_addr); ++ goto retry; ++ } + } + f2fs_err(F2FS_I_SB(inode), "set inode (%lu) has corrupted xattr", + inode->i_ino); +-- +2.43.0 + diff --git a/queue-6.1/f2fs-fix-to-update-iostat-correctly-in-f2fs_filemap_.patch b/queue-6.1/f2fs-fix-to-update-iostat-correctly-in-f2fs_filemap_.patch new file mode 100644 index 00000000000..f0db705d170 --- /dev/null +++ b/queue-6.1/f2fs-fix-to-update-iostat-correctly-in-f2fs_filemap_.patch @@ -0,0 +1,36 @@ +From ae2f297681dfb5cd9a9f407e443c624e9228364f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 10 Dec 2023 19:35:47 +0800 +Subject: f2fs: fix to update iostat correctly in f2fs_filemap_fault() + +From: Chao Yu + +[ Upstream commit bb34cc6ca87ff78f9fb5913d7619dc1389554da6 ] + +In f2fs_filemap_fault(), it fixes to update iostat info only if +VM_FAULT_LOCKED is tagged in return value of filemap_fault(). + +Fixes: 8b83ac81f428 ("f2fs: support read iostat") +Signed-off-by: Chao Yu +Signed-off-by: Jaegeuk Kim +Signed-off-by: Sasha Levin +--- + fs/f2fs/file.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/fs/f2fs/file.c b/fs/f2fs/file.c +index 3f2c55b9aa8a..fd22854dbeae 100644 +--- a/fs/f2fs/file.c ++++ b/fs/f2fs/file.c +@@ -42,7 +42,7 @@ static vm_fault_t f2fs_filemap_fault(struct vm_fault *vmf) + vm_fault_t ret; + + ret = filemap_fault(vmf); +- if (!ret) ++ if (ret & VM_FAULT_LOCKED) + f2fs_update_iostat(F2FS_I_SB(inode), inode, + APP_MAPPED_READ_IO, F2FS_BLKSIZE); + +-- +2.43.0 + diff --git a/queue-6.1/f2fs-fix-to-wait-on-block-writeback-for-post_read-ca.patch b/queue-6.1/f2fs-fix-to-wait-on-block-writeback-for-post_read-ca.patch new file mode 100644 index 00000000000..1b81f6217de --- /dev/null +++ b/queue-6.1/f2fs-fix-to-wait-on-block-writeback-for-post_read-ca.patch @@ -0,0 +1,69 @@ +From e963c3dfd980dd259b62617a5438cddcfc13db03 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 10 Dec 2023 19:35:43 +0800 +Subject: f2fs: fix to wait on block writeback for post_read case + +From: Chao Yu + +[ Upstream commit 55fdc1c24a1d6229fe0ecf31335fb9a2eceaaa00 ] + +If inode is compressed, but not encrypted, it missed to call +f2fs_wait_on_block_writeback() to wait for GCed page writeback +in IPU write path. + +Thread A GC-Thread + - f2fs_gc + - do_garbage_collect + - gc_data_segment + - move_data_block + - f2fs_submit_page_write + migrate normal cluster's block via + meta_inode's page cache +- f2fs_write_single_data_page + - f2fs_do_write_data_page + - f2fs_inplace_write_data + - f2fs_submit_page_bio + +IRQ +- f2fs_read_end_io + IRQ + old data overrides new data due to + out-of-order GC and common IO. + - f2fs_read_end_io + +Fixes: 4c8ff7095bef ("f2fs: support data compression") +Signed-off-by: Chao Yu +Signed-off-by: Jaegeuk Kim +Signed-off-by: Sasha Levin +--- + fs/f2fs/data.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +diff --git a/fs/f2fs/data.c b/fs/f2fs/data.c +index 3666c1fd77a6..8b561af37974 100644 +--- a/fs/f2fs/data.c ++++ b/fs/f2fs/data.c +@@ -2490,9 +2490,6 @@ int f2fs_encrypt_one_page(struct f2fs_io_info *fio) + + page = fio->compressed_page ? fio->compressed_page : fio->page; + +- /* wait for GCed page writeback via META_MAPPING */ +- f2fs_wait_on_block_writeback(inode, fio->old_blkaddr); +- + if (fscrypt_inode_uses_inline_crypto(inode)) + return 0; + +@@ -2681,6 +2678,10 @@ int f2fs_do_write_data_page(struct f2fs_io_info *fio) + goto out_writepage; + } + ++ /* wait for GCed page writeback via META_MAPPING */ ++ if (fio->post_read) ++ f2fs_wait_on_block_writeback(inode, fio->old_blkaddr); ++ + /* + * If current allocation needs SSR, + * it had better in-place writes for updated data. +-- +2.43.0 + diff --git a/queue-6.1/fbdev-imxfb-fix-left-margin-setting.patch b/queue-6.1/fbdev-imxfb-fix-left-margin-setting.patch new file mode 100644 index 00000000000..a1960db5d09 --- /dev/null +++ b/queue-6.1/fbdev-imxfb-fix-left-margin-setting.patch @@ -0,0 +1,121 @@ +From 0f4f621ac35a0c9239682e9a27ef712cfcfe3543 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 11 Nov 2023 11:41:50 +0100 +Subject: fbdev: imxfb: fix left margin setting + +From: Dario Binacchi + +[ Upstream commit 5758844105f7dd9a0a04990cd92499a1a593dd36 ] + +The previous setting did not take into account the CSTN mode. +For the H_WAIT_2 bitfield (bits 0-7) of the LCDC Horizontal Configuration +Register (LCDCR), the IMX25RM manual states that: + +In TFT mode, it specifies the number of SCLK periods between the end of +HSYNC and the beginning of OE signal, and the total delay time equals +(H_WAIT_2 + 3) of SCLK periods. +In CSTN mode, it specifies the number of SCLK periods between the end of +HSYNC and the first display data in each line, and the total delay time +equals (H_WAIT_2 + 2) of SCLK periods. + +The patch handles both cases. + +Fixes: 4e47382fbca9 ("fbdev: imxfb: warn about invalid left/right margin") +Fixes: 7e8549bcee00 ("imxfb: Fix margin settings") +Signed-off-by: Dario Binacchi +Signed-off-by: Helge Deller +Signed-off-by: Sasha Levin +--- + drivers/video/fbdev/imxfb.c | 27 +++++++++++++++++++++++++-- + 1 file changed, 25 insertions(+), 2 deletions(-) + +diff --git a/drivers/video/fbdev/imxfb.c b/drivers/video/fbdev/imxfb.c +index 36ada87b49a4..32b8374abeca 100644 +--- a/drivers/video/fbdev/imxfb.c ++++ b/drivers/video/fbdev/imxfb.c +@@ -42,6 +42,7 @@ + #include