From e08a675f940b2ec546236754718cd5f2a0054317 Mon Sep 17 00:00:00 2001 From: Mukul Joshi Date: Wed, 26 Feb 2025 15:35:23 -0500 Subject: [PATCH] drm/amdgpu: Setup Atomics enable in TCP UTCL0 for GFX 12.1.0 We need to explicitly setup atomics enable in TCP UTCL0 to enable PCIe atomics to host memory. Signed-off-by: Mukul Joshi Reviewed-by: Alex Sierra Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index a16cd26e9a1b..3080aecc8341 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -2521,6 +2521,12 @@ static void gfx_v12_1_init_golden_registers(struct amdgpu_device *adev) RETRY_FRAGMENT_THRESHOLD_UP_EN, 0x0); WREG32_SOC15(GC, 0, regTCP_UTCL0_THRASHING_CTRL, val); + + /* Set the TCP UTCL0 register to enable atomics */ + val = RREG32_SOC15(GC, 0, regTCP_UTCL0_CNTL1); + val = REG_SET_FIELD(val, TCP_UTCL0_CNTL1, ATOMIC_REQUESTER_EN, 0x1); + + WREG32_SOC15(GC, 0, regTCP_UTCL0_CNTL1, val); } static int gfx_v12_1_hw_init(struct amdgpu_ip_block *ip_block) -- 2.47.3