From e15d0b6680d10d7666195e9db65581364ad5e5df Mon Sep 17 00:00:00 2001 From: Xiao Zeng Date: Mon, 31 Jul 2023 12:26:51 -0600 Subject: [PATCH] [PATCH 3/5] [RISC-V] RISC-V Conditional Move costing [was:Generate Zicond instruction for select pattern with condition eq or neq to 0] This provides some basic costing to conditional moves. The underlying primitive of an IF-THEN-ELSE which turns into czero is a single insn (COSTS_N_INSNS (1)). But these insns were still consistently showing up with the wrong cost (8 instead of 4). This was chased down to computing the cost of the destination and the cost of the source independently, then summing them. That seems horribly wrong for register destinations. So this patch special cases an INSN that is just a SET of a register destination so that the cost comes from the SET_SRC. Long term the whole costing model needs a review. gcc/ * config/riscv/riscv.cc (riscv_rtx_costs, case IF_THEN_ELSE): Add Zicond costing. (case SET): For INSNs that just set a REG, take the cost from the SET_SRC. Co-authored-by: Jeff Law --- gcc/config/riscv/riscv.cc | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index b6a57d0306dd..8c474503080d 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2504,6 +2504,20 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN *total = COSTS_N_INSNS (1); return true; } + else if (TARGET_ZICOND + && outer_code == SET + && ((GET_CODE (XEXP (x, 1)) == REG + && XEXP (x, 2) == CONST0_RTX (GET_MODE (XEXP (x, 1)))) + || (GET_CODE (XEXP (x, 2)) == REG + && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 2)))) + || (GET_CODE (XEXP (x, 1)) == REG + && rtx_equal_p (XEXP (x, 1), XEXP (XEXP (x, 0), 0))) + || (GET_CODE (XEXP (x, 1)) == REG + && rtx_equal_p (XEXP (x, 2), XEXP (XEXP (x, 0), 0))))) + { + *total = COSTS_N_INSNS (1); + return true; + } else if (LABEL_REF_P (XEXP (x, 1)) && XEXP (x, 2) == pc_rtx) { if (equality_operator (XEXP (x, 0), mode) @@ -2881,6 +2895,16 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN } return false; + case SET: + /* A simple SET with a register destination takes its cost solely from + the SET_SRC operand. */ + if (outer_code == INSN && REG_P (SET_DEST (x))) + { + *total = riscv_rtx_costs (SET_SRC (x), mode, SET, opno, total, speed); + return true; + } + return false; + default: return false; } -- 2.47.2