From e45cc57c5674e404d32763d9cb0abe1070a11128 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Sun, 8 May 2005 12:06:24 +0000 Subject: [PATCH] re PR target/21416 (wrong code for __builtin_isless, __builtin_islessequal) PR target/21416 * config/mips/mips.c (mips_emit_compare): Don't reverse UNGE and UNGT comparisons. * config/mips/mips.md (sungt_df, sunge_df, sungt_sf, sunge_sf): New patterns. From-SVN: r99390 --- gcc/ChangeLog | 8 ++++++++ gcc/config/mips/mips.c | 2 -- gcc/config/mips/mips.md | 36 ++++++++++++++++++++++++++++++++++++ 3 files changed, 44 insertions(+), 2 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8c8c3f2d3fb4..63c1cc917ca7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2005-05-08 Richard Sandiford + + PR target/21416 + * config/mips/mips.c (mips_emit_compare): Don't reverse UNGE and UNGT + comparisons. + * config/mips/mips.md (sungt_df, sunge_df, sungt_sf, sunge_sf): New + patterns. + 2005-05-08 Stephane Carrez PR target/16925 diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 037d1e5d7cb3..bb4359e49bf9 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -3049,8 +3049,6 @@ get_float_compare_codes (enum rtx_code in_code, enum rtx_code *cmp_code, switch (in_code) { case NE: - case UNGE: - case UNGT: case LTGT: case ORDERED: *cmp_code = reverse_condition_maybe_unordered (in_code); diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index f054afc5aa25..35f89f0a1b43 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -7765,6 +7765,24 @@ srl\t%M0,%M1,%2\n\ [(set_attr "type" "fcmp") (set_attr "mode" "FPSW")]) +(define_insn "sungt_df" + [(set (match_operand:CC 0 "register_operand" "=z") + (ungt:CC (match_operand:DF 1 "register_operand" "f") + (match_operand:DF 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "c.ult.d\t%Z0%2,%1" + [(set_attr "type" "fcmp") + (set_attr "mode" "FPSW")]) + +(define_insn "sunge_df" + [(set (match_operand:CC 0 "register_operand" "=z") + (unge:CC (match_operand:DF 1 "register_operand" "f") + (match_operand:DF 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "c.ule.d\t%Z0%2,%1" + [(set_attr "type" "fcmp") + (set_attr "mode" "FPSW")]) + (define_insn "seq_df" [(set (match_operand:CC 0 "register_operand" "=z") (eq:CC (match_operand:DF 1 "register_operand" "f") @@ -7846,6 +7864,24 @@ srl\t%M0,%M1,%2\n\ [(set_attr "type" "fcmp") (set_attr "mode" "FPSW")]) +(define_insn "sungt_sf" + [(set (match_operand:CC 0 "register_operand" "=z") + (ungt:CC (match_operand:SF 1 "register_operand" "f") + (match_operand:SF 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT" + "c.ult.s\t%Z0%2,%1" + [(set_attr "type" "fcmp") + (set_attr "mode" "FPSW")]) + +(define_insn "sunge_sf" + [(set (match_operand:CC 0 "register_operand" "=z") + (unge:CC (match_operand:SF 1 "register_operand" "f") + (match_operand:SF 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT" + "c.ule.s\t%Z0%2,%1" + [(set_attr "type" "fcmp") + (set_attr "mode" "FPSW")]) + (define_insn "seq_sf" [(set (match_operand:CC 0 "register_operand" "=z") (eq:CC (match_operand:SF 1 "register_operand" "f") -- 2.47.2