From e4e8b60a4fc99e2aa399518f121a8a3d9f888520 Mon Sep 17 00:00:00 2001 From: Kong Lingling Date: Fri, 24 Mar 2023 09:54:46 +0800 Subject: [PATCH] [APX EGPR] Handle legacy insn that only support GPR16 (1/5) These legacy insn in opcode map0/1 only support GPR16, and do not have vex/evex counterpart, directly adjust constraints and add gpr32 attr to patterns. insn list: 1. xsave/xsave64, xrstor/xrstor64 2. xsaves/xsaves64, xrstors/xrstors64 3. xsavec/xsavec64 4. xsaveopt/xsaveopt64 5. fxsave64/fxrstor64 gcc/ChangeLog: * config/i386/i386.md (): Set attr gpr32 0 and constraint jm. (_rex64): Likewise. (_rex64): Likewise. (64): Likewise. (fxsave64): Likewise. (fxstore64): Likewise. gcc/testsuite/ChangeLog: * lib/target-supports.exp: Add apxf check. * gcc.target/i386/apx-legacy-insn-check-norex2.c: New test. * gcc.target/i386/apx-legacy-insn-check-norex2-asm.c: New assembler test. Co-authored-by: Hongyu Wang Co-authored-by: Hongtao Liu --- gcc/config/i386/i386.md | 18 +++++++---- .../i386/apx-legacy-insn-check-norex2-asm.c | 5 ++++ .../i386/apx-legacy-insn-check-norex2.c | 30 +++++++++++++++++++ gcc/testsuite/lib/target-supports.exp | 10 +++++++ 4 files changed, 57 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2-asm.c create mode 100644 gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2.c diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 144fccdf9628..e29fc8e48fc0 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -25626,11 +25626,12 @@ (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) (define_insn "fxsave64" - [(set (match_operand:BLK 0 "memory_operand" "=m") + [(set (match_operand:BLK 0 "memory_operand" "=jm") (unspec_volatile:BLK [(const_int 0)] UNSPECV_FXSAVE64))] "TARGET_64BIT && TARGET_FXSR" "fxsave64\t%0" [(set_attr "type" "other") + (set_attr "gpr32" "0") (set_attr "memory" "store") (set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 4"))]) @@ -25646,11 +25647,12 @@ (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) (define_insn "fxrstor64" - [(unspec_volatile [(match_operand:BLK 0 "memory_operand" "m")] + [(unspec_volatile [(match_operand:BLK 0 "memory_operand" "jm")] UNSPECV_FXRSTOR64)] "TARGET_64BIT && TARGET_FXSR" "fxrstor64\t%0" [(set_attr "type" "other") + (set_attr "gpr32" "0") (set_attr "memory" "load") (set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 4"))]) @@ -25704,7 +25706,7 @@ (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) (define_insn "_rex64" - [(set (match_operand:BLK 0 "memory_operand" "=m") + [(set (match_operand:BLK 0 "memory_operand" "=jm") (unspec_volatile:BLK [(match_operand:SI 1 "register_operand" "a") (match_operand:SI 2 "register_operand" "d")] @@ -25713,11 +25715,12 @@ "\t%0" [(set_attr "type" "other") (set_attr "memory" "store") + (set_attr "gpr32" "0") (set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) (define_insn "" - [(set (match_operand:BLK 0 "memory_operand" "=m") + [(set (match_operand:BLK 0 "memory_operand" "=jm") (unspec_volatile:BLK [(match_operand:SI 1 "register_operand" "a") (match_operand:SI 2 "register_operand" "d")] @@ -25726,6 +25729,7 @@ "\t%0" [(set_attr "type" "other") (set_attr "memory" "store") + (set_attr "gpr32" "0") (set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 4"))]) @@ -25743,7 +25747,7 @@ (define_insn "_rex64" [(unspec_volatile:BLK - [(match_operand:BLK 0 "memory_operand" "m") + [(match_operand:BLK 0 "memory_operand" "jm") (match_operand:SI 1 "register_operand" "a") (match_operand:SI 2 "register_operand" "d")] ANY_XRSTOR)] @@ -25751,12 +25755,13 @@ "\t%0" [(set_attr "type" "other") (set_attr "memory" "load") + (set_attr "gpr32" "0") (set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) (define_insn "64" [(unspec_volatile:BLK - [(match_operand:BLK 0 "memory_operand" "m") + [(match_operand:BLK 0 "memory_operand" "jm") (match_operand:SI 1 "register_operand" "a") (match_operand:SI 2 "register_operand" "d")] ANY_XRSTOR64)] @@ -25764,6 +25769,7 @@ "64\t%0" [(set_attr "type" "other") (set_attr "memory" "load") + (set_attr "gpr32" "0") (set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 4"))]) diff --git a/gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2-asm.c b/gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2-asm.c new file mode 100644 index 000000000000..7ecc861435f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2-asm.c @@ -0,0 +1,5 @@ +/* { dg-do assemble { target apxf } } */ +/* { dg-options "-O1 -mapxf -m64 -DDTYPE32" } */ + +#include "apx-legacy-insn-check-norex2.c" + diff --git a/gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2.c b/gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2.c new file mode 100644 index 000000000000..1e5450dfb737 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mapxf -m64 -DDTYPE32" } */ + +#include + +typedef unsigned int u32; +typedef unsigned long long u64; + +#ifndef DTYPE32 +#define DTYPE32 +#endif + +#ifdef DTYPE32 +typedef u32 DTYPE; +#endif + +__attribute__((target("xsave,fxsr"))) +void legacy_test () +{ + register DTYPE* val __asm__("r16"); + _xsave64 (val, 1); + _xrstor64 (val, 1); + _fxsave64 (val); + _fxrstor64 (val); +} + +/* { dg-final { scan-assembler-not "xsave64\[ \\t]+\\\.\\\*r\(1\[6-9\]\|2\[0-9\]|30\|31\)" } } */ +/* { dg-final { scan-assembler-not "xrstor64\[ \\t]+\\\.\\\*r\(1\[6-9\]\|2\[0-9\]|30\|31\)" } } */ +/* { dg-final { scan-assembler-not "fxsave64\[ \\t]+\\\.\\\*r\(1\[6-9\]\|2\[0-9\]|30\|31\)" } } */ +/* { dg-final { scan-assembler-not "fxrstor64\[ \\t]+\\\.\\\*r\(1\[6-9\]\|2\[0-9\]|30\|31\)" } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 64889fa6d346..f10245af1b06 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -10150,6 +10150,16 @@ proc check_effective_target_sm4 { } { } "-msm4" ] } +proc check_effective_target_apxf { } { + return [check_no_compiler_messages apxf object { + void + foo () + { + __asm__ volatile ("add\t%%r16, %%r31" ::); + } + } "-mapxf" ] +} + # Return 1 if sse instructions can be compiled. proc check_effective_target_sse { } { return [check_no_compiler_messages sse object { -- 2.47.2