From e540c47fc08e4480118e1f1b68adaf688d172528 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Jouni=20H=C3=B6gander?= Date: Thu, 4 Dec 2025 09:07:17 +0200 Subject: [PATCH] drm/i915/psr: Perform full frame update on async flip MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit According to bspec selective fetch is not supported with async flips and instructing full frame update on async flip. v4: - check crtc_state->async_flip_planes in psr2_sel_fetch_pipe_state_supported v3: - rebase - fix old_crtc_state->pipe_srcsz_early_tpt - fix using intel_atomic_get_new_crtc_state v2: - check also crtc_state->async_flip_planes in psr2_sel_fetch_plane_state_supported Bspec: 55229 Signed-off-by: Jouni Högander Reviewed-by: Ville Syrjälä Link: https://patch.msgid.link/20251204070718.1090778-3-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 2a378a5adc599..91f4ac86c7ad7 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2766,7 +2766,8 @@ static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state */ static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state) { - if (crtc_state->scaler_state.scaler_id >= 0) + if (crtc_state->scaler_state.scaler_id >= 0 || + crtc_state->async_flip_planes) return false; return true; -- 2.47.3