From e65aaf8efe1900f7bbf76235a078000bf2ec8b45 Mon Sep 17 00:00:00 2001 From: Juzhe-Zhong Date: Thu, 30 Nov 2023 07:14:46 +0800 Subject: [PATCH] RISC-V: Rename vconstraint into group_overlap Fix for Robin's suggestion. gcc/ChangeLog: * config/riscv/constraints.md (TARGET_VECTOR ? V_REGS : NO_REGS): Fix constraint. * config/riscv/riscv.md (no,W21,W42,W84,W41,W81,W82): Rename vconstraint into group_overlap. (no,yes): Ditto. (none,W21,W42,W84,W43,W86,W87): Ditto. * config/riscv/vector.md: Ditto. --- gcc/config/riscv/constraints.md | 12 ++++++------ gcc/config/riscv/riscv.md | 21 ++++++++++++--------- gcc/config/riscv/vector.md | 4 ++-- 3 files changed, 20 insertions(+), 17 deletions(-) diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 19bb36616bff..9836fd344608 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -183,14 +183,14 @@ (define_register_constraint "W84" "TARGET_VECTOR ? V_REGS : NO_REGS" "A vector register has register number % 8 == 4." "regno % 8 == 4") -(define_register_constraint "W41" "TARGET_VECTOR ? V_REGS : NO_REGS" - "A vector register has register number % 4 == 1." "regno % 4 == 1") +(define_register_constraint "W43" "TARGET_VECTOR ? V_REGS : NO_REGS" + "A vector register has register number % 4 == 3." "regno % 4 == 3") -(define_register_constraint "W81" "TARGET_VECTOR ? V_REGS : NO_REGS" - "A vector register has register number % 8 == 1." "regno % 8 == 1") +(define_register_constraint "W86" "TARGET_VECTOR ? V_REGS : NO_REGS" + "A vector register has register number % 8 == 6." "regno % 8 == 6") -(define_register_constraint "W82" "TARGET_VECTOR ? V_REGS : NO_REGS" - "A vector register has register number % 8 == 2." "regno % 8 == 2") +(define_register_constraint "W87" "TARGET_VECTOR ? V_REGS : NO_REGS" + "A vector register has register number % 8 == 7." "regno % 8 == 7") ;; This constraint is used to match instruction "csrr %0, vlenb" which is generated in "mov". ;; VLENB is a run-time constant which represent the vector register length in bytes. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 6bf2dfdf9b4c..4c6f63677df8 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -501,22 +501,25 @@ ] (const_string "no"))) -(define_attr "vconstraint" "no,W21,W42,W84,W41,W81,W82" - (const_string "no")) - -(define_attr "vconstraint_enabled" "no,yes" - (cond [(eq_attr "vconstraint" "no") +;; Widening instructions have group-overlap constraints. Those are only +;; valid for certain register-group sizes. This attribute marks the +;; alternatives not matching the required register-group size as disabled. +(define_attr "group_overlap" "none,W21,W42,W84,W43,W86,W87" + (const_string "none")) + +(define_attr "group_overlap_valid" "no,yes" + (cond [(eq_attr "group_overlap" "none") (const_string "yes") - (and (eq_attr "vconstraint" "W21") + (and (eq_attr "group_overlap" "W21") (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != 2")) (const_string "no") - (and (eq_attr "vconstraint" "W42,W41") + (and (eq_attr "group_overlap" "W42,W43") (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != 4")) (const_string "no") - (and (eq_attr "vconstraint" "W84,W81,W82") + (and (eq_attr "group_overlap" "W84,W86,W87") (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != 8")) (const_string "no") ] @@ -531,7 +534,7 @@ (eq_attr "fp_vector_disabled" "yes") (const_string "no") - (eq_attr "vconstraint_enabled" "no") + (eq_attr "group_overlap_valid" "no") (const_string "no") ] (const_string "yes"))) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 5667f8bd2b68..74716c73e983 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -3700,7 +3700,7 @@ "vext.vf2\t%0,%3%p1" [(set_attr "type" "vext") (set_attr "mode" "") - (set_attr "vconstraint" "W21,W21,W42,W42,W84,W84,no,no")]) + (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) ;; Vector Quad-Widening Sign-extend and Zero-extend. (define_insn "@pred__vf4" @@ -3923,7 +3923,7 @@ (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) (set (attr "avl_type_idx") (const_int 7)) - (set_attr "vconstraint" "W21,W21,W42,W42,W84,W84,no,no")]) + (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) ;; ------------------------------------------------------------------------------- ;; ---- Predicated integer Narrowing operations -- 2.47.2