From eaba6c73a0bec88c1a994dad10b75c1d6e59a736 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 3 Feb 2026 15:29:46 +0100 Subject: [PATCH] 6.6-stable patches added patches: drm-amdgpu-gfx10-fix-wptr-reset-in-kgq-init.patch drm-amdgpu-gfx11-fix-wptr-reset-in-kgq-init.patch drm-amdgpu-soc21-fix-xclk-for-apus.patch drm-imx-tve-fix-probe-device-leak.patch scripts-generate_rust_analyzer-add-compiler_builtins-core-dep.patch --- ...gpu-gfx10-fix-wptr-reset-in-kgq-init.patch | 37 +++++++++++++ ...gpu-gfx11-fix-wptr-reset-in-kgq-init.patch | 37 +++++++++++++ .../drm-amdgpu-soc21-fix-xclk-for-apus.patch | 39 ++++++++++++++ .../drm-imx-tve-fix-probe-device-leak.patch | 53 +++++++++++++++++++ ...lyzer-add-compiler_builtins-core-dep.patch | 37 +++++++++++++ queue-6.6/series | 5 ++ 6 files changed, 208 insertions(+) create mode 100644 queue-6.6/drm-amdgpu-gfx10-fix-wptr-reset-in-kgq-init.patch create mode 100644 queue-6.6/drm-amdgpu-gfx11-fix-wptr-reset-in-kgq-init.patch create mode 100644 queue-6.6/drm-amdgpu-soc21-fix-xclk-for-apus.patch create mode 100644 queue-6.6/drm-imx-tve-fix-probe-device-leak.patch create mode 100644 queue-6.6/scripts-generate_rust_analyzer-add-compiler_builtins-core-dep.patch diff --git a/queue-6.6/drm-amdgpu-gfx10-fix-wptr-reset-in-kgq-init.patch b/queue-6.6/drm-amdgpu-gfx10-fix-wptr-reset-in-kgq-init.patch new file mode 100644 index 0000000000..293d9e6488 --- /dev/null +++ b/queue-6.6/drm-amdgpu-gfx10-fix-wptr-reset-in-kgq-init.patch @@ -0,0 +1,37 @@ +From cc4f433b14e05eaa4a98fd677b836e9229422387 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Wed, 28 Jan 2026 20:51:08 -0500 +Subject: drm/amdgpu/gfx10: fix wptr reset in KGQ init +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Alex Deucher + +commit cc4f433b14e05eaa4a98fd677b836e9229422387 upstream. + +wptr is a 64 bit value and we need to update the +full value, not just 32 bits. Align with what we +already do for KCQs. + +Reviewed-by: Timur Kristóf +Reviewed-by: Jesse Zhang +Signed-off-by: Alex Deucher +(cherry picked from commit e80b1d1aa1073230b6c25a1a72e88f37e425ccda) +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +@@ -6459,7 +6459,7 @@ static int gfx_v10_0_gfx_init_queue(stru + memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); + /* reset the ring */ + ring->wptr = 0; +- *ring->wptr_cpu_addr = 0; ++ atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); + amdgpu_ring_clear_ring(ring); + } + diff --git a/queue-6.6/drm-amdgpu-gfx11-fix-wptr-reset-in-kgq-init.patch b/queue-6.6/drm-amdgpu-gfx11-fix-wptr-reset-in-kgq-init.patch new file mode 100644 index 0000000000..295b7941a0 --- /dev/null +++ b/queue-6.6/drm-amdgpu-gfx11-fix-wptr-reset-in-kgq-init.patch @@ -0,0 +1,37 @@ +From b1f810471c6a6bd349f7f9f2f2fed96082056d46 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Wed, 28 Jan 2026 18:09:03 -0500 +Subject: drm/amdgpu/gfx11: fix wptr reset in KGQ init +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Alex Deucher + +commit b1f810471c6a6bd349f7f9f2f2fed96082056d46 upstream. + +wptr is a 64 bit value and we need to update the +full value, not just 32 bits. Align with what we +already do for KCQs. + +Reviewed-by: Timur Kristóf +Reviewed-by: Jesse Zhang +Signed-off-by: Alex Deucher +(cherry picked from commit 1f16866bdb1daed7a80ca79ae2837a9832a74fbc) +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +@@ -3699,7 +3699,7 @@ static int gfx_v11_0_gfx_init_queue(stru + memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); + /* reset the ring */ + ring->wptr = 0; +- *ring->wptr_cpu_addr = 0; ++ atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); + amdgpu_ring_clear_ring(ring); + } + diff --git a/queue-6.6/drm-amdgpu-soc21-fix-xclk-for-apus.patch b/queue-6.6/drm-amdgpu-soc21-fix-xclk-for-apus.patch new file mode 100644 index 0000000000..6b5001dce1 --- /dev/null +++ b/queue-6.6/drm-amdgpu-soc21-fix-xclk-for-apus.patch @@ -0,0 +1,39 @@ +From e7fbff9e7622a00c2b53cb14df481916f0019742 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Fri, 16 Jan 2026 17:33:05 -0500 +Subject: drm/amdgpu/soc21: fix xclk for APUs + +From: Alex Deucher + +commit e7fbff9e7622a00c2b53cb14df481916f0019742 upstream. + +The reference clock is supposed to be 100Mhz, but it +appears to actually be slightly lower (99.81Mhz). + +Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14451 +Reviewed-by: Jesse Zhang +Signed-off-by: Alex Deucher +(cherry picked from commit 637fee3954d4bd509ea9d95ad1780fc174489860) +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/soc21.c | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/soc21.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc21.c +@@ -218,7 +218,13 @@ static u32 soc21_get_config_memsize(stru + + static u32 soc21_get_xclk(struct amdgpu_device *adev) + { +- return adev->clock.spll.reference_freq; ++ u32 reference_clock = adev->clock.spll.reference_freq; ++ ++ /* reference clock is actually 99.81 Mhz rather than 100 Mhz */ ++ if ((adev->flags & AMD_IS_APU) && reference_clock == 10000) ++ return 9981; ++ ++ return reference_clock; + } + + diff --git a/queue-6.6/drm-imx-tve-fix-probe-device-leak.patch b/queue-6.6/drm-imx-tve-fix-probe-device-leak.patch new file mode 100644 index 0000000000..d3944d08d5 --- /dev/null +++ b/queue-6.6/drm-imx-tve-fix-probe-device-leak.patch @@ -0,0 +1,53 @@ +From e535c23513c63f02f67e3e09e0787907029efeaf Mon Sep 17 00:00:00 2001 +From: Johan Hovold +Date: Thu, 30 Oct 2025 17:34:56 +0100 +Subject: drm/imx/tve: fix probe device leak + +From: Johan Hovold + +commit e535c23513c63f02f67e3e09e0787907029efeaf upstream. + +Make sure to drop the reference taken to the DDC device during probe on +probe failure (e.g. probe deferral) and on driver unbind. + +Fixes: fcbc51e54d2a ("staging: drm/imx: Add support for Television Encoder (TVEv2)") +Cc: stable@vger.kernel.org # 3.10 +Cc: Philipp Zabel +Reviewed-by: Frank Li +Signed-off-by: Johan Hovold +Link: https://patch.msgid.link/20251030163456.15807-1-johan@kernel.org +Signed-off-by: Maxime Ripard +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/imx/ipuv3/imx-tve.c | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +--- a/drivers/gpu/drm/imx/ipuv3/imx-tve.c ++++ b/drivers/gpu/drm/imx/ipuv3/imx-tve.c +@@ -521,6 +521,13 @@ static const struct component_ops imx_tv + .bind = imx_tve_bind, + }; + ++static void imx_tve_put_device(void *_dev) ++{ ++ struct device *dev = _dev; ++ ++ put_device(dev); ++} ++ + static int imx_tve_probe(struct platform_device *pdev) + { + struct device *dev = &pdev->dev; +@@ -542,6 +549,12 @@ static int imx_tve_probe(struct platform + if (ddc_node) { + tve->ddc = of_find_i2c_adapter_by_node(ddc_node); + of_node_put(ddc_node); ++ if (tve->ddc) { ++ ret = devm_add_action_or_reset(dev, imx_tve_put_device, ++ &tve->ddc->dev); ++ if (ret) ++ return ret; ++ } + } + + tve->mode = of_get_tve_mode(np); diff --git a/queue-6.6/scripts-generate_rust_analyzer-add-compiler_builtins-core-dep.patch b/queue-6.6/scripts-generate_rust_analyzer-add-compiler_builtins-core-dep.patch new file mode 100644 index 0000000000..010b0549ce --- /dev/null +++ b/queue-6.6/scripts-generate_rust_analyzer-add-compiler_builtins-core-dep.patch @@ -0,0 +1,37 @@ +From 5157c328edb35bac05ce77da473c3209d20e0bbb Mon Sep 17 00:00:00 2001 +From: Tamir Duberstein +Date: Wed, 23 Jul 2025 11:39:40 -0400 +Subject: scripts: generate_rust_analyzer: Add compiler_builtins -> core dep + +From: Tamir Duberstein + +commit 5157c328edb35bac05ce77da473c3209d20e0bbb upstream. + +Add a dependency edge from `compiler_builtins` to `core` to +`scripts/generate_rust_analyzer.py` to match `rust/Makefile`. This has +been incorrect since commit 8c4555ccc55c ("scripts: add +`generate_rust_analyzer.py`") + +Signed-off-by: Tamir Duberstein +Reviewed-by: Jesung Yang +Acked-by: Benno Lossin +Fixes: 8c4555ccc55c ("scripts: add `generate_rust_analyzer.py`") +Cc: stable@vger.kernel.org +Link: https://patch.msgid.link/20250723-rust-analyzer-pin-init-v1-1-3c6956173c78@kernel.org +Signed-off-by: Miguel Ojeda +Signed-off-by: Greg Kroah-Hartman +--- + scripts/generate_rust_analyzer.py | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/scripts/generate_rust_analyzer.py ++++ b/scripts/generate_rust_analyzer.py +@@ -73,7 +73,7 @@ def generate_crates(srctree, objtree, sy + append_crate( + "compiler_builtins", + srctree / "rust" / "compiler_builtins.rs", +- [], ++ ["core"], + ) + + append_crate( diff --git a/queue-6.6/series b/queue-6.6/series index 95dfee585b..d31a9860ac 100644 --- a/queue-6.6/series +++ b/queue-6.6/series @@ -34,3 +34,8 @@ selftests-mptcp-check-no-dup-close-events-after-error.patch selftests-mptcp-check-subflow-errors-in-close-events.patch selftests-mptcp-join-fix-local-endp-not-being-tracked.patch flex_proportions-make-fprop_new_period-hardirq-safe.patch +scripts-generate_rust_analyzer-add-compiler_builtins-core-dep.patch +drm-imx-tve-fix-probe-device-leak.patch +drm-amdgpu-soc21-fix-xclk-for-apus.patch +drm-amdgpu-gfx10-fix-wptr-reset-in-kgq-init.patch +drm-amdgpu-gfx11-fix-wptr-reset-in-kgq-init.patch -- 2.47.3