From eca9778fc8cabd032bbb68de3765aa45dabbc3e4 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Mon, 21 Jul 2025 15:41:00 +0100 Subject: [PATCH] aarch64: Fix neon-sve-bridge.c failures for big-endian Lowpart subregs are generally disallowed on big-endian SVE vector registers, since the first memory element is stored at the least significant end of the register, rather than the most significant end. (See the comment at the head of aarch64-sve.md for details, and aarch64_modes_compatible_p for the implementation.) This means that arm_sve_neon_bridge.h needs to use custom define_insns for big-endian targets, in lieu of using lowpart subregs. However, one of those define_insns relied on the prohibited lowparts internally, to convert an Advanced SIMD register to an SVE register. Since the lowpart is not allowed, the lowpart_subreg would return null, leading to a later ICE. The simplest fix seems to be to use %Z instead, to force the Advanced SIMD register to be written as an SVE register. gcc/ * config/aarch64/aarch64-sve.md (@aarch64_sve_set_neonq_): Use %Z instead of lowpart_subreg. Tweak formatting. (cherry picked from commit 69c839c7361430ec27d1f13f909531b872588f27) --- gcc/config/aarch64/aarch64-sve.md | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 0728cccad4f..f8f744c263b 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -11163,16 +11163,12 @@ (define_insn "@aarch64_sve_set_neonq_" [(set (match_operand:SVE_FULL 0 "register_operand" "=w") - (unspec:SVE_FULL - [(match_operand:SVE_FULL 1 "register_operand" "w") - (match_operand: 2 "register_operand" "w") - (match_operand: 3 "register_operand" "Upl")] - UNSPEC_SET_NEONQ))] + (unspec:SVE_FULL + [(match_operand:SVE_FULL 1 "register_operand" "w") + (match_operand: 2 "register_operand" "w") + (match_operand: 3 "register_operand" "Upl")] + UNSPEC_SET_NEONQ))] "TARGET_SVE && BYTES_BIG_ENDIAN" - { - operands[2] = lowpart_subreg (mode, operands[2], - GET_MODE (operands[2])); - return "sel\t%0., %3, %2., %1."; - } + "sel\t%0., %3, %Z2., %1." ) -- 2.47.2