From ed9d9012539b09caa8a6b18a625dc4e5b68d4a20 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 13 Feb 2026 15:03:19 +0100 Subject: [PATCH] arm64: dts: qcom: milos: Sort pinctrl subnodes by pins As documented in the "Devicetree Sources (DTS) Coding Style" document, pinctrl subnodes should be sorted by the pins property. Do this once for milos.dtsi so that future additions can be added at the right places. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260213-milos-pinctrl-sort-v1-1-799bae597074@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/milos.dtsi | 54 ++++++++++++++--------------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi index e1a51d43943ff..bd9a11ea703dc 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -1667,6 +1667,21 @@ wakeup-parent = <&pdc>; + qup_spi0_data_clk: qup-spi0-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio0", "gpio1", "gpio2"; + function = "qup0_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins = "gpio3"; + function = "qup0_se0"; + drive-strength = <6>; + bias-disable; + }; + qup_i2c1_data_clk: qup-i2c1-data-clk-state { /* SDA, SCL */ pins = "gpio4", "gpio5"; @@ -1683,29 +1698,6 @@ bias-pull-up = <2200>; }; - qup_i2c7_data_clk: qup-i2c7-data-clk-state { - /* SDA, SCL */ - pins = "gpio32", "gpio33"; - function = "qup1_se0"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_spi0_cs: qup-spi0-cs-state { - pins = "gpio3"; - function = "qup0_se0"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi0_data_clk: qup-spi0-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio0", "gpio1", "gpio2"; - function = "qup0_se0"; - drive-strength = <6>; - bias-disable; - }; - qup_uart5_default: qup-uart5-default-state { /* TX, RX */ pins = "gpio25", "gpio26"; @@ -1714,10 +1706,10 @@ bias-disable; }; - qup_uart11_default: qup-uart11-default-state { - /* TX, RX */ - pins = "gpio50", "gpio51"; - function = "qup1_se4"; + qup_i2c7_data_clk: qup-i2c7-data-clk-state { + /* SDA, SCL */ + pins = "gpio32", "gpio33"; + function = "qup1_se0"; drive-strength = <2>; bias-pull-up; }; @@ -1730,6 +1722,14 @@ bias-pull-down; }; + qup_uart11_default: qup-uart11-default-state { + /* TX, RX */ + pins = "gpio50", "gpio51"; + function = "qup1_se4"; + drive-strength = <2>; + bias-pull-up; + }; + sdc2_default: sdc2-default-state { clk-pins { pins = "gpio62"; -- 2.47.3