From ef7d4a6a497a947e863d94e729fb349afdf98b01 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Wed, 11 Jun 2025 21:58:54 +0800 Subject: [PATCH] drm/amdgpu: Enable atomics for all the available xcc Apply TCP_UTCL0_CNTL1 settings to all the available xcc Signed-off-by: Hawking Zhang Reviewed-by: Likun Gao Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 110e1cde926cb..4cdaad3570fcb 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -2518,15 +2518,24 @@ static void gfx_v12_1_xcc_disable_gpa_mode(struct amdgpu_device *adev, WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPG_PSP_DEBUG, data); } -static void gfx_v12_1_init_golden_registers(struct amdgpu_device *adev) +static void gfx_v12_1_xcc_enable_atomics(struct amdgpu_device *adev, + int xcc_id) { - uint32_t val; + uint32_t data; /* Set the TCP UTCL0 register to enable atomics */ - val = RREG32_SOC15(GC, 0, regTCP_UTCL0_CNTL1); - val = REG_SET_FIELD(val, TCP_UTCL0_CNTL1, ATOMIC_REQUESTER_EN, 0x1); + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_UTCL0_CNTL1); + data = REG_SET_FIELD(data, TCP_UTCL0_CNTL1, ATOMIC_REQUESTER_EN, 0x1); + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_UTCL0_CNTL1, data); +} + +static void gfx_v12_1_init_golden_registers(struct amdgpu_device *adev) +{ + int i; - WREG32_SOC15(GC, 0, regTCP_UTCL0_CNTL1, val); + for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); i++) + gfx_v12_1_xcc_enable_atomics(adev, i); } static int gfx_v12_1_hw_init(struct amdgpu_ip_block *ip_block) -- 2.47.3