From f00c9e9793dc7a89023aba7d3b64f05d15fbc5eb Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Wed, 17 Jun 2020 00:17:05 +0000 Subject: [PATCH] Daily bump. --- gcc/ChangeLog | 114 ++++++++++++++++++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/testsuite/ChangeLog | 96 +++++++++++++++++++++++++++++++++ 3 files changed, 211 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6cfb5b5e406b..10de672758eb 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,117 @@ +2020-06-16 Srinath Parvathaneni + + * config/arm/arm_mve.h (__arm_vbicq_n_u16): Correct the intrinsic + arguments. + (__arm_vbicq_n_s16): Likewise. + (__arm_vbicq_n_u32): Likewise. + (__arm_vbicq_n_s32): Likewise. + (__arm_vbicq): Modify polymorphic variant. + +2020-06-16 Srinath Parvathaneni + + PR target/94735 + * config/arm/predicates.md (mve_scatter_memory): Define to + match (mem (reg)) for scatter store memory. + * config/arm/mve.md (mve_vstrbq_scatter_offset_): Modify + define_insn to define_expand. + (mve_vstrbq_scatter_offset_p_): Likewise. + (mve_vstrhq_scatter_offset_): Likewise. + (mve_vstrhq_scatter_shifted_offset_p_): Likewise. + (mve_vstrhq_scatter_shifted_offset_): Likewise. + (mve_vstrdq_scatter_offset_p_v2di): Likewise. + (mve_vstrdq_scatter_offset_v2di): Likewise. + (mve_vstrdq_scatter_shifted_offset_p_v2di): Likewise. + (mve_vstrdq_scatter_shifted_offset_v2di): Likewise. + (mve_vstrhq_scatter_offset_fv8hf): Likewise. + (mve_vstrhq_scatter_offset_p_fv8hf): Likewise. + (mve_vstrhq_scatter_shifted_offset_fv8hf): Likewise. + (mve_vstrhq_scatter_shifted_offset_p_fv8hf): Likewise. + (mve_vstrwq_scatter_offset_fv4sf): Likewise. + (mve_vstrwq_scatter_offset_p_fv4sf): Likewise. + (mve_vstrwq_scatter_offset_p_v4si): Likewise. + (mve_vstrwq_scatter_offset_v4si): Likewise. + (mve_vstrwq_scatter_shifted_offset_fv4sf): Likewise. + (mve_vstrwq_scatter_shifted_offset_p_fv4sf): Likewise. + (mve_vstrwq_scatter_shifted_offset_p_v4si): Likewise. + (mve_vstrwq_scatter_shifted_offset_v4si): Likewise. + (mve_vstrbq_scatter_offset__insn): Define insn for scatter + stores. + (mve_vstrbq_scatter_offset_p__insn): Likewise. + (mve_vstrhq_scatter_offset__insn): Likewise. + (mve_vstrhq_scatter_shifted_offset_p__insn): Likewise. + (mve_vstrhq_scatter_shifted_offset__insn): Likewise. + (mve_vstrdq_scatter_offset_p_v2di_insn): Likewise. + (mve_vstrdq_scatter_offset_v2di_insn): Likewise. + (mve_vstrdq_scatter_shifted_offset_p_v2di_insn): Likewise. + (mve_vstrdq_scatter_shifted_offset_v2di_insn): Likewise. + (mve_vstrhq_scatter_offset_fv8hf_insn): Likewise. + (mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise. + (mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise. + (mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise. + (mve_vstrwq_scatter_offset_fv4sf_insn): Likewise. + (mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise. + (mve_vstrwq_scatter_offset_p_v4si_insn): Likewise. + (mve_vstrwq_scatter_offset_v4si_insn): Likewise. + (mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise. + (mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise. + (mve_vstrwq_scatter_shifted_offset_p_v4si_insn): Likewise. + (mve_vstrwq_scatter_shifted_offset_v4si_insn): Likewise. + +2020-06-16 Srinath Parvathaneni + + * config/arm/arm.c (mve_vector_mem_operand): Fix unwanted + fall-throughs. + +2020-06-16 Srinath Parvathaneni + Andre Vieira + + PR target/94959 + * config/arm/arm-protos.h (arm_mode_base_reg_class): Function + declaration. + (mve_vector_mem_operand): Likewise. + * config/arm/arm.c (thumb2_legitimate_address_p): For MVE target check + the load from memory to a core register is legitimate for give mode. + (mve_vector_mem_operand): Define function. + (arm_print_operand): Modify comment. + (arm_mode_base_reg_class): Define. + * config/arm/arm.h (MODE_BASE_REG_CLASS): Modify to add check for + TARGET_HAVE_MVE and expand to arm_mode_base_reg_class on TRUE. + * config/arm/constraints.md (Ux): Likewise. + (Ul): Likewise. + * config/arm/mve.md (mve_mov): Replace constraint Us with Ux and also + add support for missing Vector Store Register and Vector Load Register. + Add a new alternative to support load from memory to PC (or label) in + vector store/load. + (mve_vstrbq_): Modify constraint Us to Ux. + (mve_vldrbq_): Modify constriant Us to Ux, predicate to + mve_memory_operand and also modify the MVE instructions to emit. + (mve_vldrbq_z_): Modify constraint Us to Ux. + (mve_vldrhq_fv8hf): Modify constriant Us to Ux, predicate to + mve_memory_operand and also modify the MVE instructions to emit. + (mve_vldrhq_): Modify constriant Us to Ux, predicate to + mve_memory_operand and also modify the MVE instructions to emit. + (mve_vldrhq_z_fv8hf): Likewise. + (mve_vldrhq_z_): Likewise. + (mve_vldrwq_fv4sf): Likewise. + (mve_vldrwq_v4si): Likewise. + (mve_vldrwq_z_fv4sf): Likewise. + (mve_vldrwq_z_v4si): Likewise. + (mve_vld1q_f): Modify constriant Us to Ux. + (mve_vld1q_): Likewise. + (mve_vstrhq_fv8hf): Modify constriant Us to Ux, predicate to + mve_memory_operand. + (mve_vstrhq_p_fv8hf): Modify constriant Us to Ux, predicate to + mve_memory_operand and also modify the MVE instructions to emit. + (mve_vstrhq_p_): Likewise. + (mve_vstrhq_): Modify constriant Us to Ux, predicate to + mve_memory_operand. + (mve_vstrwq_fv4sf): Modify constriant Us to Ux. + (mve_vstrwq_p_fv4sf): Modify constriant Us to Ux and also modify the MVE + instructions to emit. + (mve_vstrwq_p_v4si): Likewise. + (mve_vstrwq_v4si): Likewise.Modify constriant Us to Ux. + * config/arm/predicates.md (mve_memory_operand): Define. + 2020-06-15 Andrew Stubbs * config/gcn/gcn-valu.md (v3): Fix unsignedp. diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 3ca7808b314d..d2b0822d1977 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20200616 +20200617 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 8d3d365da843..db4985195f3a 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,99 @@ +2020-06-16 Srinath Parvathaneni + + * gcc.target/arm/mve/intrinsics/vbicq_f16.c: Modify. + * gcc.target/arm/mve/intrinsics/vbicq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vbicq_u8.c: Likewise. + +2020-06-16 Srinath Parvathaneni + + PR target/94735 + * gcc.target/arm/mve/intrinsics/mve_vstore_scatter_base.c: New test. + * gcc.target/arm/mve/intrinsics/mve_vstore_scatter_base_p.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_vstore_scatter_offset.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_vstore_scatter_offset_p.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset.c: + Likewise. + * gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset_p.c: + Likewise. + +2020-06-16 Srinath Parvathaneni + Andre Vieira + + PR target/94959 + * gcc.target/arm/mve/intrinsics/mve_vector_float2.c: Modify. + * gcc.target/arm/mve/intrinsics/mve_vldr.c: New test. + * gcc.target/arm/mve/intrinsics/mve_vldr_z.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_vstr.c: Likewise. + * gcc.target/arm/mve/intrinsics/mve_vstr_p.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_f16.c: Modify. + * gcc.target/arm/mve/intrinsics/vld1q_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_z_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_z_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_z_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_z_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_z_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_z_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_z_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vld1q_z_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrbq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrbq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vuninitializedq_float.c: Likewise. + * gcc.target/arm/mve/intrinsics/vuninitializedq_float1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vuninitializedq_int.c: Likewise. + * gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c: Likewise. + +2020-06-16 Tobias Burnus + + PR middle-end/95622 + * lib/target-supports.exp (check_effective_target_offloading_enabled): + New. + * c-c++-common/goacc/kernels-alias-ipa-pta-2.c: Use it for xfail. + * c-c++-common/goacc/kernels-alias-ipa-pta-4.c: Likewise. + * c-c++-common/goacc/kernels-alias-ipa-pta.c: Likewise. + 2020-06-14 Steven G. Kargl Harald Anlauf -- 2.47.2