From f36f54ddf6c9d4a1111e52ef49d9d5e794ed9f3d Mon Sep 17 00:00:00 2001 From: rearnsha Date: Fri, 18 Oct 2019 19:05:16 +0000 Subject: [PATCH] [arm] Improvements to negvsi4 and negvdi4. The generic expansion code for negv does not try the subv patterns, but instead emits a sub and a compare separately. Fortunately, the patterns can make use of the new subv operations, so just call those. We can also rewrite this using an iterator to simplify things further. Finally, we can now make negvdi4 work on Thumb2 as well as Arm. * config/arm/arm.md (negv3): New expansion rule. (negvsi3, negvdi3): Delete. (negdi2_compare): Delete. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@277191 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 6 ++++++ gcc/config/arm/arm.md | 41 +++++------------------------------------ 2 files changed, 11 insertions(+), 36 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3f2fbb7336ed..6ef72d484a4d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2019-10-18 Richard Earnshaw + + * config/arm/arm.md (negv3): New expansion rule. + (negvsi3, negvdi3): Delete. + (negdi2_compare): Delete. + 2019-10-18 Richard Earnshaw * config/arm/arm.md (subvdi4): Decompose calculation into 32-bit diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 5a8175ff8b00..7ef0c16580d4 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -4581,48 +4581,17 @@ ;; Unary arithmetic insns -(define_expand "negvsi3" - [(match_operand:SI 0 "register_operand") - (match_operand:SI 1 "register_operand") +(define_expand "negv3" + [(match_operand:SIDI 0 "s_register_operand") + (match_operand:SIDI 1 "s_register_operand") (match_operand 2 "")] "TARGET_32BIT" { - emit_insn (gen_subsi3_compare (operands[0], const0_rtx, operands[1])); - arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[2]); - - DONE; -}) - -(define_expand "negvdi3" - [(match_operand:DI 0 "s_register_operand") - (match_operand:DI 1 "s_register_operand") - (match_operand 2 "")] - "TARGET_ARM" -{ - emit_insn (gen_negdi2_compare (operands[0], operands[1])); - arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[2]); - + emit_insn (gen_subv4 (operands[0], const0_rtx, operands[1], + operands[2])); DONE; }) - -(define_insn "negdi2_compare" - [(set (reg:CC CC_REGNUM) - (compare:CC - (const_int 0) - (match_operand:DI 1 "register_operand" "r,r"))) - (set (match_operand:DI 0 "register_operand" "=&r,&r") - (minus:DI (const_int 0) (match_dup 1)))] - "TARGET_ARM" - "@ - rsbs\\t%Q0, %Q1, #0;rscs\\t%R0, %R1, #0 - rsbs\\t%Q0, %Q1, #0;sbcs\\t%R0, %R1, %R1, lsl #1" - [(set_attr "conds" "set") - (set_attr "arch" "a,t2") - (set_attr "length" "8") - (set_attr "type" "multiple")] -) - (define_expand "negsi2" [(set (match_operand:SI 0 "s_register_operand") (neg:SI (match_operand:SI 1 "s_register_operand")))] -- 2.47.2