From f966b311c97a8c0de154c02e194efbad3a0fbdd6 Mon Sep 17 00:00:00 2001 From: Mark Wielaard Date: Fri, 13 Sep 2013 13:30:45 +0000 Subject: [PATCH] Bug 323893 - SSE3 not available on amd cpus in valgrind. Check minimum hardware capabilities, not exact matches to prevent downgrading to baseline if the hardware has more capabilities than we expect. Note that this is still not exactly correct. CPUID should depend on VEX capabilities, not on underlying CPU, see bug 324882. git-svn-id: svn://svn.valgrind.org/vex/trunk@2761 --- VEX/priv/guest_amd64_toIR.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/VEX/priv/guest_amd64_toIR.c b/VEX/priv/guest_amd64_toIR.c index 38c2556c90..522bfbe147 100644 --- a/VEX/priv/guest_amd64_toIR.c +++ b/VEX/priv/guest_amd64_toIR.c @@ -20937,15 +20937,17 @@ Long dis_ESC_0F ( const HChar* fName = NULL; void* fAddr = NULL; if (haveF2orF3(pfx)) goto decode_failure; - if (archinfo->hwcaps == (VEX_HWCAPS_AMD64_SSE3 - |VEX_HWCAPS_AMD64_CX16 - |VEX_HWCAPS_AMD64_AVX)) { + /* This isn't entirely correct, CPUID should depend on the VEX + capabilities, not on the underlying CPU. See bug #324882. */ + if ((archinfo->hwcaps & VEX_HWCAPS_AMD64_SSE3) && + (archinfo->hwcaps & VEX_HWCAPS_AMD64_CX16) && + (archinfo->hwcaps & VEX_HWCAPS_AMD64_AVX)) { fName = "amd64g_dirtyhelper_CPUID_avx_and_cx16"; fAddr = &amd64g_dirtyhelper_CPUID_avx_and_cx16; /* This is a Core-i5-2300-like machine */ } - else if (archinfo->hwcaps == (VEX_HWCAPS_AMD64_SSE3 - |VEX_HWCAPS_AMD64_CX16)) { + else if ((archinfo->hwcaps & VEX_HWCAPS_AMD64_SSE3) && + (archinfo->hwcaps & VEX_HWCAPS_AMD64_CX16)) { fName = "amd64g_dirtyhelper_CPUID_sse42_and_cx16"; fAddr = &amd64g_dirtyhelper_CPUID_sse42_and_cx16; /* This is a Core-i5-670-like machine */ -- 2.47.2