From f96e5fdeb65f841f99ef763f0e53a680106a8760 Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Wed, 22 Nov 2023 01:18:31 +0000 Subject: [PATCH] RISC-V/testsuite: Add branched cases for FP NE cond-move operations Verify, for the floating-point NE conditional-move operation, that if-conversion triggers via `noce_try_cmove' at the respective sufficiently high `-mbranch-cost=' settings that make branchless code sequences produced by if-conversion cheaper than their original branched equivalents, and that extraneous instructions such as SNEZ, etc. are not present in output. gcc/testsuite/ * gcc.target/riscv/movdifeq-sfb.c: New test. * gcc.target/riscv/movdifeq-thead.c: New test. * gcc.target/riscv/movdifeq-ventana.c: New test. * gcc.target/riscv/movdifeq-zicond.c: New test. * gcc.target/riscv/movdifeq.c: New test. * gcc.target/riscv/movsifeq-sfb.c: New test. * gcc.target/riscv/movsifeq-thead.c: New test. * gcc.target/riscv/movsifeq-ventana.c: New test. * gcc.target/riscv/movsifeq-zicond.c: New test. * gcc.target/riscv/movsifeq.c: New test. --- gcc/testsuite/gcc.target/riscv/movdifeq-sfb.c | 27 ++++++++++++++++++ .../gcc.target/riscv/movdifeq-thead.c | 25 +++++++++++++++++ .../gcc.target/riscv/movdifeq-ventana.c | 28 +++++++++++++++++++ .../gcc.target/riscv/movdifeq-zicond.c | 28 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdifeq.c | 28 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsifeq-sfb.c | 27 ++++++++++++++++++ .../gcc.target/riscv/movsifeq-thead.c | 25 +++++++++++++++++ .../gcc.target/riscv/movsifeq-ventana.c | 28 +++++++++++++++++++ .../gcc.target/riscv/movsifeq-zicond.c | 28 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsifeq.c | 28 +++++++++++++++++++ 10 files changed, 272 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/movdifeq-sfb.c create mode 100644 gcc/testsuite/gcc.target/riscv/movdifeq-thead.c create mode 100644 gcc/testsuite/gcc.target/riscv/movdifeq-ventana.c create mode 100644 gcc/testsuite/gcc.target/riscv/movdifeq-zicond.c create mode 100644 gcc/testsuite/gcc.target/riscv/movdifeq.c create mode 100644 gcc/testsuite/gcc.target/riscv/movsifeq-sfb.c create mode 100644 gcc/testsuite/gcc.target/riscv/movsifeq-thead.c create mode 100644 gcc/testsuite/gcc.target/riscv/movsifeq-ventana.c create mode 100644 gcc/testsuite/gcc.target/riscv/movsifeq-zicond.c create mode 100644 gcc/testsuite/gcc.target/riscv/movsifeq.c diff --git a/gcc/testsuite/gcc.target/riscv/movdifeq-sfb.c b/gcc/testsuite/gcc.target/riscv/movdifeq-sfb.c new file mode 100644 index 000000000000..fe5a79a520a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movdifeq-sfb.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifeq (double w, double x, int_t y, int_t z) +{ + return w == x ? y : z; +} + +/* Expect short forward branch assembly like: + + feq.d a5,fa0,fa1 + beq a5,zero,1f # movcc + mv a1,a0 +1: + mv a0,a1 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdifeq-thead.c b/gcc/testsuite/gcc.target/riscv/movdifeq-thead.c new file mode 100644 index 000000000000..487e3eb74937 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movdifeq-thead.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifeq (double w, double x, int_t y, int_t z) +{ + return w == x ? y : z; +} + +/* Expect branchless assembly like: + + feq.d a5,fa0,fa1 + th.mveqz a0,a1,a5 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdifeq-ventana.c b/gcc/testsuite/gcc.target/riscv/movdifeq-ventana.c new file mode 100644 index 000000000000..6d6c80197039 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movdifeq-ventana.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifeq (double w, double x, int_t y, int_t z) +{ + return w == x ? y : z; +} + +/* Expect branchless assembly like: + + feq.d a5,fa0,fa1 + vt.maskcn a1,a1,a5 + vt.maskc a0,a0,a5 + or a0,a0,a1 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdifeq-zicond.c b/gcc/testsuite/gcc.target/riscv/movdifeq-zicond.c new file mode 100644 index 000000000000..15bd6e13d7fe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movdifeq-zicond.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifeq (double w, double x, int_t y, int_t z) +{ + return w == x ? y : z; +} + +/* Expect branchless assembly like: + + feq.d a5,fa0,fa1 + czero.nez a1,a1,a5 + czero.eqz a0,a0,a5 + or a0,a0,a1 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdifeq.c b/gcc/testsuite/gcc.target/riscv/movdifeq.c new file mode 100644 index 000000000000..de6e17e5f807 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movdifeq.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=5 -mmovcc -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifeq (double w, double x, int_t y, int_t z) +{ + return w == x ? y : z; +} + +/* Expect branchless assembly like: + + feq.d a5,fa0,fa1 + neg a5,a5 + and a0,a5,a0 + not a5,a5 + and a5,a5,a1 + or a0,a0,a5 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsifeq-sfb.c b/gcc/testsuite/gcc.target/riscv/movsifeq-sfb.c new file mode 100644 index 000000000000..1f20bb4f45c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movsifeq-sfb.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifeq (double w, double x, int_t y, int_t z) +{ + return w == x ? y : z; +} + +/* Expect short forward branch assembly like: + + feq.d a5,fa0,fa1 + beq a5,zero,1f # movcc + mv a1,a0 +1: + mv a0,a1 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsifeq-thead.c b/gcc/testsuite/gcc.target/riscv/movsifeq-thead.c new file mode 100644 index 000000000000..e2e69e008457 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movsifeq-thead.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifeq (double w, double x, int_t y, int_t z) +{ + return w == x ? y : z; +} + +/* Expect branchless assembly like: + + feq.d a5,fa0,fa1 + th.mveqz a0,a1,a5 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsifeq-ventana.c b/gcc/testsuite/gcc.target/riscv/movsifeq-ventana.c new file mode 100644 index 000000000000..9fb29aa5bf40 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movsifeq-ventana.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifeq (double w, double x, int_t y, int_t z) +{ + return w == x ? y : z; +} + +/* Expect branchless assembly like: + + feq.d a5,fa0,fa1 + vt.maskcn a1,a1,a5 + vt.maskc a0,a0,a5 + or a0,a0,a1 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsifeq-zicond.c b/gcc/testsuite/gcc.target/riscv/movsifeq-zicond.c new file mode 100644 index 000000000000..d967d328d836 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movsifeq-zicond.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifeq (double w, double x, int_t y, int_t z) +{ + return w == x ? y : z; +} + +/* Expect branchless assembly like: + + feq.d a5,fa0,fa1 + czero.nez a1,a1,a5 + czero.eqz a0,a0,a5 + or a0,a0,a1 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsifeq.c b/gcc/testsuite/gcc.target/riscv/movsifeq.c new file mode 100644 index 000000000000..a4c0c674765a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movsifeq.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=5 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=5 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifeq (double w, double x, int_t y, int_t z) +{ + return w == x ? y : z; +} + +/* Expect branchless assembly like: + + feq.d a5,fa0,fa1 + neg a5,a5 + and a0,a5,a0 + not a5,a5 + and a5,a5,a1 + or a0,a0,a5 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ -- 2.47.2