From fba8fc4a9620c2e4600f609d6c70076885d5184e Mon Sep 17 00:00:00 2001 From: Balaji Selvanathan Date: Fri, 27 Jun 2025 10:22:44 +0530 Subject: [PATCH] usb: dwc3: qcom: Add delays in UTMI clock selection for Qscratch Added delays before and after setting the PIPE_UTMI_CLK_SEL and PIPE3_PHYSTATUS_SW bits in the Qscratch GENERAL_CFG register during UTMI clock selection for DWC3 on Qualcomm platforms. These delays help ensure proper timing and stability of the UTMI clock switching sequence, potentially avoiding race conditions or unstable PHY behavior during initialization. Tested on platforms using Qscratch-based DWC3 PHY configuration. This change is taken from this Linux kernel implementation: https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/usb/dwc3/dwc3-qcom.c?id=a4333c3a6ba9ca9cff50a3c1d1bf193dc5489e1c Signed-off-by: Balaji Selvanathan Reviewed-by: Neil Armstrong Reviewed-by: Mattijs Korpershoek Link: https://patch.msgid.link/20250627045244.2225303-1-balaji.selvanathan@oss.qualcomm.com Signed-off-by: Casey Connolly --- drivers/usb/dwc3/dwc3-generic.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index bb11613a587..02c02b1d80e 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -461,9 +461,13 @@ static void dwc3_qcom_select_utmi_clk(void __iomem *qscratch_base) setbits_le32(qscratch_base + QSCRATCH_GENERAL_CFG, PIPE_UTMI_CLK_DIS); + udelay(100); + setbits_le32(qscratch_base + QSCRATCH_GENERAL_CFG, PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW); + udelay(100); + clrbits_le32(qscratch_base + QSCRATCH_GENERAL_CFG, PIPE_UTMI_CLK_DIS); } -- 2.47.3