From fd77b1208ddd5605b32bd836e6b8ce986fb94c8c Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Tue, 15 Feb 2022 18:09:34 +0000 Subject: [PATCH] aarch64: Add +nosve to tests This patch adds +nosve to various Advanced SIMD-only tests. gcc/testsuite/ * gcc.target/aarch64/shl-combine-2.c: New test. * gcc.target/aarch64/shl-combine-3.c: Likewise. * gcc.target/aarch64/shl-combine-4.c: Likewise. * gcc.target/aarch64/shl-combine-5.c: Likewise. * gcc.target/aarch64/xtn-combine-1.c: Likewise. * gcc.target/aarch64/xtn-combine-2.c: Likewise. * gcc.target/aarch64/xtn-combine-3.c: Likewise. * gcc.target/aarch64/xtn-combine-4.c: Likewise. * gcc.target/aarch64/xtn-combine-5.c: Likewise. * gcc.target/aarch64/xtn-combine-6.c: Likewise. --- gcc/testsuite/gcc.target/aarch64/shl-combine-2.c | 2 ++ gcc/testsuite/gcc.target/aarch64/shl-combine-3.c | 2 ++ gcc/testsuite/gcc.target/aarch64/shl-combine-4.c | 2 ++ gcc/testsuite/gcc.target/aarch64/shl-combine-5.c | 2 ++ gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c | 2 ++ gcc/testsuite/gcc.target/aarch64/xtn-combine-2.c | 2 ++ gcc/testsuite/gcc.target/aarch64/xtn-combine-3.c | 2 ++ gcc/testsuite/gcc.target/aarch64/xtn-combine-4.c | 2 ++ gcc/testsuite/gcc.target/aarch64/xtn-combine-5.c | 2 ++ gcc/testsuite/gcc.target/aarch64/xtn-combine-6.c | 2 ++ 10 files changed, 20 insertions(+) diff --git a/gcc/testsuite/gcc.target/aarch64/shl-combine-2.c b/gcc/testsuite/gcc.target/aarch64/shl-combine-2.c index 6a0331fbe609..491fd44e6377 100644 --- a/gcc/testsuite/gcc.target/aarch64/shl-combine-2.c +++ b/gcc/testsuite/gcc.target/aarch64/shl-combine-2.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ +#pragma GCC target "+nosve" + #define TYPE char void e (signed TYPE * restrict a, signed TYPE *b, int n) diff --git a/gcc/testsuite/gcc.target/aarch64/shl-combine-3.c b/gcc/testsuite/gcc.target/aarch64/shl-combine-3.c index 2086b24a3cb5..39bef21f39c9 100644 --- a/gcc/testsuite/gcc.target/aarch64/shl-combine-3.c +++ b/gcc/testsuite/gcc.target/aarch64/shl-combine-3.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ +#pragma GCC target "+nosve" + #define TYPE short void e (signed TYPE * restrict a, signed TYPE *b, int n) diff --git a/gcc/testsuite/gcc.target/aarch64/shl-combine-4.c b/gcc/testsuite/gcc.target/aarch64/shl-combine-4.c index 083181071f40..15dcbff8e8cf 100644 --- a/gcc/testsuite/gcc.target/aarch64/shl-combine-4.c +++ b/gcc/testsuite/gcc.target/aarch64/shl-combine-4.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ +#pragma GCC target "+nosve" + #define TYPE int void e (signed TYPE * restrict a, signed TYPE *b, int n) diff --git a/gcc/testsuite/gcc.target/aarch64/shl-combine-5.c b/gcc/testsuite/gcc.target/aarch64/shl-combine-5.c index 6b2a6bd86b36..703f63023828 100644 --- a/gcc/testsuite/gcc.target/aarch64/shl-combine-5.c +++ b/gcc/testsuite/gcc.target/aarch64/shl-combine-5.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ +#pragma GCC target "+nosve" + #define TYPE long void e (signed TYPE * restrict a, signed TYPE *b, int n) diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c b/gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c index 14e0414cd147..27b785832f00 100644 --- a/gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ +#pragma GCC target "+nosve" + #define SIGN signed #define TYPE1 char #define TYPE2 short diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-2.c b/gcc/testsuite/gcc.target/aarch64/xtn-combine-2.c index c259010442bc..02f03fa7efe6 100644 --- a/gcc/testsuite/gcc.target/aarch64/xtn-combine-2.c +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-2.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ +#pragma GCC target "+nosve" + #define SIGN signed #define TYPE1 short #define TYPE2 int diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-3.c b/gcc/testsuite/gcc.target/aarch64/xtn-combine-3.c index 9a2065f65101..4bcbd8519c22 100644 --- a/gcc/testsuite/gcc.target/aarch64/xtn-combine-3.c +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-3.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ +#pragma GCC target "+nosve" + #define SIGN signed #define TYPE1 int #define TYPE2 long long diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-4.c b/gcc/testsuite/gcc.target/aarch64/xtn-combine-4.c index 77c3dce12049..29703d1d0429 100644 --- a/gcc/testsuite/gcc.target/aarch64/xtn-combine-4.c +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-4.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ +#pragma GCC target "+nosve" + #define SIGN unsigned #define TYPE1 char #define TYPE2 short diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-5.c b/gcc/testsuite/gcc.target/aarch64/xtn-combine-5.c index ae30e864ed7a..f5ee30dbae7f 100644 --- a/gcc/testsuite/gcc.target/aarch64/xtn-combine-5.c +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-5.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ +#pragma GCC target "+nosve" + #define SIGN unsigned #define TYPE1 short #define TYPE2 int diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-6.c b/gcc/testsuite/gcc.target/aarch64/xtn-combine-6.c index 882f3d333e2c..3ddb87eb6871 100644 --- a/gcc/testsuite/gcc.target/aarch64/xtn-combine-6.c +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-6.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ +#pragma GCC target "+nosve" + #define SIGN unsigned #define TYPE1 int #define TYPE2 long long -- 2.47.2