From fe8c17b6ed7ebd2262cecc8967a7a30577021d08 Mon Sep 17 00:00:00 2001 From: Oleg Endo Date: Tue, 13 Jan 2015 01:18:56 +0000 Subject: [PATCH] backport: re PR target/64479 ([SH] wrong optimization delayed-branch) gcc/ Backport form mainline 2015-01-13 Oleg Endo PR target/64479 * rtlanal.c (set_reg_p): Handle SEQUENCE constructs. From-SVN: r219508 --- gcc/ChangeLog | 8 ++++++++ gcc/rtlanal.c | 13 ++++++++++++- 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 484f0c9979ca..189c068e2cd9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2015-01-13 Oleg Endo + + Backport form mainline + 2015-01-13 Oleg Endo + + PR target/64479 + * rtlanal.c (set_reg_p): Handle SEQUENCE constructs. + 2014-12-27 H.J. Lu Backport from mainline: diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c index 89455d3615b3..dcb23cc5916d 100644 --- a/gcc/rtlanal.c +++ b/gcc/rtlanal.c @@ -873,6 +873,17 @@ reg_set_between_p (const_rtx reg, const_rtx from_insn, const_rtx to_insn) int reg_set_p (const_rtx reg, const_rtx insn) { + /* After delay slot handling, call and branch insns might be in a + sequence. Check all the elements there. */ + if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE) + { + for (int i = 0; i < XVECLEN (PATTERN (insn), 0); ++i) + if (reg_set_p (reg, XVECEXP (PATTERN (insn), 0, i))) + return true; + + return false; + } + /* We can be passed an insn or part of one. If we are passed an insn, check if a side-effect of the insn clobbers REG. */ if (INSN_P (insn) @@ -884,7 +895,7 @@ reg_set_p (const_rtx reg, const_rtx insn) GET_MODE (reg), REGNO (reg))) || MEM_P (reg) || find_reg_fusage (insn, CLOBBER, reg))))) - return 1; + return true; return set_of (reg, insn) != NULL_RTX; } -- 2.47.2