From 29b3d929a610c265675b74a173ac529d69790361 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Sun, 2 Nov 2025 15:15:35 +0100 Subject: [PATCH] microchipsw: lan969x: add Novarq Tactical 1000 Novarq Tactical 1000 is a LAN9696 based switch. Specifications: * CPU: Microchip LAN9696 switch SoC * DRAM: 2GB DDR4 * Storage: * 32MB QSPI NOR * 16GB eMMC * Networking: * 24 x 10/100/1000 RJ45 via LAN8804 Quad PHY-s over QSGMII * 4 x 100/1000/2500/5000/10000 SFP+ ports * 1 x 10/100/1000 management RJ45 via LAN8840 PHY over RGMII (U-Boot too) * USB: 1 x USB2.0 Type-A * Management via USB-C (MCP2200): * UART @ 115200 baud (Default), 921600 possible * GPIO-s for bootstrap and reset * LED-s: * 2 per networking port (Green and Yellow) * Green status LED * Soft reset GPIO * Power: 12V DC barrel jack * External PoE: * Option for PoE add-on * Temperature Sensors: * TMP1075 onboard * CPU temperature * Microchip MCP79402 RTC with battery back-up * Microchip ATECC608C secure peripheral * CPU heatsink with PWM fan * Onboard header for case fan Installation instructions: 1. Connect to UART via the USB-C port 2. Connect the management port 3. Boot and interrupt U-Boot 4. TFTP the OpenWrt initramfs image and boot it 5. SCP the OpenWrt eMMC GPT image to a running OpenWrt initramfs to /tmp openwrt-microchipsw-lan969x-novarq_tactical-1000-squashfs-emmc-gpt.img.gz And decompress it via: gzip -d /tmp/openwrt-microchipsw-lan969x-novarq_tactical-1000-squashfs-emmc-gpt.img.gz 6. Wipe eMMC with: dd if=/dev/zero of=/dev/mmcblk0 bs=1M 7. Flash OpenWrt eMMC image with: dd if=/tmp/openwrt-microchipsw-lan969x-novarq_tactical-1000-squashfs-emmc-gpt.img of=/dev/mmcblk0 After a restart OpenWrt will boot, and then regular sysupgrade can be used for upgrades. Signed-off-by: Robert Marko --- .../arm-trusted-firmware-microchipsw/Makefile | 12 +- ...-lan969x-add-Novarq-Tactical-1000-v3.patch | 171 ++++ package/boot/uboot-microchipsw/Makefile | 11 +- .../microchipsw/dts/lan9696-tactical-1000.dts | 834 ++++++++++++++++++ target/linux/microchipsw/image/lan969x.mk | 23 + .../lan969x/base-files/etc/board.d/01_leds | 3 +- .../lan969x/base-files/etc/board.d/02_network | 3 +- .../base-files/lib/upgrade/platform.sh | 6 +- 8 files changed, 1057 insertions(+), 6 deletions(-) create mode 100644 package/boot/arm-trusted-firmware-microchipsw/patches/0001-microchip-lan969x-add-Novarq-Tactical-1000-v3.patch create mode 100644 target/linux/microchipsw/dts/lan9696-tactical-1000.dts diff --git a/package/boot/arm-trusted-firmware-microchipsw/Makefile b/package/boot/arm-trusted-firmware-microchipsw/Makefile index 75fb0b7ef95..0095cc1c382 100644 --- a/package/boot/arm-trusted-firmware-microchipsw/Makefile +++ b/package/boot/arm-trusted-firmware-microchipsw/Makefile @@ -28,7 +28,17 @@ define Trusted-Firmware-A/ev23x71a DEPENDS:=+u-boot-ev23x71a endef -TFA_TARGETS:= ev23x71a +define Trusted-Firmware-A/tactical-1000 + NAME:=Novarq Tactical 1000 + BUILD_SUBTARGET:=lan969x + BUILD_DEVICES:=novarq_tactical-1000 + PLAT:=novarq_tactical_1000_v3 + DEPENDS:=+u-boot-tactical-1000 +endef + +TFA_TARGETS:= \ + ev23x71a \ + tactical-1000 MBEDTLS_NAME:=mbedtls MBEDTLS_RELEASE:=2.28.10 diff --git a/package/boot/arm-trusted-firmware-microchipsw/patches/0001-microchip-lan969x-add-Novarq-Tactical-1000-v3.patch b/package/boot/arm-trusted-firmware-microchipsw/patches/0001-microchip-lan969x-add-Novarq-Tactical-1000-v3.patch new file mode 100644 index 00000000000..a0e83c0059f --- /dev/null +++ b/package/boot/arm-trusted-firmware-microchipsw/patches/0001-microchip-lan969x-add-Novarq-Tactical-1000-v3.patch @@ -0,0 +1,171 @@ +From 190202583edb9dcab5ca49638169d08a332f0fdf Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sun, 2 Nov 2025 16:57:45 +0100 +Subject: [PATCH] microchip: lan969x: add Novarq Tactical 1000 v3 + +Add support for Novarq Tactical 1000 v3 board as a separate platform since +it uses 2GB of RAM and requires a different RAM configuration. + +Signed-off-by: Robert Marko +--- + .../fdts/lan969x-tactical-1000-v3-ddr.dtsi | 90 +++++++++++++++++++ + .../novarq_tactical_1000_v3_tb_fw_config.dts | 30 +++++++ + .../novarq_tactical_1000_v3/platform.mk | 12 +++ + scripts/fwu/fwu.js | 2 +- + 4 files changed, 133 insertions(+), 1 deletion(-) + create mode 100644 plat/microchip/lan969x/fdts/lan969x-tactical-1000-v3-ddr.dtsi + create mode 100644 plat/microchip/lan969x/novarq_tactical_1000_v3/fdts/novarq_tactical_1000_v3_tb_fw_config.dts + create mode 100644 plat/microchip/lan969x/novarq_tactical_1000_v3/platform.mk + +--- /dev/null ++++ b/plat/microchip/lan969x/fdts/lan969x-tactical-1000-v3-ddr.dtsi +@@ -0,0 +1,90 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries. ++ * ++ */ ++ ++&ddr { ++ microchip,mem-name = "lan969x_tactical_1000_2gb 2025-11-02-13:03:23 7391dfb-dirty"; ++ microchip,mem-speed = <2400>; ++ microchip,mem-size = <0x80000000>; ++ microchip,mem-bus-width = <16>; ++ ++ microchip,main-reg = < ++ 0x00001091 /* crcparctl1 */ ++ 0x00000001 /* dbictl */ ++ 0x00000040 /* dfimisc */ ++ 0x0391820f /* dfitmg0 */ ++ 0x00040201 /* dfitmg1 */ ++ 0x40400003 /* dfiupd0 */ ++ 0x004000ff /* dfiupd1 */ ++ 0x003f7f40 /* ecccfg0 */ ++ 0x00020248 /* init0 */ ++ 0x00e80000 /* init1 */ ++ 0x0c340101 /* init3 */ ++ 0x10180200 /* init4 */ ++ 0x00110000 /* init5 */ ++ 0x00000402 /* init6 */ ++ 0x00000c19 /* init7 */ ++ 0x81040010 /* mstr */ ++ 0x00000000 /* pccfg */ ++ 0x00000000 /* pwrctl */ ++ 0x00210020 /* rfshctl0 */ ++ 0x00000000 /* rfshctl3 */ ++ >; ++ ++ microchip,timing-reg = < ++ 0x17131413 /* dramtmg0 */ ++ 0x0007051b /* dramtmg1 */ ++ 0x1a000010 /* dramtmg12 */ ++ 0x090b0512 /* dramtmg2 */ ++ 0x0000400c /* dramtmg3 */ ++ 0x08040409 /* dramtmg4 */ ++ 0x07070404 /* dramtmg5 */ ++ 0x07060c0b /* dramtmg8 */ ++ 0x0003040d /* dramtmg9 */ ++ 0x07000610 /* odtcfg */ ++ 0x0049014b /* rfshtmg */ ++ >; ++ ++ microchip,mapping-reg = < ++ 0x0000001f /* addrmap0 */ ++ 0x003f0909 /* addrmap1 */ ++ 0x00000700 /* addrmap2 */ ++ 0x00000000 /* addrmap3 */ ++ 0x00001f1f /* addrmap4 */ ++ 0x07070707 /* addrmap5 */ ++ 0x07070707 /* addrmap6 */ ++ 0x00000f07 /* addrmap7 */ ++ 0x00003f01 /* addrmap8 */ ++ >; ++ ++ microchip,phy-reg = < ++ 0x0000040c /* dcr */ ++ 0x0064401b /* dsgcr */ ++ 0x8000b0cf /* dtcr0 */ ++ 0x00010a37 /* dtcr1 */ ++ 0x00c01884 /* dxccr */ ++ 0x000010ba /* pgcr2 */ ++ 0x00000000 /* schcr1 */ ++ 0x00079900 /* zq0pr */ ++ 0x10077900 /* zq1pr */ ++ 0x00000000 /* zq2pr */ ++ 0x00058f00 /* zqcr */ ++ >; ++ ++ microchip,phy_timing-reg = < ++ 0x0827100a /* dtpr0 */ ++ 0x28250018 /* dtpr1 */ ++ 0x000702a1 /* dtpr2 */ ++ 0x03000101 /* dtpr3 */ ++ 0x02950808 /* dtpr4 */ ++ 0x00361009 /* dtpr5 */ ++ 0x4ae25710 /* ptr0 */ ++ 0x74f4950e /* ptr1 */ ++ 0x00083def /* ptr2 */ ++ 0x2a192000 /* ptr3 */ ++ 0x1003a000 /* ptr4 */ ++ >; ++ ++}; +--- /dev/null ++++ b/plat/microchip/lan969x/novarq_tactical_1000_v3/fdts/novarq_tactical_1000_v3_tb_fw_config.dts +@@ -0,0 +1,30 @@ ++/* ++ * Copyright (c) 2022, Microchip Technology Inc. and its subsidiaries. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++/dts-v1/; ++ ++#include "lan969x.dtsi" ++#include "lan969x-tactical-1000-v3-ddr.dtsi" ++ ++&emmc_clk { ++ clock-frequency = <100000000>; ++}; ++ ++&sdmmc0 { ++ status = "okay"; ++ bus-width = <8>; ++}; ++ ++&qspi0 { ++ status = "okay"; ++ spi-flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <100000000>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; ++ }; ++}; +--- /dev/null ++++ b/plat/microchip/lan969x/novarq_tactical_1000_v3/platform.mk +@@ -0,0 +1,12 @@ ++# ++# Copyright (c) 2021, Microchip Technology Inc. and its subsidiaries. ++# ++# SPDX-License-Identifier: BSD-3-Clause ++# ++ ++include plat/microchip/lan969x/common/common.mk ++ ++# This is used in lan969x code ++$(eval $(call add_define,LAN969X_ASIC)) ++# This is used in common drivers ++$(eval $(call add_define,LAN966X_ASIC)) +--- a/scripts/fwu/fwu.js ++++ b/scripts/fwu/fwu.js +@@ -91,7 +91,7 @@ const platforms = [ + "ddr_diag": ddr_diag_regs_lan969x, + "ddr_regs": ddr_regs_lan969x, + "ddr_speed": lan969x_speeds, +- "bl2u_compat": ["lan969x_a0", "lan969x_svb"], ++ "bl2u_compat": ["lan969x_a0", "lan969x_svb", "novarq_tactical_1000_v3"], + }, + ]; + diff --git a/package/boot/uboot-microchipsw/Makefile b/package/boot/uboot-microchipsw/Makefile index f7277392767..8e241a00d22 100644 --- a/package/boot/uboot-microchipsw/Makefile +++ b/package/boot/uboot-microchipsw/Makefile @@ -27,7 +27,16 @@ define U-Boot/ev23x71a UBOOT_CONFIG:=mchp_lan969x endef -UBOOT_TARGETS:= ev23x71a +define U-Boot/tactical-1000 + NAME:=Novarq Tactical 1000 + BUILD_DEVICES:=novarq_tactical-1000 + BUILD_SUBTARGET:=lan969x + UBOOT_CONFIG:=mchp_lan969x +endef + +UBOOT_TARGETS:= \ + ev23x71a \ + tactical-1000 define Build/InstallDev $(INSTALL_DIR) $(STAGING_DIR_IMAGE) diff --git a/target/linux/microchipsw/dts/lan9696-tactical-1000.dts b/target/linux/microchipsw/dts/lan9696-tactical-1000.dts new file mode 100644 index 00000000000..1ee1d3ab55c --- /dev/null +++ b/target/linux/microchipsw/dts/lan9696-tactical-1000.dts @@ -0,0 +1,834 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) + +/dts-v1/; + +#include +#include +#include +#include "lan9691.dtsi" + +/ { + model = "Novarq Tactical 1000"; + compatible = "novarq,tactical-1000", "microchip,lan9696", "microchip,lan9691"; + + aliases { + serial0 = &usart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpu_gpio_pwm: pwm { + compatible = "pwm-gpio"; + gpios = <&gpio 25 GPIO_ACTIVE_LOW>; + #pwm-cells = <3>; + }; + + cpu_fan: cpu-pwm-fan { + compatible = "pwm-fan"; + pinctrl-names = "default"; + pinctrl-0 = <&fan_pins>; + pwms = <&cpu_gpio_pwm 0 40000 0>; + }; + + case_fan: case-gpio-fan { + compatible = "gpio-fan"; + #cooling-cells = <2>; + gpios = <&gpio 59 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0>, + <2000 1>; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 60 GPIO_ACTIVE_LOW>; + open-source; + priority = <200>; + }; + + i2c-mux { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c3>; + idle-state = <0x8>; + mux-gpios = <&sgpio_out 0 1 GPIO_ACTIVE_HIGH>, + <&sgpio_out 0 2 GPIO_ACTIVE_HIGH>, + <&sgpio_out 0 3 GPIO_ACTIVE_HIGH>; + settle-time-us = <100>; + + i2c_sfp0: i2c@0 { + reg = <0x0>; + }; + + i2c_sfp1: i2c@1 { + reg = <0x1>; + }; + + i2c_sfp2: i2c@2 { + reg = <0x2>; + }; + + i2c_sfp3: i2c@3 { + reg = <0x3>; + }; + + i2c_rtc: i2c@4 { + reg = <0x4>; + #address-cells = <1>; + #size-cells = <0>; + + rtc@6f { + compatible = "microchip,mcp7940x"; + reg = <0x6f>; + }; + }; + + i2c_tmp: i2c@6 { + reg = <0x6>; + #address-cells = <1>; + #size-cells = <0>; + + temperature-sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + }; + }; + + i2c_poe: i2c@7 { + reg = <0x7>; + }; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + key-reset { + label = "reset"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-status { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio 61 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-sfp1-green { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + gpios = <&sgpio_out 6 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-sfp1-yellow { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + gpios = <&sgpio_out 6 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-sfp2-green { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + gpios = <&sgpio_out 7 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-sfp2-yellow { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + gpios = <&sgpio_out 7 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-sfp3-green { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + gpios = <&sgpio_out 8 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-sfp3-yellow { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + gpios = <&sgpio_out 8 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-sfp4-green { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <3>; + gpios = <&sgpio_out 9 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-sfp4-yellow { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <3>; + gpios = <&sgpio_out 9 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + sfp0: sfp0 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp0>; + tx-disable-gpios = <&sgpio_out 6 2 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in 6 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 6 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 6 2 GPIO_ACTIVE_HIGH>; + }; + + sfp1: sfp1 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp1>; + tx-disable-gpios = <&sgpio_out 7 2 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in 7 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 7 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 7 2 GPIO_ACTIVE_HIGH>; + }; + + sfp2: sfp2 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp2>; + tx-disable-gpios = <&sgpio_out 8 2 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in 8 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 8 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 8 2 GPIO_ACTIVE_HIGH>; + }; + + sfp3: sfp3 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp3>; + tx-disable-gpios = <&sgpio_out 9 2 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in 9 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 9 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 9 2 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpio { + button_pins: button-pins { + pins = "GPIO_2"; + function = "gpio"; + }; + + case_fan_pins: case-fan-pins { + pins = "GPIO_59"; + function = "gpio"; + }; + + emmc_sd_pins: emmc-sd-pins { + /* eMMC_SD - CMD, CLK, D0, D1, D2, D3, D4, D5, D6, D7, RSTN */ + pins = "GPIO_14", "GPIO_15", "GPIO_16", "GPIO_17", + "GPIO_18", "GPIO_19", "GPIO_20", "GPIO_21", + "GPIO_22", "GPIO_23", "GPIO_24"; + function = "emmc_sd"; + }; + + fan_pins: fan-pins { + pins = "GPIO_25", "GPIO_26"; + function = "gpio"; + }; + + fc0_pins: fc0-pins { + pins = "GPIO_3", "GPIO_4"; + function = "fc"; + }; + + + fc2_pins: fc2-pins { + pins = "GPIO_65", "GPIO_66"; + function = "fc"; + }; + + fc3_pins: fc3-pins { + pins = "GPIO_55", "GPIO_56"; + function = "fc"; + }; + + mdio_pins: mdio-pins { + pins = "GPIO_9", "GPIO_10"; + function = "miim"; + }; + + mdio_irq_pins: mdio-irq-pins { + pins = "GPIO_11"; + function = "miim_irq"; + }; + + sgpio_pins: sgpio-pins { + /* SCK, D0, D1, LD */ + pins = "GPIO_5", "GPIO_6", "GPIO_7", "GPIO_8"; + function = "sgpio_a"; + }; + + usb_ulpi_pins: usb-ulpi-pins { + pins = "GPIO_30", "GPIO_31", "GPIO_32", "GPIO_33", + "GPIO_34", "GPIO_35", "GPIO_36", "GPIO_37", + "GPIO_38", "GPIO_39", "GPIO_40", "GPIO_41"; + function = "usb_ulpi"; + }; + + usb_rst_pins: usb-rst-pins { + pins = "GPIO_12"; + function = "usb2phy_rst"; + }; + + usb_over_pins: usb-over-pins { + pins = "GPIO_13"; + function = "usb_over_detect"; + }; + + usb_power_pins: usb-power-pins { + pins = "GPIO_1"; + function = "usb_power"; + }; +}; + +&flx0 { + atmel,flexcom-mode = ; + status = "okay"; +}; + +&flx2 { + atmel,flexcom-mode = ; + status = "okay"; +}; + +&flx3 { + atmel,flexcom-mode = ; + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&fc2_pins>; + pinctrl-names = "default"; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + i2c-sda-hold-time-ns = <1500>; + status = "okay"; + + /* ATECC608C lives here on 0x60 */ +}; + +&i2c3 { + pinctrl-0 = <&fc3_pins>; + pinctrl-names = "default"; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + i2c-sda-hold-time-ns = <1500>; + status = "okay"; +}; + +&mdio0 { + pinctrl-0 = <&mdio_pins>, <&mdio_irq_pins>; + pinctrl-names = "default"; + reset-gpios = <&gpio 62 GPIO_ACTIVE_LOW>; + status = "okay"; + + phy3: phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy4: phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy5: phy@5 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy6: phy@6 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <6>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy7: phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy8: phy@8 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <8>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy9: phy@9 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <9>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy10: phy@10 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <10>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy11: phy@11 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <11>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy12: phy@12 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <12>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy13: phy@13 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <13>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy14: phy@14 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <14>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy15: phy@15 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <15>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy16: phy@16 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <16>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy17: phy@17 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <17>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy18: phy@18 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <18>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy19: phy@19 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <19>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy20: phy@20 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <20>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy21: phy@21 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <21>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy22: phy@22 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <22>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy23: phy@23 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <23>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy24: phy@24 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <24>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy25: phy@25 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <25>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy26: phy@26 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <26>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy27: phy@27 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <27>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; +}; + +&qspi0 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + #address-cells = <1>; + #size-cells = <1>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + m25p,fast-read; + }; +}; + +&serdes { + status = "okay"; +}; + +&sdmmc0 { + pinctrl-0 = <&emmc_sd_pins>; + pinctrl-names = "default"; + max-frequency = <100000000>; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + disable-wp; + status = "okay"; +}; + +&serdes { + status = "okay"; +}; + +&sgpio { + pinctrl-0 = <&sgpio_pins>; + pinctrl-names = "default"; + microchip,sgpio-port-ranges = <0 1>, <6 9>; + status = "okay"; + + gpio@0 { + ngpios = <128>; + }; + gpio@1 { + ngpios = <128>; + }; +}; + +&switch { + status = "okay"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port0: port@0 { + reg = <0>; + phy-handle = <&phy4>; + phy-mode = "qsgmii"; + phys = <&serdes 0>; + microchip,bandwidth = <1000>; + }; + + port1: port@1 { + reg = <1>; + phy-handle = <&phy5>; + phy-mode = "qsgmii"; + phys = <&serdes 0>; + microchip,bandwidth = <1000>; + }; + + port2: port@2 { + reg = <2>; + phy-handle = <&phy6>; + phy-mode = "qsgmii"; + phys = <&serdes 0>; + microchip,bandwidth = <1000>; + }; + + port3: port@3 { + reg = <3>; + phy-handle = <&phy7>; + phy-mode = "qsgmii"; + phys = <&serdes 0>; + microchip,bandwidth = <1000>; + }; + + port4: port@4 { + reg = <4>; + phy-handle = <&phy8>; + phy-mode = "qsgmii"; + phys = <&serdes 1>; + microchip,bandwidth = <1000>; + }; + + port5: port@5 { + reg = <5>; + phy-handle = <&phy9>; + phy-mode = "qsgmii"; + phys = <&serdes 1>; + microchip,bandwidth = <1000>; + }; + + port6: port@6 { + reg = <6>; + phy-handle = <&phy10>; + phy-mode = "qsgmii"; + phys = <&serdes 1>; + microchip,bandwidth = <1000>; + }; + + port7: port@7 { + reg = <7>; + phy-handle = <&phy11>; + phy-mode = "qsgmii"; + phys = <&serdes 1>; + microchip,bandwidth = <1000>; + }; + + port8: port@8 { + reg = <8>; + phy-handle = <&phy12>; + phy-mode = "qsgmii"; + phys = <&serdes 2>; + microchip,bandwidth = <1000>; + }; + + port9: port@9 { + reg = <9>; + phy-handle = <&phy13>; + phy-mode = "qsgmii"; + phys = <&serdes 2>; + microchip,bandwidth = <1000>; + }; + + port10: port@10 { + reg = <10>; + phy-handle = <&phy14>; + phy-mode = "qsgmii"; + phys = <&serdes 2>; + microchip,bandwidth = <1000>; + }; + + port11: port@11 { + reg = <11>; + phy-handle = <&phy15>; + phy-mode = "qsgmii"; + phys = <&serdes 2>; + microchip,bandwidth = <1000>; + }; + + port12: port@12 { + reg = <12>; + phy-handle = <&phy16>; + phy-mode = "qsgmii"; + phys = <&serdes 3>; + microchip,bandwidth = <1000>; + }; + + port13: port@13 { + reg = <13>; + phy-handle = <&phy17>; + phy-mode = "qsgmii"; + phys = <&serdes 3>; + microchip,bandwidth = <1000>; + }; + + port14: port@14 { + reg = <14>; + phy-handle = <&phy18>; + phy-mode = "qsgmii"; + phys = <&serdes 3>; + microchip,bandwidth = <1000>; + }; + + port15: port@15 { + reg = <15>; + phy-handle = <&phy19>; + phy-mode = "qsgmii"; + phys = <&serdes 3>; + microchip,bandwidth = <1000>; + }; + + port16: port@16 { + reg = <16>; + phy-handle = <&phy20>; + phy-mode = "qsgmii"; + phys = <&serdes 4>; + microchip,bandwidth = <1000>; + }; + + port17: port@17 { + reg = <17>; + phy-handle = <&phy21>; + phy-mode = "qsgmii"; + phys = <&serdes 4>; + microchip,bandwidth = <1000>; + }; + + port18: port@18 { + reg = <18>; + phy-handle = <&phy22>; + phy-mode = "qsgmii"; + phys = <&serdes 4>; + microchip,bandwidth = <1000>; + }; + + port19: port@19 { + reg = <19>; + phy-handle = <&phy23>; + phy-mode = "qsgmii"; + phys = <&serdes 4>; + microchip,bandwidth = <1000>; + }; + + port20: port@20 { + reg = <20>; + phy-handle = <&phy24>; + phy-mode = "qsgmii"; + phys = <&serdes 5>; + microchip,bandwidth = <1000>; + }; + + port21: port@21 { + reg = <21>; + phy-handle = <&phy25>; + phy-mode = "qsgmii"; + phys = <&serdes 5>; + microchip,bandwidth = <1000>; + }; + + port22: port@22 { + reg = <22>; + phy-handle = <&phy26>; + phy-mode = "qsgmii"; + phys = <&serdes 5>; + microchip,bandwidth = <1000>; + }; + + port23: port@23 { + reg = <23>; + phy-handle = <&phy27>; + phy-mode = "qsgmii"; + phys = <&serdes 5>; + microchip,bandwidth = <1000>; + }; + + port24: port@24 { + reg = <24>; + phys = <&serdes 6>; + phy-mode = "10gbase-r"; + sfp = <&sfp0>; + managed = "in-band-status"; + microchip,bandwidth = <10000>; + microchip,sd-sgpio = <24>; + }; + + port25: port@25 { + reg = <25>; + phys = <&serdes 7>; + phy-mode = "10gbase-r"; + sfp = <&sfp1>; + managed = "in-band-status"; + microchip,bandwidth = <10000>; + microchip,sd-sgpio = <28>; + }; + + port26: port@26 { + reg = <26>; + phys = <&serdes 8>; + phy-mode = "10gbase-r"; + sfp = <&sfp2>; + managed = "in-band-status"; + microchip,bandwidth = <10000>; + microchip,sd-sgpio = <32>; + }; + + port27: port@27 { + reg = <27>; + phys = <&serdes 9>; + phy-mode = "10gbase-r"; + sfp = <&sfp3>; + managed = "in-band-status"; + microchip,bandwidth = <10000>; + microchip,sd-sgpio = <36>; + }; + + port29: port@29 { + reg = <29>; + phys = <&serdes 11>; + phy-handle = <&phy3>; + phy-mode = "rgmii-id"; + microchip,bandwidth = <1000>; + }; + }; +}; + +&usart0 { + pinctrl-0 = <&fc0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb { + pinctrl-0 = <&usb_ulpi_pins>, <&usb_rst_pins>, <&usb_over_pins>, <&usb_power_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/target/linux/microchipsw/image/lan969x.mk b/target/linux/microchipsw/image/lan969x.mk index 04b681b017d..bbcf1807bc8 100644 --- a/target/linux/microchipsw/image/lan969x.mk +++ b/target/linux/microchipsw/image/lan969x.mk @@ -39,3 +39,26 @@ define Device/microchip_ev23x71a gzip endef TARGET_DEVICES += microchip_ev23x71a + +define Device/novarq_tactical-1000 + $(call Device/FitImage) + DEVICE_VENDOR := Novarq + DEVICE_MODEL := Tactical 1000 + SOC := lan9696 + DEVICE_PACKAGES := kmod-i2c-mux-gpio \ + kmod-gpio-pwm kmod-hwmon-pwmfan kmod-hwmon-gpiofan \ + kmod-rtc-ds1307 kmod-hwmon-lm75 + IMAGES += emmc-atf-gpt.gz emmc-gpt.img.gz + IMAGE/emmc-atf-gpt.gz := lan969x-gpt-emmc |\ + pad-to 1M | lan969x-fip tactical-1000 |\ + pad-to 9M | lan969x-fip tactical-1000 |\ + gzip + IMAGE/emmc-gpt.img.gz := lan969x-gpt-emmc flash |\ + pad-to 1M | lan969x-fip tactical-1000 |\ + pad-to 9M | lan969x-fip tactical-1000 |\ + pad-to 19M | append-kernel-part |\ + append-rootfs |\ + gzip + SUPPORTED_DEVICES += novarq,tactical-1000-v3 +endef +TARGET_DEVICES += novarq_tactical-1000 diff --git a/target/linux/microchipsw/lan969x/base-files/etc/board.d/01_leds b/target/linux/microchipsw/lan969x/base-files/etc/board.d/01_leds index 6e3da9e0ec2..7ec67e695ff 100644 --- a/target/linux/microchipsw/lan969x/base-files/etc/board.d/01_leds +++ b/target/linux/microchipsw/lan969x/base-files/etc/board.d/01_leds @@ -6,7 +6,8 @@ board_config_update board=$(board_name) case "$board" in -microchip,ev23x71a) +microchip,ev23x71a|\ +novarq,tactical-1000) ucidef_set_led_netdev "sfp1-link" "SFP1-LINK" "green:lan-0" "eth24" "link" ucidef_set_led_netdev "sfp1-traffic" "SFP1-TRAFFIC" "yellow:lan-0" "eth24" "tx rx" ucidef_set_led_netdev "sfp2-link" "SFP2-LINK" "green:lan-1" "eth25" "link" diff --git a/target/linux/microchipsw/lan969x/base-files/etc/board.d/02_network b/target/linux/microchipsw/lan969x/base-files/etc/board.d/02_network index be28e56192d..fcf03f88a36 100644 --- a/target/linux/microchipsw/lan969x/base-files/etc/board.d/02_network +++ b/target/linux/microchipsw/lan969x/base-files/etc/board.d/02_network @@ -7,7 +7,8 @@ lan969x_setup_interfaces() local board="$1" case "$board" in - microchip,ev23x71a) + microchip,ev23x71a|\ + novarq,tactical-1000) lan_list=$(ls -1 -v -d /sys/class/net/eth* | xargs -n1 basename | xargs) ucidef_set_interface_lan "$lan_list" ;; diff --git a/target/linux/microchipsw/lan969x/base-files/lib/upgrade/platform.sh b/target/linux/microchipsw/lan969x/base-files/lib/upgrade/platform.sh index a3d4b488f0f..b5a37c1975b 100644 --- a/target/linux/microchipsw/lan969x/base-files/lib/upgrade/platform.sh +++ b/target/linux/microchipsw/lan969x/base-files/lib/upgrade/platform.sh @@ -10,7 +10,8 @@ platform_check_image() { platform_do_upgrade() { case "$(board_name)" in - microchip,ev23x71a) + microchip,ev23x71a|\ + novarq,tactical-1000) CI_KERNPART="kernel" CI_ROOTPART="rootfs" emmc_do_upgrade "$1" @@ -23,7 +24,8 @@ platform_do_upgrade() { platform_copy_config() { case "$(board_name)" in - microchip,ev23x71a) + microchip,ev23x71a|\ + novarq,tactical-1000) emmc_copy_config ;; esac -- 2.47.3