From d1a9f876f3265577b5a1881dbc1e428c04c8808f Mon Sep 17 00:00:00 2001 From: =?utf8?q?Linus=20L=C3=BCssing?= Date: Wed, 7 May 2025 18:40:40 +0200 Subject: [PATCH] realtek: replace additional "magic numbers" with macros MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Increase readability by replacing more numbers and bit operations with macros in order to give them distinct, expressive names. Signed-off-by: Linus Lüssing Link: https://github.com/openwrt/openwrt/pull/21786 Signed-off-by: Robert Marko --- .../drivers/net/dsa/rtl83xx/common.c | 8 +-- .../files-6.12/drivers/net/dsa/rtl83xx/dsa.c | 6 +- .../drivers/net/dsa/rtl83xx/rtl838x.c | 24 ++++--- .../drivers/net/dsa/rtl83xx/rtl838x.h | 65 ++++++++++++++++++- .../drivers/net/dsa/rtl83xx/rtl839x.c | 24 ++++--- .../drivers/net/dsa/rtl83xx/rtl930x.c | 28 ++++---- .../drivers/net/dsa/rtl83xx/rtl931x.c | 39 ++++++----- 7 files changed, 137 insertions(+), 57 deletions(-) diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c index 8340d218241..a24009ecd6c 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c @@ -1417,7 +1417,7 @@ static int rtl83xx_sw_probe(struct platform_device *pdev) priv->port_width = 1; priv->irq_mask = 0x0FFFFFFF; priv->r = &rtl838x_reg; - priv->ds->num_ports = 29; + priv->ds->num_ports = RTL838X_CPU_PORT + 1; priv->fib_entries = 8192; priv->ds->num_lag_ids = 8; priv->l2_bucket_size = 4; @@ -1433,7 +1433,7 @@ static int rtl83xx_sw_probe(struct platform_device *pdev) priv->port_width = 2; priv->irq_mask = 0xFFFFFFFFFFFFFULL; priv->r = &rtl839x_reg; - priv->ds->num_ports = 53; + priv->ds->num_ports = RTL839X_CPU_PORT + 1; priv->fib_entries = 16384; priv->ds->num_lag_ids = 16; priv->l2_bucket_size = 4; @@ -1449,7 +1449,7 @@ static int rtl83xx_sw_probe(struct platform_device *pdev) priv->port_width = 1; priv->irq_mask = 0x0FFFFFFF; priv->r = &rtl930x_reg; - priv->ds->num_ports = 29; + priv->ds->num_ports = RTL930X_CPU_PORT + 1; priv->fib_entries = 16384; priv->ds->num_lag_ids = 16; sw_w32(0, RTL930X_ST_CTRL); @@ -1466,7 +1466,7 @@ static int rtl83xx_sw_probe(struct platform_device *pdev) priv->port_width = 2; priv->irq_mask = GENMASK_ULL(priv->cpu_port - 1, 0); priv->r = &rtl931x_reg; - priv->ds->num_ports = 57; + priv->ds->num_ports = RTL931X_CPU_PORT + 1; priv->fib_entries = 16384; priv->ds->num_lag_ids = 16; sw_w32(0, RTL931x_ST_CTRL); diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c index 597d2f9dcdb..29052ff1b91 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c @@ -456,7 +456,7 @@ static void rtldsa_vlan_setup(struct rtl838x_switch_priv *priv) priv->r->vlan_profile_setup(0); priv->r->vlan_profile_setup(1); - pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK)); + dev_info(priv->dev, "MC_PMASK_ALL_PORTS: %016llx\n", priv->r->read_mcast_pmask(MC_PMASK_ALL_PORTS_IDX)); priv->r->vlan_profile_dump(0); info.fid = 0; /* Default Forwarding ID / MSTI */ @@ -2107,7 +2107,7 @@ static int rtldsa_vlan_add(struct dsa_switch *ds, int port, if (!vlan->vid) return 0; - if (vlan->vid > 4095) { + if (vlan->vid >= MAX_VLANS) { dev_err(priv->dev, "VLAN out of range: %d", vlan->vid); return -ENOTSUPP; } @@ -2179,7 +2179,7 @@ static int rtldsa_vlan_del(struct dsa_switch *ds, int port, if (!vlan->vid) return 0; - if (vlan->vid > 4095) { + if (vlan->vid >= MAX_VLANS) { dev_err(priv->dev, "VLAN out of range: %d", vlan->vid); return -ENOTSUPP; } diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.c index 284c08177b9..e0014c4ffca 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.c +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.c @@ -192,7 +192,7 @@ static void rtl838x_vlan_set_untagged(u32 vlan, u64 portmask) /* Access UNTAG table (0) via register 1 */ struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 0); - sw_w32(portmask & 0x1fffffff, rtl_table_data(r, 0)); + sw_w32(portmask & RTL838X_MC_PMASK_ALL_PORTS, rtl_table_data(r, 0)); rtl_table_write(r, vlan); rtl_table_release(r); } @@ -485,16 +485,17 @@ static void rtl838x_write_mcast_pmask(int idx, u64 portmask) /* Access MC_PMSK (2) via register RTL8380_TBL_L2 */ struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 2); - sw_w32(((u32)portmask) & 0x1fffffff, rtl_table_data(q, 0)); + sw_w32(((u32)portmask) & RTL838X_MC_PMASK_ALL_PORTS, rtl_table_data(q, 0)); rtl_table_write(q, idx); rtl_table_release(q); } static void rtl838x_vlan_profile_setup(int profile) { - u32 pmask_id = UNKNOWN_MC_PMASK; - /* Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for unknown MC traffic flooding */ - u32 p = 1 | pmask_id << 1 | pmask_id << 10 | pmask_id << 19; + u32 p = RTL838X_VLAN_L2_LEARN_EN(1) | + RTL838X_VLAN_L2_UNKN_MC_FLD(MC_PMASK_ALL_PORTS_IDX) | + RTL838X_VLAN_IP4_UNKN_MC_FLD(MC_PMASK_ALL_PORTS_IDX) | + RTL838X_VLAN_IP6_UNKN_MC_FLD(MC_PMASK_ALL_PORTS_IDX); sw_w32(p, RTL838X_VLAN_PROFILE(profile)); @@ -503,7 +504,7 @@ static void rtl838x_vlan_profile_setup(int profile) * On RTL93XX, the portmask is directly set in the profile, * see e.g. rtl9300_vlan_profile_setup */ - rtl838x_write_mcast_pmask(UNKNOWN_MC_PMASK, 0x1fffffff); + rtl838x_write_mcast_pmask(MC_PMASK_ALL_PORTS_IDX, RTL838X_MC_PMASK_ALL_PORTS); } static void rtl838x_l2_learning_setup(void) @@ -512,7 +513,9 @@ static void rtl838x_l2_learning_setup(void) * to the reserved entry in the portmask table used also for * multicast flooding */ - sw_w32(UNKNOWN_MC_PMASK << 9 | UNKNOWN_MC_PMASK, RTL838X_L2_FLD_PMSK); + sw_w32(RTL838X_L2_BC_FLD(MC_PMASK_ALL_PORTS_IDX) | + RTL838X_L2_UNKN_UC_FLD(MC_PMASK_ALL_PORTS_IDX), + RTL838X_L2_FLD_PMSK); /* Enable learning constraint system-wide (bit 0), per-port (bit 1) * and per vlan (bit 2) @@ -1779,12 +1782,15 @@ void rtl838x_vlan_profile_dump(int profile) { u32 p; - if (profile < 0 || profile > 7) + if (profile < 0 || profile > RTL838X_VLAN_PROFILE_MAX) return; p = sw_r32(RTL838X_VLAN_PROFILE(profile)); pr_debug("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d\n", - profile, p & 1, (p >> 1) & 0x1ff, (p >> 10) & 0x1ff, (p >> 19) & 0x1ff); + profile, RTL838X_VLAN_L2_LEARN_EN_R(p), + RTL838X_VLAN_L2_UNKN_MC_FLD_PMSK(p), + RTL838X_VLAN_IP4_UNKN_MC_FLD_PMSK(p), + RTL838X_VLAN_IP6_UNKN_MC_FLD_PMSK(p)); } diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.h b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.h index 02df5f4ecfd..2d87eacdbb7 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.h +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.h @@ -3,6 +3,7 @@ #ifndef _RTL838X_H #define _RTL838X_H +#include #include /* Register definition */ @@ -45,28 +46,73 @@ /* VLAN registers */ #define RTL838X_VLAN_CTRL (0x3A74) #define RTL838X_VLAN_PROFILE(idx) (0x3A88 + ((idx) << 2)) +#define RTL838X_VLAN_PROFILE_MAX 7 #define RTL838X_VLAN_PORT_EGR_FLTR (0x3A84) #define RTL838X_VLAN_PORT_PB_VLAN (0x3C00) #define RTL838X_VLAN_PORT_IGR_FLTR (0x3A7C) +#define RTL838X_VLAN_L2_LEARN_EN(i) (i) +#define RTL838X_VLAN_L2_UNKN_MC_FLD(pmsk) (pmsk << 1) +#define RTL838X_VLAN_IP4_UNKN_MC_FLD(pmsk) (pmsk << 10) +#define RTL838X_VLAN_IP6_UNKN_MC_FLD(pmsk) (pmsk << 19) + +#define RTL838X_VLAN_L2_LEARN_EN_R(p) (p & RTL838X_VLAN_L2_LEARN_EN(1)) +#define RTL838X_VLAN_L2_UNKN_MC_FLD_PMSK(p) ((p >> 1) & (MAX_MC_PMASKS - 1)) +#define RTL838X_VLAN_IP4_UNKN_MC_FLD_PMSK(p) ((p >> 10) & (MAX_MC_PMASKS - 1)) +#define RTL838X_VLAN_IP6_UNKN_MC_FLD_PMSK(p) ((p >> 19) & (MAX_MC_PMASKS - 1)) + #define RTL839X_VLAN_PROFILE(idx) (0x25C0 + (((idx) << 3))) +#define RTL839X_VLAN_PROFILE_MAX 7 #define RTL839X_VLAN_CTRL (0x26D4) #define RTL839X_VLAN_PORT_PB_VLAN (0x26D8) #define RTL839X_VLAN_PORT_IGR_FLTR (0x27B4) #define RTL839X_VLAN_PORT_EGR_FLTR (0x27C4) +#define RTL839X_VLAN_L2_LEARN_EN(i) (i) +#define RTL839X_VLAN_L2_UNKN_MC_FLD(pmsk) (pmsk << 1) +#define RTL839X_VLAN_IP4_UNKN_MC_FLD(pmsk) (pmsk << 13) +#define RTL839X_VLAN_IP6_UNKN_MC_FLD(pmsk) (pmsk) + +#define RTL839X_VLAN_L2_LEARN_EN_R(p) (p[1] & RTL839X_VLAN_L2_LEARN_EN(1)) +#define RTL839X_VLAN_L2_UNKN_MC_FLD_PMSK(p) ((p[1] >> 1) & (MAX_MC_PMASKS - 1)) +#define RTL839X_VLAN_IP4_UNKN_MC_FLD_PMSK(p) ((p[1] >> 13) & (MAX_MC_PMASKS - 1)) +#define RTL839X_VLAN_IP6_UNKN_MC_FLD_PMSK(p) ((p[0]) & (MAX_MC_PMASKS - 1)) + #define RTL930X_VLAN_PROFILE_SET(idx) (0x9c60 + (((idx) * 20))) +#define RTL930X_VLAN_PROFILE_MAX 7 #define RTL930X_VLAN_CTRL (0x82D4) #define RTL930X_VLAN_PORT_PB_VLAN (0x82D8) #define RTL930X_VLAN_PORT_IGR_FLTR (0x83C0) #define RTL930X_VLAN_PORT_EGR_FLTR (0x83C8) +#define RTL930X_VLAN_L2_UNKN_MC_FLD(pmsk) (pmsk) +#define RTL930X_VLAN_IP4_UNKN_MC_FLD(pmsk) (pmsk) +#define RTL930X_VLAN_IP6_UNKN_MC_FLD(pmsk) (pmsk) + +#define RTL930X_VLAN_L2_LEARN_EN_R(p) (p[0] & (3 << 21)) +#define RTL930X_VLAN_L2_UNKN_MC_FLD_PMSK(p) (p[2] & RTL930X_MC_PMASK_ALL_PORTS) +#define RTL930X_VLAN_IP4_UNKN_MC_FLD_PMSK(p) (p[3] & RTL930X_MC_PMASK_ALL_PORTS) +#define RTL930X_VLAN_IP6_UNKN_MC_FLD_PMSK(p) (p[4] & RTL930X_MC_PMASK_ALL_PORTS) + #define RTL931X_VLAN_PROFILE_SET(idx) (0x9800 + (((idx) * 28))) +#define RTL931X_VLAN_PROFILE_MAX 15 #define RTL931X_VLAN_CTRL (0x94E4) #define RTL931X_VLAN_PORT_IGR_CTRL (0x94E8) #define RTL931X_VLAN_PORT_IGR_FLTR (0x96B4) #define RTL931X_VLAN_PORT_EGR_FLTR (0x96C4) +#define RTL931X_VLAN_L2_UNKN_MC_FLD_H(pmsk) (((u64)pmsk) >> 32) +#define RTL931X_VLAN_L2_UNKN_MC_FLD_L(pmsk) (pmsk & GENMASK_ULL(31, 0)) +#define RTL931X_VLAN_IP4_UNKN_MC_FLD_H(pmsk) (((u64)pmsk) >> 32) +#define RTL931X_VLAN_IP4_UNKN_MC_FLD_L(pmsk) (pmsk & GENMASK_ULL(31, 0)) +#define RTL931X_VLAN_IP6_UNKN_MC_FLD_H(pmsk) (((u64)pmsk) >> 32) +#define RTL931X_VLAN_IP6_UNKN_MC_FLD_L(pmsk) (pmsk & GENMASK_ULL(31, 0)) + +#define RTL931X_VLAN_L2_LEARN_EN_R(p) (p[0] & (3 << 14)) +#define RTL931X_VLAN_L2_UNKN_MC_FLD_PMSK(p) ((((u64)p[1]) << 32 | p[2]) & RTL931X_MC_PMASK_ALL_PORTS) +#define RTL931X_VLAN_IP4_UNKN_MC_FLD_PMSK(p) ((((u64)p[3]) << 32 | p[4]) & RTL931X_MC_PMASK_ALL_PORTS) +#define RTL931X_VLAN_IP6_UNKN_MC_FLD_PMSK(p) ((((u64)p[5]) << 32 | p[6]) & RTL931X_MC_PMASK_ALL_PORTS) + /* Table access registers */ #define RTL838X_TBL_ACCESS_CTRL_0 (0x6914) #define RTL838X_TBL_ACCESS_DATA_0(idx) (0x6918 + ((idx) << 2)) @@ -207,6 +253,11 @@ #define RTL930X_L2_UNKN_UC_FLD_PMSK (0x9064) #define RTL931X_L2_UNKN_UC_FLD_PMSK (0xC8F4) +#define RTL838X_L2_BC_FLD(pmsk) (pmsk << 9) +#define RTL838X_L2_UNKN_UC_FLD(pmsk) (pmsk) +#define RTL839X_L2_BC_FLD(pmsk) (pmsk << 12) +#define RTL839X_L2_UNKN_UC_FLD(pmsk) (pmsk) + #define RTL838X_L2_LRN_CONSTRT_EN (0x3368) #define RTL838X_L2_PORT_LRN_CONSTRT (0x32A0) #define RTL839X_L2_PORT_LRN_CONSTRT (0x3914) @@ -701,8 +752,20 @@ typedef enum { #define MAX_LAGS 16 #define MAX_PRIOS 8 #define RTL930X_PORT_IGNORE 0x3f +/* ToDo: MAX_MC_GROUPS could be increased + * 838x/839x/930x/931x -> 8192/16384/16384/32768 entries (priv->fib_entries) + * They are shared with unicast entries + */ #define MAX_MC_GROUPS 512 -#define UNKNOWN_MC_PMASK (MAX_MC_GROUPS - 1) +/* ToDo: MAX_MC_PMASKS could be increased + * 838x/839x/930x/931x -> 512/4096/1024/4096 entries + */ +#define MAX_MC_PMASKS 512 +#define RTL838X_MC_PMASK_ALL_PORTS (GENMASK(RTL838X_CPU_PORT, 0)) +#define RTL839X_MC_PMASK_ALL_PORTS (GENMASK_ULL(RTL839X_CPU_PORT, 0)) +#define RTL930X_MC_PMASK_ALL_PORTS (GENMASK(RTL930X_CPU_PORT, 0)) +#define RTL931X_MC_PMASK_ALL_PORTS (GENMASK_ULL(RTL931X_CPU_PORT, 0)) +#define MC_PMASK_ALL_PORTS_IDX ((MAX_MC_PMASKS - 1)) #define PIE_BLOCK_SIZE 128 #define MAX_PIE_ENTRIES (18 * PIE_BLOCK_SIZE) #define N_FIXED_FIELDS 12 diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl839x.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl839x.c index 72ca80c7350..ff47950cb90 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl839x.c +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl839x.c @@ -521,17 +521,17 @@ static void rtl839x_write_mcast_pmask(int idx, u64 portmask) static void rtl839x_vlan_profile_setup(int profile) { - u32 p[2]; - u32 pmask_id = UNKNOWN_MC_PMASK; + u32 p[2] = { 0, 0 }; - p[0] = pmask_id; /* Use portmaks 0xfff for unknown IPv6 MC flooding */ - /* Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for IP/L2-MC traffic flooding */ - p[1] = 1 | pmask_id << 1 | pmask_id << 13; + p[1] = RTL839X_VLAN_L2_LEARN_EN(1); + p[1] |= RTL839X_VLAN_L2_UNKN_MC_FLD(MC_PMASK_ALL_PORTS_IDX) | + RTL839X_VLAN_IP4_UNKN_MC_FLD(MC_PMASK_ALL_PORTS_IDX); + p[0] |= RTL839X_VLAN_IP6_UNKN_MC_FLD(MC_PMASK_ALL_PORTS_IDX); sw_w32(p[0], RTL839X_VLAN_PROFILE(profile)); sw_w32(p[1], RTL839X_VLAN_PROFILE(profile) + 4); - rtl839x_write_mcast_pmask(UNKNOWN_MC_PMASK, 0x001fffffffffffff); + rtl839x_write_mcast_pmask(MC_PMASK_ALL_PORTS_IDX, RTL839X_MC_PMASK_ALL_PORTS); } static void rtl839x_traffic_set(int source, u64 dest_matrix) @@ -555,7 +555,9 @@ static void rtl839x_l2_learning_setup(void) * address flooding to the reserved entry in the portmask table used * also for multicast flooding */ - sw_w32(UNKNOWN_MC_PMASK << 12 | UNKNOWN_MC_PMASK, RTL839X_L2_FLD_PMSK); + sw_w32(RTL839X_L2_BC_FLD(MC_PMASK_ALL_PORTS_IDX) | + RTL839X_L2_UNKN_UC_FLD(MC_PMASK_ALL_PORTS_IDX), + RTL839X_L2_FLD_PMSK); /* Limit learning to maximum: 32k entries, after that just flood (bits 0-1) */ sw_w32((0x7fff << 2) | 0, RTL839X_L2_LRN_CONSTRT); @@ -628,15 +630,17 @@ void rtl839x_vlan_profile_dump(int profile) { u32 p[2]; - if (profile < 0 || profile > 7) + if (profile < 0 || profile > RTL839X_VLAN_PROFILE_MAX) return; p[0] = sw_r32(RTL839X_VLAN_PROFILE(profile)); p[1] = sw_r32(RTL839X_VLAN_PROFILE(profile) + 4); pr_debug("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d\n", - profile, p[1] & 1, (p[1] >> 1) & 0xfff, (p[1] >> 13) & 0xfff, - (p[0]) & 0xfff); + profile, RTL839X_VLAN_L2_LEARN_EN_R(p), + RTL839X_VLAN_L2_UNKN_MC_FLD_PMSK(p), + RTL839X_VLAN_IP4_UNKN_MC_FLD_PMSK(p), + RTL839X_VLAN_IP6_UNKN_MC_FLD_PMSK(p)); pr_debug("VLAN profile %d: raw %08x, %08x\n", profile, p[0], p[1]); } diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl930x.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl930x.c index fbf21c07ca0..6d9bb3ac2f6 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl930x.c +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl930x.c @@ -310,17 +310,20 @@ void rtl930x_vlan_profile_dump(int profile) { u32 p[5]; - if (profile < 0 || profile > 7) + if (profile < 0 || profile > RTL930X_VLAN_PROFILE_MAX) return; p[0] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile)); p[1] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 4); - p[2] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 8) & 0x1FFFFFFF; - p[3] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 12) & 0x1FFFFFFF; - p[4] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 16) & 0x1FFFFFFF; - - pr_debug("VLAN %d: L2 learn: %d; Unknown MC PMasks: L2 %0x, IPv4 %0x, IPv6: %0x", - profile, p[0] & (3 << 21), p[2], p[3], p[4]); + p[2] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 8); + p[3] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 12); + p[4] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 16); + + pr_debug("VLAN %d: L2 learn: %d; Unknown MC PMasks: L2 %0lx, IPv4 %0lx, IPv6: %0lx", + profile, RTL930X_VLAN_L2_LEARN_EN_R(p), + RTL930X_VLAN_L2_UNKN_MC_FLD_PMSK(p), + RTL930X_VLAN_IP4_UNKN_MC_FLD_PMSK(p), + RTL930X_VLAN_IP6_UNKN_MC_FLD_PMSK(p)); pr_debug(" Routing enabled: IPv4 UC %c, IPv6 UC %c, IPv4 MC %c, IPv6 MC %c\n", p[0] & BIT(17) ? 'y' : 'n', p[0] & BIT(16) ? 'y' : 'n', p[0] & BIT(13) ? 'y' : 'n', p[0] & BIT(12) ? 'y' : 'n'); @@ -359,9 +362,10 @@ static void rtl930x_vlan_profile_setup(int profile) /* Enable routing of Ipv4/6 Unicast and IPv4/6 Multicast traffic */ p[0] |= BIT(17) | BIT(16) | BIT(13) | BIT(12); - p[2] = 0x1fffffff; /* L2 unknown MC flooding portmask all ports, including the CPU-port */ - p[3] = 0x1fffffff; /* IPv4 unknown MC flooding portmask */ - p[4] = 0x1fffffff; /* IPv6 unknown MC flooding portmask */ + + p[2] = RTL930X_VLAN_L2_UNKN_MC_FLD(RTL930X_MC_PMASK_ALL_PORTS); + p[3] = RTL930X_VLAN_IP4_UNKN_MC_FLD(RTL930X_MC_PMASK_ALL_PORTS); + p[4] = RTL930X_VLAN_IP6_UNKN_MC_FLD(RTL930X_MC_PMASK_ALL_PORTS); sw_w32(p[0], RTL930X_VLAN_PROFILE_SET(profile)); sw_w32(p[1], RTL930X_VLAN_PROFILE_SET(profile) + 4); @@ -373,10 +377,10 @@ static void rtl930x_vlan_profile_setup(int profile) static void rtl930x_l2_learning_setup(void) { /* Portmask for flooding broadcast traffic */ - sw_w32(0x1fffffff, RTL930X_L2_BC_FLD_PMSK); + sw_w32(RTL930X_MC_PMASK_ALL_PORTS, RTL930X_L2_BC_FLD_PMSK); /* Portmask for flooding unicast traffic with unknown destination */ - sw_w32(0x1fffffff, RTL930X_L2_UNKN_UC_FLD_PMSK); + sw_w32(RTL930X_MC_PMASK_ALL_PORTS, RTL930X_L2_UNKN_UC_FLD_PMSK); /* Limit learning to maximum: 32k entries, after that just flood (bits 0-1) */ sw_w32((0x7fff << 2) | 0, RTL930X_L2_LRN_CONSTRT_CTRL); diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl931x.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl931x.c index 0ea628defc3..415cd0faedf 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl931x.c +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl931x.c @@ -139,21 +139,24 @@ inline int rtl931x_tbl_access_data_0(int i) static void rtl931x_vlan_profile_dump(int index) { - u64 profile[4]; + u32 p[7]; - if (index < 0 || index > 15) + if (index < 0 || index > RTL931X_VLAN_PROFILE_MAX) return; - profile[0] = sw_r32(RTL931X_VLAN_PROFILE_SET(index)); - profile[1] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 4) & 0x1FFFFFFFULL) << 32 | - (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 8) & 0xFFFFFFFF); - profile[2] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 12) & 0x1FFFFFFFULL) << 32 | - (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 16) & 0xFFFFFFFF); - profile[3] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 20) & 0x1FFFFFFFULL) << 32 | - (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 24) & 0xFFFFFFFF); + p[0] = sw_r32(RTL931X_VLAN_PROFILE_SET(index)); + p[1] = sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 4); + p[2] = sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 8); + p[3] = sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 12); + p[4] = sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 16); + p[5] = sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 20); + p[6] = sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 24); pr_debug("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %llx, IPv4 Unknown MultiCast Field %llx, IPv6 Unknown MultiCast Field: %llx\n", - index, (u32)(profile[0] & (3 << 14)), profile[1], profile[2], profile[3]); + index, RTL931X_VLAN_L2_LEARN_EN_R(p), + RTL931X_VLAN_L2_UNKN_MC_FLD_PMSK(p), + RTL931X_VLAN_IP4_UNKN_MC_FLD_PMSK(p), + RTL931X_VLAN_IP6_UNKN_MC_FLD_PMSK(p)); } static int rtldsa_931x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, int port, u32 port_state[]) @@ -809,12 +812,12 @@ static void rtl931x_vlan_profile_setup(int profile) /* p[0] |= BIT(17) | BIT(16) | BIT(13) | BIT(12); */ p[0] |= 0x3 << 11; /* COPY2CPU */ - p[1] = 0x1FFFFFF; /* L2 unknwon MC flooding portmask all ports, including the CPU-port */ - p[2] = 0xFFFFFFFF; - p[3] = 0x1FFFFFF; /* IPv4 unknwon MC flooding portmask */ - p[4] = 0xFFFFFFFF; - p[5] = 0x1FFFFFF; /* IPv6 unknwon MC flooding portmask */ - p[6] = 0xFFFFFFFF; + p[1] = RTL931X_VLAN_L2_UNKN_MC_FLD_H(RTL931X_MC_PMASK_ALL_PORTS); + p[2] = RTL931X_VLAN_L2_UNKN_MC_FLD_L(RTL931X_MC_PMASK_ALL_PORTS); + p[3] = RTL931X_VLAN_IP4_UNKN_MC_FLD_H(RTL931X_MC_PMASK_ALL_PORTS); + p[4] = RTL931X_VLAN_IP4_UNKN_MC_FLD_L(RTL931X_MC_PMASK_ALL_PORTS); + p[5] = RTL931X_VLAN_IP6_UNKN_MC_FLD_H(RTL931X_MC_PMASK_ALL_PORTS); + p[6] = RTL931X_VLAN_IP6_UNKN_MC_FLD_L(RTL931X_MC_PMASK_ALL_PORTS); for (int i = 0; i < 7; i++) sw_w32(p[i], RTL931X_VLAN_PROFILE_SET(profile) + i * 4); @@ -824,10 +827,10 @@ static void rtl931x_vlan_profile_setup(int profile) static void rtl931x_l2_learning_setup(void) { /* Portmask for flooding broadcast traffic */ - rtl839x_set_port_reg_be(0x1FFFFFFFFFFFFFF, RTL931X_L2_BC_FLD_PMSK); + rtl839x_set_port_reg_be(RTL931X_MC_PMASK_ALL_PORTS, RTL931X_L2_BC_FLD_PMSK); /* Portmask for flooding unicast traffic with unknown destination */ - rtl839x_set_port_reg_be(0x1FFFFFFFFFFFFFF, RTL931X_L2_UNKN_UC_FLD_PMSK); + rtl839x_set_port_reg_be(RTL931X_MC_PMASK_ALL_PORTS, RTL931X_L2_UNKN_UC_FLD_PMSK); /* Limit learning to maximum: 64k entries, after that just flood (bits 0-2) */ sw_w32((0xffff << 3) | FORWARD, RTL931X_L2_LRN_CONSTRT_CTRL); -- 2.47.3