From 47ce4d8a718de4ca94d6a8e50e657479a8d81b41 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Bj=C3=B8rn=20Mork?= Date: Wed, 4 Feb 2026 16:02:08 +0100 Subject: [PATCH] realtek: dsa: rtl838x: drop redundant SMI_GLB_CTRL accesses MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Bit 15 of the rtl838x SMI_GLB_CTRL register is set early during mdio reset and never cleared. There is no need to set it again. Signed-off-by: Bjørn Mork Link: https://github.com/openwrt/openwrt/pull/21868 Signed-off-by: Robert Marko --- .../realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c | 9 ++------- .../realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c | 2 -- 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c index a24009ecd6c..8ed55f55d79 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c @@ -366,14 +366,9 @@ static int rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv) /* Disable MAC polling the PHY so that we can start configuration */ priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl); - /* Enable PHY control via SoC */ - if (priv->family_id == RTL8380_FAMILY_ID) { - /* Enable PHY control by telling SoC that "PHY patching is done" */ - sw_w32_mask(0, BIT(15), RTL838X_SMI_GLB_CTRL); - } else if (priv->family_id == RTL8390_FAMILY_ID) { - /* Disable PHY polling via SoC */ + /* Disable PHY polling via SoC */ + if (priv->family_id == RTL8390_FAMILY_ID) sw_w32_mask(BIT(7), 0, RTL839X_SMI_GLB_CTRL); - } return 0; } diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c index 29052ff1b91..d33e0fa449e 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c @@ -60,8 +60,6 @@ static void rtldsa_enable_phy_polling(struct rtl838x_switch_priv *priv) /* PHY update complete, there is no global PHY polling enable bit on the 93xx */ if (priv->family_id == RTL8390_FAMILY_ID) sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL); - else if (priv->family_id == RTL8380_FAMILY_ID) - sw_w32_mask(0, BIT(15), RTL838X_SMI_GLB_CTRL); } const struct rtldsa_mib_list_item rtldsa_838x_mib_list[] = { -- 2.47.3