From 01fb4a6daadb5814099bc2c401a6a0310287850b Mon Sep 17 00:00:00 2001 From: Kenneth Kasilag Date: Thu, 5 Feb 2026 23:48:07 +0000 Subject: [PATCH] qualcommbe: update pwm patches and add missing symbol Update PWM patch set to v20 which resolves some bugs related to the duty cycle / frequency calculation; and add missing config symbol CONFIG_PWM. Fixes: #21727 Signed-off-by: Kenneth Kasilag Link: https://github.com/openwrt/openwrt/pull/21889 Signed-off-by: Robert Marko --- target/linux/qualcommbe/config-6.12 | 1 + ...river-for-qualcomm-ipq6018-pwm-block.patch | 314 ++++++------------ ...-arm64-dts-qcom-ipq9574-add-pwm-node.patch | 95 +++--- 3 files changed, 149 insertions(+), 261 deletions(-) diff --git a/target/linux/qualcommbe/config-6.12 b/target/linux/qualcommbe/config-6.12 index 39fef151ed4..a65d1856a68 100644 --- a/target/linux/qualcommbe/config-6.12 +++ b/target/linux/qualcommbe/config-6.12 @@ -397,6 +397,7 @@ CONFIG_POWER_RESET=y CONFIG_POWER_SUPPLY=y CONFIG_PRINTK_TIME=y CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PWM=y CONFIG_PWM_IPQ=y CONFIG_QCA807X_PHY=y CONFIG_QCA808X_PHY=y diff --git a/target/linux/qualcommbe/patches-6.12/0375-pwm-driver-for-qualcomm-ipq6018-pwm-block.patch b/target/linux/qualcommbe/patches-6.12/0375-pwm-driver-for-qualcomm-ipq6018-pwm-block.patch index 367349657e6..670b360e985 100644 --- a/target/linux/qualcommbe/patches-6.12/0375-pwm-driver-for-qualcomm-ipq6018-pwm-block.patch +++ b/target/linux/qualcommbe/patches-6.12/0375-pwm-driver-for-qualcomm-ipq6018-pwm-block.patch @@ -1,92 +1,90 @@ -From patchwork Fri Nov 28 10:29:14 2025 +From patchwork Wed Feb 4 11:25:08 2026 Content-Type: text/plain; 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+ Wed, 4 Feb 2026 11:25:13 +0000 (UTC) From: George Moussalem via B4 Relay -Date: Fri, 28 Nov 2025 14:29:14 +0400 -Subject: [PATCH v19 2/6] pwm: driver for qualcomm ipq6018 pwm block +Date: Wed, 04 Feb 2026 15:25:08 +0400 +Subject: [PATCH v20 2/6] pwm: driver for qualcomm ipq6018 pwm block Precedence: bulk X-Mailing-List: linux-pwm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 -Message-Id: <20251128-ipq-pwm-v19-2-13bc704cc6a5@outlook.com> -References: <20251128-ipq-pwm-v19-0-13bc704cc6a5@outlook.com> -In-Reply-To: <20251128-ipq-pwm-v19-0-13bc704cc6a5@outlook.com> +Message-Id: <20260204-ipq-pwm-v20-2-91733011a3d1@outlook.com> +References: <20260204-ipq-pwm-v20-0-91733011a3d1@outlook.com> +In-Reply-To: <20260204-ipq-pwm-v20-0-91733011a3d1@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , @@ -98,11 +96,11 @@ Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, Devi Priya , Baruch Siach X-Mailer: b4 0.14.2 -X-Developer-Signature: v=1; a=ed25519-sha256; t=1764325760; l=12302; +X-Developer-Signature: v=1; a=ed25519-sha256; t=1770204310; l=9677; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; - bh=ECLgbGQXvQqaCHleNN2KaOI3IfiJYGfU1o7zDHbZOZo=; - b=vPkUe390XfPgnR9A+4cm/jNIETdu3JSzsxMjDjX/DTB7RqMnFGjoy8Nh/xGoBmr00hGJQY3dW - bPY4a3duJVOAtYeG1EbsRAywjXTrIxNLun6ElJfCqutCXvpOyMkvWn0 + bh=lqVC0W9FHdaTi1eT81frsdr/MvrSo0xMFV72k7YrO7I=; + b=mcjrEkuzodOMpsOdLZkQ609EXbJZFxJ8sU8yRwppwYWMDGETj4y5NtRIMVLi7GxOiU0zqcWls + CZHLZJaNDRaCaTzN1DMBfmpBhwkY/Hu+GKk+Nh9uBfpU2UxvCU4SSmG X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 @@ -124,118 +122,6 @@ Signed-off-by: Devi Priya Reviewed-by: Bjorn Andersson Signed-off-by: George Moussalem --- -v18: - - Added hardware notes and limitations based on own findings as - requested. NOTE: there's no publically available datasheet though. - - Expanded comment on REG1_UPDATE to indicate that when this bit is set, - values for div and pre-div take effect. The hardware automatically - unsets it when the change is completed. - - Added newline between MACRO definition and next comment - - In config_div_and_duty, used mul_u64_u64_div_u64 to avoid overflow - - Removed unncessary restriction of pwm_div to MAX_DIV - 1 after testing - - Constrain pre_div to MAX_DIV is pre_div calculated is > MAX_DIV - - Use of mul_u64_u64_div_u64 in .apply - - Skip calculation of period and duty cycle when PWM_ENABLE REG is unset - - Set duty cycle to period value when calculated duty cycle > period to - return a valid config - - Removed .npwm as it's taken care of in devm_pwmchip_alloc - - Added call to devm_clk_rate_exclusive_get to lock the clock rate - - Start all kernel messages with a capital letter and end with \n. - -v17: - - Removed unnecessary code comments - -v16: - - Simplified code to calculate divs and duty cycle as per Uwe's comments - - Removed unused pwm_chip struct from ipq_pwm_chip struct - - Removed unnecessary cast as per Uwe's comment - - Replaced devm_clk_get & clk_prepare_enable by devm_clk_get_enabled - - Replaced pwmchip_add by devm_pwmchip_add and removed .remove function - - Removed .owner from driver struct - -v15: - - No change - -v14: - - Picked up the R-b tag - -v13: - - Updated the file name to match the compatible - - Sorted the properties and updated the order in the required field - - Dropped the syscon node from examples - -v12: - - Picked up the R-b tag - -v11: - - No change - -v10: - - No change - -v9: - - Add 'ranges' property to example (Rob) - - Drop label in example (Rob) - -v8: - - Add size cell to 'reg' (Rob) - -v7: - - Use 'reg' instead of 'offset' (Rob) - - Drop 'clock-names' and 'assigned-clock*' (Bjorn) - - Use single cell address/size in example node (Bjorn) - - Move '#pwm-cells' lower in example node (Bjorn) - - List 'reg' as required - -v6: - - Device node is child of TCSR; remove phandle (Rob Herring) - - Add assigned-clocks/assigned-clock-rates (Uwe Kleine-König) - -v5: Use qcom,pwm-regs for phandle instead of direct regs (Bjorn - Andersson, Kathiravan T) - -v4: Update the binding example node as well (Rob Herring's bot) - -v3: s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring) - -v2: Make #pwm-cells const (Rob Herring) --- drivers/pwm/Kconfig | 12 +++ drivers/pwm/Makefile | 1 + @@ -312,12 +198,6 @@ v2: Make #pwm-cells const (Rob Herring) +#define IPQ_PWM_MAX_PERIOD_NS ((u64)NSEC_PER_SEC) + +/* -+ * The max value specified for each field is based on the number of bits -+ * in the pwm control register for that field -+ */ -+#define IPQ_PWM_MAX_DIV 0xFFFF -+ -+/* + * Two 32-bit registers for each PWM: REG0, and REG1. + * Base offset for PWM #i is at 8 * #i. + */ @@ -329,6 +209,12 @@ v2: Make #pwm-cells const (Rob Herring) +#define IPQ_PWM_REG1_PRE_DIV GENMASK(15, 0) + +/* ++ * The max value specified for each field is based on the number of bits ++ * in the pwm control register for that field (16-bit) ++ */ ++#define IPQ_PWM_MAX_DIV FIELD_MAX(IPQ_PWM_REG0_PWM_DIV) ++ ++/* + * Enable bit is set to enable output toggling in pwm device. + * Update bit is set to trigger the change and is unset automatically + * to reflect the changed divider and high duration values in register. @@ -337,8 +223,8 @@ v2: Make #pwm-cells const (Rob Herring) +#define IPQ_PWM_REG1_ENABLE BIT(31) + +struct ipq_pwm_chip { -+ struct clk *clk; + void __iomem *mem; ++ unsigned long clk_rate; +}; + +static struct ipq_pwm_chip *ipq_pwm_from_chip(struct pwm_chip *chip) @@ -363,57 +249,55 @@ v2: Make #pwm-cells const (Rob Herring) + writel(val, ipq_chip->mem + off); +} + -+static void config_div_and_duty(struct pwm_device *pwm, unsigned int pre_div, -+ unsigned int pwm_div, unsigned long rate, u64 duty_ns, -+ bool enable) -+{ -+ unsigned long hi_dur; -+ unsigned long val = 0; -+ -+ /* -+ * high duration = pwm duty * (pwm div + 1) -+ * pwm duty = duty_ns / period_ns -+ */ -+ hi_dur = mul_u64_u64_div_u64(duty_ns, rate, (pre_div + 1) * NSEC_PER_SEC); -+ -+ val = FIELD_PREP(IPQ_PWM_REG0_HI_DURATION, hi_dur) | -+ FIELD_PREP(IPQ_PWM_REG0_PWM_DIV, pwm_div); -+ ipq_pwm_reg_write(pwm, IPQ_PWM_REG0, val); -+ -+ val = FIELD_PREP(IPQ_PWM_REG1_PRE_DIV, pre_div); -+ ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val); -+ -+ /* PWM enable toggle needs a separate write to REG1 */ -+ val |= IPQ_PWM_REG1_UPDATE; -+ if (enable) -+ val |= IPQ_PWM_REG1_ENABLE; -+ ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val); -+} -+ +static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct ipq_pwm_chip *ipq_chip = ipq_pwm_from_chip(chip); -+ unsigned long rate = clk_get_rate(ipq_chip->clk); + unsigned int pre_div, pwm_div; + u64 period_ns, duty_ns; ++ unsigned long val = 0; ++ unsigned long hi_dur; + + if (state->polarity != PWM_POLARITY_NORMAL) + return -EINVAL; + -+ if (state->period < DIV64_U64_ROUND_UP(NSEC_PER_SEC, rate)) ++ if (!ipq_chip->clk_rate) ++ return -EINVAL; ++ ++ if (state->period < DIV64_U64_ROUND_UP(NSEC_PER_SEC, ++ ipq_chip->clk_rate)) + return -ERANGE; + + period_ns = min(state->period, IPQ_PWM_MAX_PERIOD_NS); + duty_ns = min(state->duty_cycle, period_ns); + -+ pwm_div = IPQ_PWM_MAX_DIV; -+ pre_div = mul_u64_u64_div_u64(period_ns, rate, (u64)NSEC_PER_SEC * (pwm_div + 1)); ++ pwm_div = IPQ_PWM_MAX_DIV - 1; ++ pre_div = mul_u64_u64_div_u64(period_ns, ipq_chip->clk_rate, ++ (u64)NSEC_PER_SEC * (pwm_div + 1)); ++ pre_div = (pre_div > 0) ? pre_div - 1 : 0; + + if (pre_div > IPQ_PWM_MAX_DIV) + pre_div = IPQ_PWM_MAX_DIV; + -+ config_div_and_duty(pwm, pre_div, pwm_div, rate, duty_ns, state->enabled); ++ /* ++ * high duration = pwm duty * (pwm div + 1) ++ * pwm duty = duty_ns / period_ns ++ */ ++ hi_dur = mul_u64_u64_div_u64(duty_ns, ipq_chip->clk_rate, ++ (u64)(pre_div + 1) * NSEC_PER_SEC); ++ ++ val = FIELD_PREP(IPQ_PWM_REG0_HI_DURATION, hi_dur) | ++ FIELD_PREP(IPQ_PWM_REG0_PWM_DIV, pwm_div); ++ ipq_pwm_reg_write(pwm, IPQ_PWM_REG0, val); ++ ++ val = FIELD_PREP(IPQ_PWM_REG1_PRE_DIV, pre_div); ++ ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val); ++ ++ /* PWM enable toggle needs a separate write to REG1 */ ++ val |= IPQ_PWM_REG1_UPDATE; ++ if (state->enabled) ++ val |= IPQ_PWM_REG1_ENABLE; ++ ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val); + + return 0; +} @@ -422,7 +306,6 @@ v2: Make #pwm-cells const (Rob Herring) + struct pwm_state *state) +{ + struct ipq_pwm_chip *ipq_chip = ipq_pwm_from_chip(chip); -+ unsigned long rate = clk_get_rate(ipq_chip->clk); + unsigned int pre_div, pwm_div, hi_dur; + u64 effective_div, hi_div; + u32 reg0, reg1; @@ -441,12 +324,13 @@ v2: Make #pwm-cells const (Rob Herring) + hi_dur = FIELD_GET(IPQ_PWM_REG0_HI_DURATION, reg0); + pre_div = FIELD_GET(IPQ_PWM_REG1_PRE_DIV, reg1); + -+ /* No overflow here, both pre_div and pwm_div <= 0xffff */ -+ effective_div = (pre_div + 1) * (pwm_div + 1); -+ state->period = DIV64_U64_ROUND_UP(effective_div * NSEC_PER_SEC, rate); ++ effective_div = (u64)(pre_div + 1) * (pwm_div + 1); ++ state->period = DIV64_U64_ROUND_UP(effective_div * NSEC_PER_SEC, ++ ipq_chip->clk_rate); + + hi_div = hi_dur * (pre_div + 1); -+ state->duty_cycle = DIV64_U64_ROUND_UP(hi_div * NSEC_PER_SEC, rate); ++ state->duty_cycle = DIV64_U64_ROUND_UP(hi_div * NSEC_PER_SEC, ++ ipq_chip->clk_rate); + + /* + * ensure a valid config is passed back to PWM core in case duty_cycle @@ -467,6 +351,7 @@ v2: Make #pwm-cells const (Rob Herring) + struct device *dev = &pdev->dev; + struct ipq_pwm_chip *pwm; + struct pwm_chip *chip; ++ struct clk *clk; + int ret; + + chip = devm_pwmchip_alloc(dev, 4, sizeof(*pwm)); @@ -477,17 +362,18 @@ v2: Make #pwm-cells const (Rob Herring) + pwm->mem = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pwm->mem)) + return dev_err_probe(dev, PTR_ERR(pwm->mem), -+ "Failed to acquire resource\n"); ++ "Failed to acquire resource\n"); + -+ pwm->clk = devm_clk_get_enabled(dev, NULL); -+ if (IS_ERR(pwm->clk)) -+ return dev_err_probe(dev, PTR_ERR(pwm->clk), -+ "Failed to get clock\n"); ++ clk = devm_clk_get_enabled(dev, NULL); ++ if (IS_ERR(clk)) ++ return dev_err_probe(dev, PTR_ERR(clk), ++ "Failed to get clock\n"); + -+ ret = devm_clk_rate_exclusive_get(dev, pwm->clk); ++ ret = devm_clk_rate_exclusive_get(dev, clk); + if (ret) -+ return dev_err_probe(dev, ret, -+ "Failed to lock clock rate\n"); ++ return dev_err_probe(dev, ret, "Failed to lock clock rate\n"); ++ ++ pwm->clk_rate = clk_get_rate(clk); + + chip->ops = &ipq_pwm_ops; + @@ -495,7 +381,7 @@ v2: Make #pwm-cells const (Rob Herring) + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to add pwm chip\n"); + -+ return ret; ++ return 0; +} + +static const struct of_device_id pwm_ipq_dt_match[] = { diff --git a/target/linux/qualcommbe/patches-6.12/0376-arm64-dts-qcom-ipq9574-add-pwm-node.patch b/target/linux/qualcommbe/patches-6.12/0376-arm64-dts-qcom-ipq9574-add-pwm-node.patch index 9519307e486..011433c6ddb 100644 --- a/target/linux/qualcommbe/patches-6.12/0376-arm64-dts-qcom-ipq9574-add-pwm-node.patch +++ b/target/linux/qualcommbe/patches-6.12/0376-arm64-dts-qcom-ipq9574-add-pwm-node.patch @@ -1,91 +1,91 @@ -From patchwork Fri Nov 28 10:29:18 2025 +From patchwork Wed Feb 4 11:25:12 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem via B4 Relay -X-Patchwork-Id: 2169930 +X-Patchwork-Id: 2192912 Return-Path: - + X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 - header.s=k20201202 header.b=WkpmcfUf; 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+ Wed, 4 Feb 2026 11:25:14 +0000 (UTC) From: George Moussalem via B4 Relay -Date: Fri, 28 Nov 2025 14:29:18 +0400 -Subject: [PATCH v19 6/6] arm64: dts: qcom: ipq9574: add pwm node +Date: Wed, 04 Feb 2026 15:25:12 +0400 +Subject: [PATCH v20 6/6] arm64: dts: qcom: ipq9574: add pwm node Precedence: bulk X-Mailing-List: linux-pwm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 -Message-Id: <20251128-ipq-pwm-v19-6-13bc704cc6a5@outlook.com> -References: <20251128-ipq-pwm-v19-0-13bc704cc6a5@outlook.com> -In-Reply-To: <20251128-ipq-pwm-v19-0-13bc704cc6a5@outlook.com> +Message-Id: <20260204-ipq-pwm-v20-6-91733011a3d1@outlook.com> +References: <20260204-ipq-pwm-v20-0-91733011a3d1@outlook.com> +In-Reply-To: <20260204-ipq-pwm-v20-0-91733011a3d1@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , @@ -96,11 +96,11 @@ Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, George Moussalem , Dmitry Baryshkov X-Mailer: b4 0.14.2 -X-Developer-Signature: v=1; a=ed25519-sha256; t=1764325760; l=1234; +X-Developer-Signature: v=1; a=ed25519-sha256; t=1770204310; l=1234; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; - bh=9v7/UevGH2hUC1+SPEdsNKg4jplKvUQ7JbA9V5V+kSc=; - b=NOosCxAFNtyHdh0CZXQHfKfcI/2XszvFfKQFo7nkdC6jnoLg4o1FtB4hVem3P5EZGMEwz5dQf - 1Uza9u+gHQaDRU17TViI1KBbHu6+42RP25c0lx9nUJyj3NadDr59X8h + bh=1ixhFwq2rEjXYJIhs5+j+ngAUcQh5KQa6+Qdzh8kp4o=; + b=ky+nnCBbPuFce/HNZnz6s4ubdKccwoR4mGT7VVjp1Q+YR30lXS7xluR+rnmLy73TfU2J3/6kO + 144Si65ChORDD0KZk1dvy+masC3Igfhy8O3qYSqMdoqSlttNJsS5eZR X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 @@ -118,6 +118,7 @@ should have its own node. Reviewed-by: Dmitry Baryshkov Signed-off-by: George Moussalem +Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.47.3