git.ipfire.org Git - thirdparty/kernel/stable-queue.git/blob

   1 From f3edf03a4c59e59e52c0c1fd958f64a76a038302 Mon Sep 17 00:00:00 2001
   2 From: Xu Yang <xu.yang_2@nxp.com>
   3 Date: Thu, 12 Dec 2024 14:57:08 +0800
   4 Subject: perf: imx9_perf: Introduce AXI filter version to refactor the driver and better extension
   5
   6 From: Xu Yang <xu.yang_2@nxp.com>
   7
   8 commit f3edf03a4c59e59e52c0c1fd958f64a76a038302 upstream.
   9
  10 The imx93 is the first supported DDR PMU that supports read transaction,
  11 write transaction and read beats events which corresponding respecitively
  12 to counter 2, 3 and 4.
  13
  14 However, transaction-based AXI match has low accuracy when get total bits
  15 compared to beats-based. And imx93 doesn't assign AXI_ID to each master.
  16 So axi filter is not used widely on imx93. This could be regards as AXI
  17 filter version 1.
  18
  19 To improve the AXI filter capability, imx95 supports 1 read beats and 3
  20 write beats event which corresponding respecitively to counter 2-5. imx95
  21 also detailed AXI_ID allocation so that most of the master could be count
  22 individually. This could be regards as AXI filter version 2.
  23
  24 This will introduce AXI filter version to refactor the driver and support
  25 better extension, such as coming imx943. This is also a potential fix on
  26 imx91 when configure axi filter.
  27
  28 Fixes: 44798fe136dc ("perf: imx_perf: add support for i.MX91 platform")
  29 Cc: stable@vger.kernel.org
  30 Reviewed-by: Frank Li <Frank.Li@nxp.com>
  31 Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
  32 Link: https://lore.kernel.org/r/20241212065708.1353513-1-xu.yang_2@nxp.com
  33 Signed-off-by: Will Deacon <will@kernel.org>
  34 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  35 ---
  36  drivers/perf/fsl_imx9_ddr_perf.c |   33 +++++++++++++++++++++++++--------
  37  1 file changed, 25 insertions(+), 8 deletions(-)
  38
  39 --- a/drivers/perf/fsl_imx9_ddr_perf.c
  40 +++ b/drivers/perf/fsl_imx9_ddr_perf.c
  41 @@ -63,8 +63,21 @@
  42
  43  static DEFINE_IDA(ddr_ida);
  44
  45 +/*
  46 + * V1 support 1 read transaction, 1 write transaction and 1 read beats
  47 + * event which corresponding respecitively to counter 2, 3 and 4.
  48 + */
  49 +#define DDR_PERF_AXI_FILTER_V1         0x1
  50 +
  51 +/*
  52 + * V2 support 1 read beats and 3 write beats events which corresponding
  53 + * respecitively to counter 2-5.
  54 + */
  55 +#define DDR_PERF_AXI_FILTER_V2         0x2
  56 +
  57  struct imx_ddr_devtype_data {
  58         const char *identifier;         /* system PMU identifier for userspace */
  59 +       unsigned int filter_ver;        /* AXI filter version */
  60  };
  61
  62  struct ddr_pmu {
  63 @@ -83,24 +96,27 @@ struct ddr_pmu {
  64
  65  static const struct imx_ddr_devtype_data imx91_devtype_data = {
  66         .identifier = "imx91",
  67 +       .filter_ver = DDR_PERF_AXI_FILTER_V1
  68  };
  69
  70  static const struct imx_ddr_devtype_data imx93_devtype_data = {
  71         .identifier = "imx93",
  72 +       .filter_ver = DDR_PERF_AXI_FILTER_V1
  73  };
  74
  75  static const struct imx_ddr_devtype_data imx95_devtype_data = {
  76         .identifier = "imx95",
  77 +       .filter_ver = DDR_PERF_AXI_FILTER_V2
  78  };
  79
  80 -static inline bool is_imx93(struct ddr_pmu *pmu)
  81 +static inline bool axi_filter_v1(struct ddr_pmu *pmu)
  82  {
  83 -       return pmu->devtype_data == &imx93_devtype_data;
  84 +       return pmu->devtype_data->filter_ver == DDR_PERF_AXI_FILTER_V1;
  85  }
  86
  87 -static inline bool is_imx95(struct ddr_pmu *pmu)
  88 +static inline bool axi_filter_v2(struct ddr_pmu *pmu)
  89  {
  90 -       return pmu->devtype_data == &imx95_devtype_data;
  91 +       return pmu->devtype_data->filter_ver == DDR_PERF_AXI_FILTER_V2;
  92  }
  93
  94  static const struct of_device_id imx_ddr_pmu_dt_ids[] = {
  95 @@ -155,7 +171,7 @@ static const struct attribute_group ddr_
  96  struct imx9_pmu_events_attr {
  97         struct device_attribute attr;
  98         u64 id;
  99 -       const void *devtype_data;
 100 +       const struct imx_ddr_devtype_data *devtype_data;
 101  };
 102
 103  static ssize_t ddr_pmu_event_show(struct device *dev,
 104 @@ -307,7 +323,8 @@ ddr_perf_events_attrs_is_visible(struct
 105         if (!eattr->devtype_data)
 106                 return attr->mode;
 107
 108 -       if (eattr->devtype_data != ddr_pmu->devtype_data)
 109 +       if (eattr->devtype_data != ddr_pmu->devtype_data &&
 110 +           eattr->devtype_data->filter_ver != ddr_pmu->devtype_data->filter_ver)
 111                 return 0;
 112
 113         return attr->mode;
 114 @@ -624,11 +641,11 @@ static int ddr_perf_event_add(struct per
 115         hwc->idx = counter;
 116         hwc->state |= PERF_HES_STOPPED;
 117
 118 -       if (is_imx93(pmu))
 119 +       if (axi_filter_v1(pmu))
 120                 /* read trans, write trans, read beat */
 121                 imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2);
 122
 123 -       if (is_imx95(pmu))
 124 +       if (axi_filter_v2(pmu))
 125                 /* write beat, read beat2, read beat1, read beat */
 126                 imx95_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2);
 127