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   1 #ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl2080_ctrl2080internal_h__
   2 #define __src_common_sdk_nvidia_inc_ctrl_ctrl2080_ctrl2080internal_h__
   3
   4 /* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */
   5
   6 /*
   7  * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
   8  * SPDX-License-Identifier: MIT
   9  *
  10  * Permission is hereby granted, free of charge, to any person obtaining a
  11  * copy of this software and associated documentation files (the "Software"),
  12  * to deal in the Software without restriction, including without limitation
  13  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  14  * and/or sell copies of the Software, and to permit persons to whom the
  15  * Software is furnished to do so, subject to the following conditions:
  16  *
  17  * The above copyright notice and this permission notice shall be included in
  18  * all copies or substantial portions of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26  * DEALINGS IN THE SOFTWARE.
  27  */
  28
  29 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO (0x20800a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */
  30
  31 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS {
  32     NvU32  feHwSysCap;
  33     NvU32  windowPresentMask;
  34     NvBool bFbRemapperEnabled;
  35     NvU32  numHeads;
  36     NvBool bPrimaryVga;
  37     NvU32  i2cPort;
  38     NvU32  internalDispActiveMask;
  39 } NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS;
  40
  41 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM (0x20800a49) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID" */
  42
  43 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS {
  44     NV_DECLARE_ALIGNED(NvU64 instMemPhysAddr, 8);
  45     NV_DECLARE_ALIGNED(NvU64 instMemSize, 8);
  46     NvU32 instMemAddrSpace;
  47     NvU32 instMemCpuCacheAttr;
  48 } NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS;
  49
  50 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER (0x20800a58) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID" */
  51
  52 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS {
  53     NvU32  addressSpace;
  54     NV_DECLARE_ALIGNED(NvU64 physicalAddr, 8);
  55     NV_DECLARE_ALIGNED(NvU64 limit, 8);
  56     NvU32  cacheSnoop;
  57     NvU32  hclass;
  58     NvU32  channelInstance;
  59     NvBool valid;
  60 } NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS;
  61
  62 #define NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE (0x20800a5c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID" */
  63
  64 #define NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE       128
  65
  66 typedef enum NV2080_INTR_CATEGORY {
  67     NV2080_INTR_CATEGORY_DEFAULT = 0,
  68     NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE = 1,
  69     NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION = 2,
  70     NV2080_INTR_CATEGORY_RUNLIST = 3,
  71     NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION = 4,
  72     NV2080_INTR_CATEGORY_UVM_OWNED = 5,
  73     NV2080_INTR_CATEGORY_UVM_SHARED = 6,
  74     NV2080_INTR_CATEGORY_ENUM_COUNT = 7,
  75 } NV2080_INTR_CATEGORY;
  76
  77 typedef struct NV2080_INTR_CATEGORY_SUBTREE_MAP {
  78     NvU8 subtreeStart;
  79     NvU8 subtreeEnd;
  80 } NV2080_INTR_CATEGORY_SUBTREE_MAP;
  81
  82 typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY {
  83     NvU16 engineIdx;
  84     NvU32 pmcIntrMask;
  85     NvU32 vectorStall;
  86     NvU32 vectorNonStall;
  87 } NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY;
  88
  89 typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS {
  90     NvU32                                            tableLen;
  91     NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY table[NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE];
  92     NV2080_INTR_CATEGORY_SUBTREE_MAP                 subtreeMap[NV2080_INTR_CATEGORY_ENUM_COUNT];
  93 } NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS;
  94
  95 #define NV2080_CTRL_CMD_INTERNAL_FBSR_INIT (0x20800ac2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID" */
  96
  97 typedef struct NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS {
  98     NvU32    fbsrType;
  99     NvU32    numRegions;
 100     NvHandle hClient;
 101     NvHandle hSysMem;
 102     NV_DECLARE_ALIGNED(NvU64 gspFbAllocsSysOffset, 8);
 103     NvBool   bEnteringGcoffState;
 104 } NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS;
 105
 106 #define NV2080_CTRL_CMD_INTERNAL_FBSR_SEND_REGION_INFO (0x20800ac3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS_MESSAGE_ID" */
 107
 108 typedef struct NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS {
 109     NvU32    fbsrType;
 110     NvHandle hClient;
 111     NvHandle hVidMem;
 112     NV_DECLARE_ALIGNED(NvU64 vidOffset, 8);
 113     NV_DECLARE_ALIGNED(NvU64 sysOffset, 8);
 114     NV_DECLARE_ALIGNED(NvU64 size, 8);
 115 } NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS;
 116
 117 #define NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD (0x20800ac6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID" */
 118
 119 #define NV2080_CTRL_ACPI_DSM_READ_SIZE                   (0x1000) /* finn: Evaluated from "(4 * 1024)" */
 120
 121 typedef struct NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS {
 122     NvU32 status;
 123     NvU16 backLightDataSize;
 124     NvU8  backLightData[NV2080_CTRL_ACPI_DSM_READ_SIZE];
 125 } NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS;
 126
 127 #endif