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1 From: Prajwal Mohan <prajwal.karur.mohan@intel.com>
2 Date: Tue, 27 Apr 2010 11:23:00 -0700
3 Subject: [PATCH] Aava specific patches
4
5 This driver is from aava
6
7 Signed-off-by: Prajwal Mohan <prajwal.karur.mohan@intel.com>
8 Patch-mainline: 2.6.34
9 ---
10 Index: linux-2.6.33/drivers/misc/mrst_test_ipc/ipc_module.c
11 ===================================================================
12 --- linux-2.6.33.orig/drivers/misc/mrst_test_ipc/ipc_module.c
13 +++ linux-2.6.33/drivers/misc/mrst_test_ipc/ipc_module.c
14 @@ -44,8 +44,13 @@
15 #include <linux/uaccess.h>
16 #include <linux/time.h>
17
18 +
19 +
20 #include <asm/ipc_defs.h>
21
22 +#include <linux/device.h>
23 +#include <linux/ipc_module.h>
24 +
25 static u32 major;
26 #define MAX_FW_SIZE 264192
27
28 @@ -53,9 +58,11 @@ int init_ipc_driver(void);
29 int ipc_ioctl(struct inode *inode, struct file *filp, u32 cmd,
30 unsigned long arg);
31 const struct file_operations ipc_fops = {
32 +owner:THIS_MODULE,
33 ioctl:ipc_ioctl,
34 };
35
36 +static struct class *mid_ipc_class;
37
38 int ipc_ioctl(struct inode *inode, struct file *filp, u32 cmd,
39 unsigned long arg)
40 @@ -71,6 +78,18 @@ int ipc_ioctl(struct inode *inode, struc
41 u8 *fw_buf = NULL ;
42
43 switch (cmd) {
44 + case IPC_IOC_PMIC_REG_READ:
45 + cmd = IPC_PMIC_REGISTER_READ;
46 + break;
47 + case IPC_IOC_PMIC_REG_WRITE:
48 + cmd = IPC_PMIC_REGISTER_WRITE;
49 + break;
50 + default:
51 + printk(KERN_INFO "ioctl <UNRECOGNIZED> received\n");
52 + break;
53 + }
54 +
55 + switch (cmd) {
56 case IPC_PMIC_REGISTER_READ:
57 {
58 printk(KERN_INFO
59 @@ -169,6 +188,8 @@ int ipc_ioctl(struct inode *inode, struc
60
61 static int __init ipc_module_init(void)
62 {
63 + struct device *dev;
64 +
65 printk(KERN_INFO "Init ipc_module\n");
66
67 major = register_chrdev(0, "mid_ipc", &ipc_fops);
68 @@ -177,6 +198,23 @@ static int __init ipc_module_init(void)
69 return major;
70 }
71
72 + mid_ipc_class = class_create(THIS_MODULE, "mid_ipc");
73 + if (IS_ERR(mid_ipc_class)) {
74 + unregister_chrdev(major, "mid_ipc");
75 + return PTR_ERR(mid_ipc_class);
76 + }
77 +
78 + dev = device_create(mid_ipc_class,
79 + NULL,
80 + MKDEV(major, 0),
81 + NULL,
82 + "mid_ipc" );
83 + if (IS_ERR(dev)) {
84 + class_destroy(mid_ipc_class);
85 + unregister_chrdev(major, "mid_ipc");
86 + return PTR_ERR(dev);
87 + }
88 +
89 init_ipc_driver ( ) ;
90 return SUCCESS;
91
92 @@ -184,6 +222,8 @@ static int __init ipc_module_init(void)
93
94 static void __exit ipc_module_exit(void)
95 {
96 + device_destroy(mid_ipc_class, MKDEV(major, 0));
97 + class_destroy(mid_ipc_class);
98 unregister_chrdev(major, "mid_ipc");
99 }
100
101 Index: linux-2.6.33/include/linux/Kbuild
102 ===================================================================
103 --- linux-2.6.33.orig/include/linux/Kbuild
104 +++ linux-2.6.33/include/linux/Kbuild
105 @@ -385,3 +385,5 @@ unifdef-y += xfrm.h
106 objhdr-y += version.h
107 header-y += wimax.h
108 header-y += wimax/
109 +header-y += ipc_module.h
110 +
111 Index: linux-2.6.33/drivers/gpio/gpiolib.c
112 ===================================================================
113 --- linux-2.6.33.orig/drivers/gpio/gpiolib.c
114 +++ linux-2.6.33/drivers/gpio/gpiolib.c
115 @@ -228,11 +228,14 @@ static ssize_t gpio_direction_show(struc
116
117 if (!test_bit(FLAG_EXPORT, &desc->flags))
118 status = -EIO;
119 - else
120 - status = sprintf(buf, "%s\n",
121 - test_bit(FLAG_IS_OUT, &desc->flags)
122 - ? "out" : "in");
123 -
124 + else {
125 + status = sprintf(buf,
126 + "%s\n",
127 + gpio_get_direction( (desc - gpio_desc) ) ==
128 + DIRECTION_OUT ?
129 + "out" :
130 + "in");
131 + }
132 mutex_unlock(&sysfs_lock);
133 return status;
134 }
135 @@ -1507,6 +1510,29 @@ void gpio_set_value_cansleep(unsigned gp
136 }
137 EXPORT_SYMBOL_GPL(gpio_set_value_cansleep);
138
139 +enum gpio_direction gpio_get_direction(unsigned gpio)
140 +{
141 + struct gpio_chip *chip;
142 + struct gpio_desc *desc = &gpio_desc[gpio];
143 +
144 + chip = gpio_to_chip(gpio);
145 + might_sleep_if(extra_checks && chip->can_sleep);
146 +
147 + if (chip->get_direction) {
148 + if (chip->get_direction(chip, gpio - chip->base) ==
149 + DIRECTION_IN) {
150 + clear_bit(FLAG_IS_OUT, &desc->flags);
151 + return DIRECTION_IN;
152 + } else {
153 + set_bit(FLAG_IS_OUT, &desc->flags);
154 + return DIRECTION_OUT;
155 + }
156 + }
157 + return test_bit(FLAG_IS_OUT, &desc->flags) ?
158 + DIRECTION_OUT :
159 + DIRECTION_IN;
160 +}
161 +EXPORT_SYMBOL_GPL(gpio_get_direction);
162
163 #ifdef CONFIG_DEBUG_FS
164
165 Index: linux-2.6.33/drivers/gpio/langwell_gpio.c
166 ===================================================================
167 --- linux-2.6.33.orig/drivers/gpio/langwell_gpio.c
168 +++ linux-2.6.33/drivers/gpio/langwell_gpio.c
169 @@ -107,6 +107,19 @@ static int lnw_gpio_direction_output(str
170 return 0;
171 }
172
173 +static enum gpio_direction lnw_gpio_get_direction(struct gpio_chip *chip,
174 + unsigned offset)
175 +{
176 + struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
177 + u8 reg = offset / 32;
178 + void __iomem *gpdr;
179 +
180 + gpdr = (void __iomem *)(&lnw->reg_base->GPDR[reg]);
181 + if (readl(gpdr) & BIT(offset % 32))
182 + return DIRECTION_OUT;
183 + return DIRECTION_IN;
184 +}
185 +
186 static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
187 {
188 struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
189 @@ -240,6 +253,7 @@ static int __devinit lnw_gpio_probe(stru
190 lnw->chip.label = dev_name(&pdev->dev);
191 lnw->chip.direction_input = lnw_gpio_direction_input;
192 lnw->chip.direction_output = lnw_gpio_direction_output;
193 + lnw->chip.get_direction = lnw_gpio_get_direction;
194 lnw->chip.get = lnw_gpio_get;
195 lnw->chip.set = lnw_gpio_set;
196 lnw->chip.to_irq = lnw_gpio_to_irq;
197 Index: linux-2.6.33/drivers/gpio/langwell_pmic_gpio.c
198 ===================================================================
199 --- linux-2.6.33.orig/drivers/gpio/langwell_pmic_gpio.c
200 +++ linux-2.6.33/drivers/gpio/langwell_pmic_gpio.c
201 @@ -165,15 +165,33 @@ static int pmic_gpio_direction_output(st
202 return rc;
203 }
204
205 -static int pmic_gpio_get(struct gpio_chip *chip, unsigned offset)
206 +static enum gpio_direction pmic_gpio_get_direction(struct gpio_chip *chip,
207 + unsigned offset)
208 {
209 - /* we only have 8 GPIO can use as input */
210 if (offset > 8) {
211 - printk(KERN_ERR
212 - "%s: only pin 0-7 support input\n", __func__);
213 - return -1;
214 + /* GPOWSs and GPOs are always outputs */
215 + return DIRECTION_OUT;
216 }
217 - return ipc_read_char(GPIO0 + offset) & GPIO_DIN;
218 + if (ipc_read_char(GPIO0 + offset) & GPIO_DIR)
219 + return DIRECTION_IN;
220 + return DIRECTION_OUT;
221 +}
222 +
223 +static int pmic_gpio_get(struct gpio_chip *chip, unsigned offset)
224 +{
225 + if (offset < 8) {
226 + /* GPIOSW: Get state according to direction */
227 + if (pmic_gpio_get_direction( chip, offset ) == DIRECTION_IN)
228 + return (ipc_read_char(GPIO0 + offset) & GPIO_DIN);
229 + return (ipc_read_char(GPIO0 + offset) & GPIO_DOU);
230 + } else if (offset < 16) {
231 + /* GPOSW */
232 + return (ipc_read_char(GPOSWCTL0 + offset - 8) & GPOSW_DOU);
233 + } else if (offset < 24) {
234 + /* GPO */
235 + return (ipc_read_char(GPO) & (1 << (offset - 16)));
236 + }
237 + return 0;
238 }
239
240 static void pmic_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
241 @@ -284,6 +302,7 @@ static int __devinit pmic_gpio_probe(str
242 pg->chip.label = "langwell_pmic";
243 pg->chip.direction_input = pmic_gpio_direction_input;
244 pg->chip.direction_output = pmic_gpio_direction_output;
245 + pg->chip.get_direction = pmic_gpio_get_direction;
246 pg->chip.get = pmic_gpio_get;
247 pg->chip.set = pmic_gpio_set;
248 pg->chip.to_irq = pmic_gpio_to_irq;
249 Index: linux-2.6.33/drivers/gpio/pca953x.c
250 ===================================================================
251 --- linux-2.6.33.orig/drivers/gpio/pca953x.c
252 +++ linux-2.6.33/drivers/gpio/pca953x.c
253 @@ -144,6 +144,24 @@ static int pca953x_gpio_direction_output
254 return 0;
255 }
256
257 +static enum gpio_direction pca953x_gpio_get_direction(struct gpio_chip *gc,
258 + unsigned off)
259 +{
260 + struct pca953x_chip *chip;
261 + uint16_t reg_val;
262 + int ret;
263 +
264 + chip = container_of(gc, struct pca953x_chip, gpio_chip);
265 +
266 + ret = pca953x_read_reg(chip, PCA953X_DIRECTION, &reg_val);
267 + if (ret == 0) {
268 + if ( reg_val & (1u << off) )
269 + return DIRECTION_IN;
270 + return DIRECTION_OUT;
271 + }
272 + return DIRECTION_IN;
273 +}
274 +
275 static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
276 {
277 struct pca953x_chip *chip;
278 @@ -199,6 +217,7 @@ static void pca953x_setup_gpio(struct pc
279
280 gc->direction_input = pca953x_gpio_direction_input;
281 gc->direction_output = pca953x_gpio_direction_output;
282 + gc->get_direction = pca953x_gpio_get_direction;
283 gc->get = pca953x_gpio_get_value;
284 gc->set = pca953x_gpio_set_value;
285 gc->to_irq = pca953x_gpio_to_irq;
286 Index: linux-2.6.33/include/asm-generic/gpio.h
287 ===================================================================
288 --- linux-2.6.33.orig/include/asm-generic/gpio.h
289 +++ linux-2.6.33/include/asm-generic/gpio.h
290 @@ -101,6 +101,8 @@ struct gpio_chip {
291 char **names;
292 unsigned can_sleep:1;
293 unsigned exported:1;
294 + enum gpio_direction (*get_direction)(struct gpio_chip *chip,
295 + unsigned offset);
296 };
297
298 extern const char *gpiochip_is_requested(struct gpio_chip *chip,
299 @@ -120,6 +122,7 @@ extern void gpio_free(unsigned gpio);
300
301 extern int gpio_direction_input(unsigned gpio);
302 extern int gpio_direction_output(unsigned gpio, int value);
303 +extern enum gpio_direction gpio_get_direction(unsigned gpio);
304
305 extern int gpio_get_value_cansleep(unsigned gpio);
306 extern void gpio_set_value_cansleep(unsigned gpio, int value);
307 Index: linux-2.6.33/include/linux/gpio.h
308 ===================================================================
309 --- linux-2.6.33.orig/include/linux/gpio.h
310 +++ linux-2.6.33/include/linux/gpio.h
311 @@ -3,6 +3,11 @@
312
313 /* see Documentation/gpio.txt */
314
315 +enum gpio_direction {
316 + DIRECTION_IN = 0,
317 + DIRECTION_OUT = 1,
318 +};
319 +
320 #ifdef CONFIG_GENERIC_GPIO
321 #include <asm/gpio.h>
322
323 @@ -126,6 +131,13 @@ static inline int irq_to_gpio(unsigned i
324 return -EINVAL;
325 }
326
327 +static inline enum gpio_direction gpio_get_direction(unsigned gpio)
328 +{
329 + /* GPIO can never have been requested or set as {in,out}put */
330 + WARN_ON(1);
331 + return DIRECTION_IN;
332 +}
333 +
334 #endif
335
336 #endif /* __LINUX_GPIO_H */
337 Index: linux-2.6.33/include/linux/ipc_module.h
338 ===================================================================
339 --- /dev/null
340 +++ linux-2.6.33/include/linux/ipc_module.h
341 @@ -0,0 +1,60 @@
342 +/*
343 + * include/linux/ipc_module.h
344 + *
345 + * Copyright (C) 2009 Aava Mobile Oy
346 + * Written by Mikko Kovanen <mikko.kovanen@aavamobile.com>
347 + *
348 + * This program is free software; you can redistribute it and/or modify
349 + * it under the terms of the GNU General Public License version 2 as
350 + * published by the Free Software Foundation.
351 + *
352 + * This program is distributed in the hope that it will be useful,
353 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
354 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
355 + * GNU General Public License for more details.
356 + *
357 + * You should have received a copy of the GNU General Public License
358 + * along with this program; if not, write to the Free Software
359 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
360 + */
361 +
362 +#ifndef IPC_MODULE_H
363 +#define IPC_MODULE_H
364 +
365 +#include <linux/types.h>
366 +
367 +#ifndef __IPC_DEFS_H__
368 +#define E_INVALID_CMD -249
369 +#define E_READ_USER_CMD -250
370 +#define E_READ_USER_DATA -251
371 +#define E_WRITE_USER_DATA -252
372 +#define E_PMIC_MALLOC -253
373 +
374 +#define MAX_PMICREGS 5
375 +#define MAX_PMIC_MOD_REGS 4
376 +
377 +struct pmicreg {
378 + __u16 register_address;
379 + __u8 value;
380 +};
381 +
382 +struct ipc_pmic_reg_data {
383 + _Bool ioc;
384 + struct pmicreg pmic_reg_data[MAX_PMICREGS];
385 + __u8 num_entries;
386 +};
387 +#endif /* __IPC_DEFS_H__ */
388 +
389 +#define IPC_IOC_MAGIC 'a'
390 +
391 +
392 +#define IPC_IOC_PMIC_REG_READ _IOR(IPC_IOC_MAGIC, \
393 + 0, \
394 + struct ipc_pmic_reg_data)
395 +
396 +#define IPC_IOC_PMIC_REG_WRITE _IOW(IPC_IOC_MAGIC, \
397 + 1, \
398 + struct ipc_pmic_reg_data)
399 +
400 +#endif /* IPC_MODULE_H */
401 +
402 Index: linux-2.6.33/drivers/input/keyboard/mrst_keypad.c
403 ===================================================================
404 --- linux-2.6.33.orig/drivers/input/keyboard/mrst_keypad.c
405 +++ linux-2.6.33/drivers/input/keyboard/mrst_keypad.c
406 @@ -40,6 +40,9 @@
407 #include <linux/device.h>
408 #include <linux/err.h>
409 #include <linux/gpio.h>
410 +/*jhuot start*/
411 +#include <asm/ipc_defs.h>
412 +/*jhuot end*/
413
414 /*
415 * Keypad Controller registers
416 @@ -116,10 +119,10 @@ MODULE_DEVICE_TABLE(pci, keypad_pci_tbl)
417 #define keypad_writel(off, v) writel((v), keypad->mmio_base + (off))
418
419 #define MAX_MATRIX_KEY_NUM (8 * 8)
420 -#define MAX_DIRECT_KEY_NUM (4)
421 +#define MAX_DIRECT_KEY_NUM (2)
422
423 -#define MAX_MATRIX_KEY_ROWS (8)
424 -#define MAX_MATRIX_KEY_COLS (8)
425 +#define MAX_MATRIX_KEY_ROWS (7)
426 +#define MAX_MATRIX_KEY_COLS (7)
427 #define DEBOUNCE_INTERVAL 100
428
429 #define KEY_HALFSHUTTER KEY_PROG1
430 @@ -167,7 +170,7 @@ static unsigned int mrst_keycode_fn[MAX_
431
432 /* direct key map */
433 static unsigned int mrst_direct_keycode[MAX_DIRECT_KEY_NUM] = {
434 - KEY_VOLUMEUP, KEY_VOLUMEDOWN, KEY_HALFSHUTTER, KEY_FULLSHUTTER,
435 + KEY_VOLUMEUP, KEY_VOLUMEDOWN, //KEY_HALFSHUTTER, KEY_FULLSHUTTER,
436 };
437
438 struct mrst_keypad {
439 @@ -430,6 +433,8 @@ scan:
440 if ((bits_changed & (1 << row)) == 0)
441 continue;
442
443 + printk(KERN_INFO "BUTTONS: "
444 + "report key row %d, col %d\n", row, col);
445 input_report_key(keypad->input_dev,
446 lookup_matrix_keycode(keypad, row, col),
447 new_state[col] & (1 << row));
448 @@ -513,6 +518,8 @@ static void mrst_keypad_scan_direct(stru
449
450 for (i = 0; i < keypad->direct_key_num; i++) {
451 if (bits_changed & (1 << i)) {
452 + printk(KERN_INFO "BUTTONS: "
453 + "scan_direct %d\n", keypad->direct_key_map[i]);
454 input_report_key(keypad->input_dev,
455 keypad->direct_key_map[i],
456 (new_state & (1 << i)));
457 @@ -528,10 +535,13 @@ static irqreturn_t mrst_keypad_irq_handl
458 struct mrst_keypad *keypad = dev_id;
459 unsigned long kpc = keypad_readl(KPC);
460
461 + printk(KERN_INFO "BUTTONS: irq_handler, kpc %lu\n", kpc);
462 if (kpc & KPC_DI)
463 + printk(KERN_INFO "BUTTONS: mrst_keypad_scan_direct\n");
464 mrst_keypad_scan_direct(keypad);
465
466 if (kpc & KPC_MI)
467 + printk(KERN_INFO "BUTTONS: mrst_keypad_scan_matrix\n");
468 mrst_keypad_scan_matrix(keypad);
469
470 return IRQ_HANDLED;
471 @@ -544,13 +554,47 @@ static int mrst_keypad_gpio_init(void)
472 MAX_MATRIX_KEY_COLS + MAX_DIRECT_KEY_NUM;
473
474 /* explicitely tell which pins have been occupied... */
475 +/*
476 for (i = KEYPAD_MATRIX_GPIO_IN_PIN; i < pins; i++, cnt++) {
477 err = gpio_request(i, NULL);
478 if (err) {
479 printk(KERN_ERR "GPIO pin %d failed to request.\n", i);
480 goto err_request;
481 }
482 - }
483 + }*/
484 +
485 + for (i = 0; i < MAX_MATRIX_KEY_ROWS; i++){
486 + err = gpio_request(KEYPAD_MATRIX_GPIO_IN_PIN + i,NULL);
487 +
488 + if (err) {
489 + printk(KERN_ERR "GPIO pin %d failed to request.\n", i);
490 + goto err_request;
491 + }
492 +
493 + }
494 +
495 + for (i = 0; i < MAX_MATRIX_KEY_COLS; i++)
496 + {
497 + err = gpio_request(KEYPAD_MATRIX_GPIO_OUT_PIN + i, NULL);
498 + if (err) {
499 + printk(KERN_ERR "GPIO pin %d failed to request.\n", i);
500 + goto err_request;
501 + }
502 +
503 + }
504 +
505 + for (i = 0; i < MAX_DIRECT_KEY_NUM; i++)
506 + {
507 + err = gpio_request(KEYPAD_DIRECT_GPIO_IN_PIN + i,NULL);
508 +
509 + if (err) {
510 + printk(KERN_ERR "GPIO pin %d failed to request.\n", i);
511 + goto err_request;
512 + }
513 +
514 +
515 + }
516 +
517
518 for (i = 0; i < MAX_MATRIX_KEY_ROWS; i++)
519 gpio_direction_input(KEYPAD_MATRIX_GPIO_IN_PIN + i);
520 @@ -642,6 +686,9 @@ static int __devinit mrst_keypad_probe(s
521 struct mrst_keypad *keypad;
522 struct input_dev *input_dev;
523 int error;
524 +/* jhuot start */
525 + struct ipc_io_bus_master_regs *p_reg_data;
526 +/* jhuot end */
527
528 #ifndef MODULE
529 printk(KERN_INFO MRST_KEYPAD_DRIVER_NAME "\n");
530 @@ -711,6 +758,18 @@ static int __devinit mrst_keypad_probe(s
531 goto failed_free_dev;
532 }
533
534 +
535 +/* jhuot start */
536 + /* Enable 75 kOhm internal pull-ups for KBD_DKIN0 and KBD_DKIN1 */
537 + /*bus: 0x4h, address: 0x20h, bits 0...3 */
538 + p_reg_data = kzalloc(sizeof(struct ipc_io_bus_master_regs), GFP_KERNEL);
539 + /*01 = W, 04 = bus, 20 = address*/
540 + p_reg_data->ctrl_reg_addr = 0x01040020;
541 + /*b3-b0 = 1010 (75kOhm pull-ups) = 0xAh*/
542 + p_reg_data->ctrl_reg_data = 0xA;
543 + ipc_program_io_bus_master(p_reg_data);
544 +/* jhuot end */
545 +
546 /* Register the input device */
547 error = input_register_device(input_dev);
548 if (error) {
549 Index: linux-2.6.33/drivers/gpu/drm/mrst/Kconfig
550 ===================================================================
551 --- linux-2.6.33.orig/drivers/gpu/drm/mrst/Kconfig
552 +++ linux-2.6.33/drivers/gpu/drm/mrst/Kconfig
553 @@ -23,6 +23,20 @@ config IMG_DOES_NOT_SUPPORT_MENLOW
554 help
555 Choose Menlow
556
557 +config DRM_MRST_AAVA
558 + bool "Aava platform specific MIPI display"
559 + depends on DRM_MRST
560 + default n
561 + help
562 + Choose Aava platform MIPI display, temp option
563 +
564 +config DRM_MRST_CDK
565 + bool "Aava platform specific MIPI display"
566 + depends on DRM_MRST && !DRM_MRST_AAVA
567 + default y
568 + help
569 + Choose CDK
570 +
571 config PVR_RELEASE
572 string "Build IMG kernel services as release"
573 depends on DRM_MRST
574 Index: linux-2.6.33/drivers/misc/Makefile
575 ===================================================================
576 --- linux-2.6.33.orig/drivers/misc/Makefile
577 +++ linux-2.6.33/drivers/misc/Makefile
578 @@ -21,7 +21,7 @@ obj-$(CONFIG_SGI_XP) += sgi-xp/
579 obj-$(CONFIG_SGI_GRU) += sgi-gru/
580 obj-$(CONFIG_CS5535_MFGPT) += cs5535-mfgpt.o
581 obj-$(CONFIG_HP_ILO) += hpilo.o
582 -obj-$(CONFIG_MRST) += intel_mrst.o
583 +obj-$(CONFIG_X86_MRST) += intel_mrst.o
584 obj-$(CONFIG_ISL29003) += isl29003.o
585 obj-$(CONFIG_MRST_RAR_HANDLER) += memrar.o
586 memrar-y := memrar_allocator.o memrar_handler.o
587 Index: linux-2.6.33/drivers/misc/intel_mrst.c
588 ===================================================================
589 --- linux-2.6.33.orig/drivers/misc/intel_mrst.c
590 +++ linux-2.6.33/drivers/misc/intel_mrst.c
591 @@ -112,6 +112,48 @@ static int intel_mrst_sdio_EVP_power_dow
592
593 static int intel_mrst_sdio_8688_power_up(void)
594 {
595 +/*ouljhuot start*/
596 +/*WLAN / BT power-up sequence:*/
597 +/*1. power (GPO4) & reset (GPO3) low*/
598 +/*2. power (GPO4) high*/
599 +/*3. reset (GPO3) high*/
600 +
601 +/*GPS power-up sequence:*/
602 +/*1. power (GPO1) & reset (GPO2) low*/
603 +/*2. VDD_IO and VDD_LP_PLLREG_IN high*/
604 +/*VDD_IO & VDD_LP_PLLREG_IN == VPMIC_1V8*/
605 +/*3. usleep(1) (tvddio_nreset min. 500ns)*/
606 +/*4. reset (GPO2) high*/
607 +/*5. VDD_COREREG_IN and VDD_RFREG_IN high*/
608 + /*VDD_COREREG_IN == VWLAN_GPS_1V8 (GYMXIO)*/
609 + /*VDD_RFREG_IN == VGPS_ANA_3V3 (GYMX33)*/
610 +/*6. power (GPO1) high*/
611 +/*7. msleep(1);*/
612 + unsigned int temp = 0;
613 +
614 + /* Register 0xf4 has 4 GPIO lines connected to the MRVL 8688 * IFX GPS:
615 + * bit 4: WiFi PDn
616 + * bit 3: WiFi RESETn
617 + * bit 2: GPS RESET_N
618 + * bit 1: GPS PD_N*/
619 +
620 + /*WLAN POWER and RESET low*/
621 + intel_mrst_pmic_read(0xf4, &temp);
622 + temp &= ~0x18;
623 + intel_mrst_pmic_write(0xf4, temp);
624 +/* msleep(1);*/
625 +
626 + /*GPS RESET low & POWER low*/
627 + intel_mrst_pmic_read(0xf4, &temp);
628 + temp &= ~0x6;
629 + intel_mrst_pmic_write(0xf4, temp);
630 +/* usleep(1);*/
631 +
632 + msleep(1);
633 + /*GPS RESET high*/
634 + temp |= 0x4;
635 + intel_mrst_pmic_write(0xf4, temp);
636 +/*ouljhuot end*/
637 intel_mrst_pmic_write(0x37, 0x3f); /* Set VDDQ for Marvell 8688 */
638 intel_mrst_pmic_write(0x4a, 0x3f); /* Set GYMXIOCNT for Marvell 8688 */
639 intel_mrst_pmic_write(0x4e, 0x3f); /* Set GYMX33CNT for Marvell 8688 */
640 @@ -124,6 +166,22 @@ static int intel_mrst_sdio_8688_power_up
641 intel_mrst_pmic_write(0x4c, 0x27); /* Enable V1p8_VWYMXARF for
642 MRVL8688 */
643
644 +
645 +/*ouljhuot start*/
646 + /*WLAN POWER high*/
647 + temp |= 0x10;
648 + intel_mrst_pmic_write(0xf4, temp);
649 +
650 + /*WLAN RESET high*/
651 + temp |= 0x8;
652 + intel_mrst_pmic_write(0xf4, temp);
653 +
654 + /*GPS POWER high*/
655 + temp |= 0x2;
656 + intel_mrst_pmic_write(0xf4, temp);
657 +/* msleep(16);*/
658 +/*ouljhuot end*/
659 +
660 return 0;
661 }
662
663 @@ -153,6 +211,35 @@ static int intel_mrst_bringup_8688_sdio2
664 return 0;
665 }
666
667 +
668 +
669 +
670 + /*ouljhuot start*/
671 +static int intel_mrst_sdio_gps_power_up(void)
672 + {
673 + unsigned int temp = 0;
674 +
675 + /*GPS RESET low & POWER low*/
676 + intel_mrst_pmic_read(0xf4, &temp);
677 + temp &= ~0x6;
678 + intel_mrst_pmic_write(0xf4, temp);
679 + msleep(1);
680 + /*GPS RESET high*/
681 + temp |= 0x4;
682 + intel_mrst_pmic_write(0xf4, temp);
683 +
684 + intel_mrst_pmic_write(0x4a, 0x3f); /* Ensure GYMXIOCNT */
685 + intel_mrst_pmic_write(0x4e, 0x3f); /* Ensure GYMX33CNT */
686 +
687 + /*GPS POWER high*/
688 + temp |= 0x2;
689 + intel_mrst_pmic_write(0xf4, temp);
690 + /* Wait to settle */
691 + msleep(16);
692 +
693 + return 0;
694 + }
695 +
696 static int intel_mrst_bringup_EVP_sdio2_Option_spi(void)
697 {
698 unsigned int temp = 0;
699 @@ -199,7 +286,10 @@ static int __init intel_mrst_module_init
700
701 printk(KERN_INFO "intel_mrst_module_init: bringing up power for "
702 "8688 WLAN on SDIO2 & IFX GPS over SPI...\n");
703 - ret = intel_mrst_bringup_8688_sdio2();
704 +/*ouljhuot start*/
705 + ret = intel_mrst_sdio_8688_power_up();
706 +/* ret = intel_mrst_sdio_gps_power_up();*/
707 +/*ouljhuot end*/
708
709 #endif /* CONFIG_8688_RC */
710
711 Index: linux-2.6.33/drivers/hwmon/lis331dl.c
712 ===================================================================
713 --- linux-2.6.33.orig/drivers/hwmon/lis331dl.c
714 +++ linux-2.6.33/drivers/hwmon/lis331dl.c
715 @@ -45,6 +45,8 @@ MODULE_LICENSE("GPL v2");
716 #define ACCEL_NORMAL_MODE 0
717 #define ACCEL_MEMORY_REBOOT 1
718
719 +#define POS_READ_MAX_RETRY (5)
720 +
721 /* internal return values */
722
723 struct acclero_data {
724 @@ -93,9 +95,24 @@ static ssize_t x_pos_show(struct device
725 {
726 struct i2c_client *client = to_i2c_client(dev);
727 int ret_val;
728 + int retry = 0;
729
730 +x_retry:
731 ret_val = i2c_smbus_read_byte_data(client, 0x29);
732 - return sprintf(buf, "%d\n", ret_val);
733 + if (ret_val == -ETIMEDOUT) {
734 + dev_dbg(dev, "x pos read timed out, retry %d\n", retry);
735 + retry++;
736 + if (retry <= POS_READ_MAX_RETRY) {
737 + msleep(10);
738 + goto x_retry;
739 + } else {
740 + ret_val = 0;
741 + dev_err(dev, "x pos read failed %d retries\n", retry);
742 + }
743 + }
744 + /* ouljkorh, 09.11.2009, change start */
745 + return sprintf(buf, "%d\n", (signed char)ret_val);
746 + /* ouljkorh, 09.11.2009, change end */
747 }
748
749 static ssize_t y_pos_show(struct device *dev,
750 @@ -103,9 +120,24 @@ static ssize_t y_pos_show(struct device
751 {
752 struct i2c_client *client = to_i2c_client(dev);
753 int ret_val;
754 + int retry = 0;
755
756 +y_retry:
757 ret_val = i2c_smbus_read_byte_data(client, 0x2B);
758 - return sprintf(buf, "%d\n", ret_val);
759 + if (ret_val == -ETIMEDOUT) {
760 + dev_dbg(dev, "y pos read timed out, retry %d\n", retry);
761 + retry++;
762 + if (retry <= POS_READ_MAX_RETRY) {
763 + msleep(10);
764 + goto y_retry;
765 + } else {
766 + ret_val = 0;
767 + dev_err(dev, "y pos read failed %d retries\n", retry);
768 + }
769 + }
770 + /* ouljkorh, 09.11.2009, change start */
771 + return sprintf(buf, "%d\n", (signed char)ret_val);
772 + /* ouljkorh, 09.11.2009, change end */
773 }
774
775 static ssize_t z_pos_show(struct device *dev,
776 @@ -113,9 +145,24 @@ static ssize_t z_pos_show(struct device
777 {
778 struct i2c_client *client = to_i2c_client(dev);
779 int ret_val;
780 + int retry = 0;
781
782 +z_retry:
783 ret_val = i2c_smbus_read_byte_data(client, 0x2D);
784 - return sprintf(buf, "%d\n", ret_val);
785 + if (ret_val == -ETIMEDOUT) {
786 + dev_dbg(dev, "z pos read timed out, retry %d\n", retry);
787 + retry++;
788 + if (retry <= POS_READ_MAX_RETRY) {
789 + msleep(10);
790 + goto z_retry;
791 + } else {
792 + ret_val = 0;
793 + dev_err(dev, "z pos read failed %d retries\n", retry);
794 + }
795 + }
796 + /* ouljkorh, 09.11.2009, change start */
797 + return sprintf(buf, "%d\n", (signed char)ret_val);
798 + /* ouljkorh, 09.11.2009, change end */
799 }
800
801 static ssize_t xyz_pos_show(struct device *dev,
802 @@ -123,11 +170,38 @@ static ssize_t xyz_pos_show(struct devic
803 {
804 int x, y, z;
805 struct i2c_client *client = to_i2c_client(dev);
806 + int retry = 0;
807
808 +xyz_retry:
809 + if (retry > POS_READ_MAX_RETRY) {
810 + dev_err(dev, "xyz read retry failed\n");
811 + x = y = z = 0;
812 + return sprintf(buf, "(%d,%d,%d)\n", (signed char)x,
813 + (signed char)y, (signed char)z);
814 + }
815 + retry++;
816 x = i2c_smbus_read_byte_data(client, 0x29);
817 + if (x == -ETIMEDOUT) {
818 + msleep(100);
819 + goto xyz_retry;
820 + }
821 + msleep(100);
822 y = i2c_smbus_read_byte_data(client, 0x2B);
823 + if (y == -ETIMEDOUT) {
824 + msleep(100);
825 + goto xyz_retry;
826 + }
827 + msleep(100);
828 z = i2c_smbus_read_byte_data(client, 0x2D);
829 - return sprintf(buf, "(%d,%d,%d)\n", x, y, z);
830 + if (z == -ETIMEDOUT) {
831 + msleep(100);
832 + goto xyz_retry;
833 + }
834 +
835 + /* ouljkorh, 09.11.2009, change start */
836 + return sprintf(buf, "(%d,%d,%d)\n", (signed char)x,
837 + (signed char)y, (signed char)z);
838 + /* ouljkorh, 09.11.2009, change end */
839 }
840
841 static ssize_t data_rate_store(struct device *dev,
842 Index: linux-2.6.33/drivers/usb/gadget/u_serial.c
843 ===================================================================
844 --- linux-2.6.33.orig/drivers/usb/gadget/u_serial.c
845 +++ linux-2.6.33/drivers/usb/gadget/u_serial.c
846 @@ -783,11 +783,6 @@ static int gs_open(struct tty_struct *tt
847 port->open_count = 1;
848 port->openclose = false;
849
850 - /* low_latency means ldiscs work in tasklet context, without
851 - * needing a workqueue schedule ... easier to keep up.
852 - */
853 - tty->low_latency = 1;
854 -
855 /* if connected, start the I/O stream */
856 if (port->port_usb) {
857 struct gserial *gser = port->port_usb;
858 Index: linux-2.6.33/drivers/i2c/busses/i2c-mrst.c
859 ===================================================================
860 --- linux-2.6.33.orig/drivers/i2c/busses/i2c-mrst.c
861 +++ linux-2.6.33/drivers/i2c/busses/i2c-mrst.c
862 @@ -37,7 +37,7 @@
863
864 #include "i2c-mrst.h"
865
866 -#define MAX_T_POLL_COUNT 4000 /* FIXME */
867 +#define MAX_T_POLL_COUNT 8000 /* FIXME */
868 #define DEF_BAR 0
869 #define VERSION "Version 0.5"
870
871 Index: linux-2.6.33/arch/x86/kernel/mrst.c
872 ===================================================================
873 --- linux-2.6.33.orig/arch/x86/kernel/mrst.c
874 +++ linux-2.6.33/arch/x86/kernel/mrst.c
875 @@ -23,6 +23,9 @@
876 #include <linux/input.h>
877 #include <linux/platform_device.h>
878 #include <linux/irq.h>
879 +/*jhuot, added for MAX3107 data*/
880 +#include <linux/spi/mrst_spi.h>
881 +
882
883 #include <asm/string.h>
884 #include <asm/setup.h>
885 @@ -267,6 +270,27 @@ void __init x86_mrst_early_setup(void)
886 #define MRST_SPI2_CS_START 4
887 static struct langwell_pmic_gpio_platform_data pmic_gpio_pdata;
888
889 +#ifdef CONFIG_SERIAL_MAX3107
890 +static struct mrst_spi_chip spi_slave0 = {
891 + .poll_mode = 1,
892 + .enable_dma = 0,
893 + .type = SPI_FRF_SPI,
894 +};
895 +
896 +static struct spi_board_info mrst_spi_board_info[] __initdata = {
897 + {
898 + /* the modalias must be the same as spi device driver name */
899 + .modalias = "max3107", /* spi_driver name driving device */
900 + .max_speed_hz = 3125000,/* default value */
901 + .bus_num = 0, /* SPI0 */
902 + .chip_select = 0, /* Framework chip select. */
903 + .platform_data = NULL, /* fill later */
904 + .controller_data = &spi_slave0,
905 + .irq = 0x13d,
906 + },
907 +};
908 +#endif
909 +
910 static int __init sfi_parse_spib(struct sfi_table_header *table)
911 {
912 struct sfi_table_simple *sb;
913 @@ -290,31 +314,48 @@ static int __init sfi_parse_spib(struct
914 pr_info("Moorestown SPI devices info:\n");
915
916 for (i = 0, j = 0; i < num; i++, pentry++) {
917 - strncpy(info[j].modalias, pentry->name, 16);
918 - info[j].irq = pentry->irq_info;
919 - info[j].bus_num = pentry->host_num;
920 - info[j].chip_select = pentry->cs;
921 - info[j].max_speed_hz = 3125000; /* hard coded */
922 - if (info[i].chip_select >= MRST_SPI2_CS_START) {
923 - /* these SPI2 devices are not exposed to system as PCI
924 - * devices, but they have separate RTE entry in IOAPIC
925 - * so we have to enable them one by one here
926 - */
927 - ioapic = mp_find_ioapic(info[j].irq);
928 - irq_attr.ioapic = ioapic;
929 - irq_attr.ioapic_pin = info[j].irq;
930 - irq_attr.trigger = 1;
931 - irq_attr.polarity = 1;
932 - io_apic_set_pci_routing(NULL, info[j].irq,
933 +#ifdef CONFIG_SERIAL_MAX3107
934 + if (j != 1) { /*other devices info*/
935 +#endif
936 + strncpy(info[j].modalias, pentry->name, 16);
937 + info[j].irq = pentry->irq_info;
938 + info[j].bus_num = pentry->host_num;
939 + info[j].chip_select = pentry->cs;
940 + info[j].max_speed_hz = 3125000; /* hard coded */
941 + if (info[i].chip_select >= MRST_SPI2_CS_START) {
942 + /* these SPI2 devices are not exposed to system as PCI
943 + * devices, but they have separate RTE entry in IOAPIC
944 + * so we have to enable them one by one here
945 + */
946 + ioapic = mp_find_ioapic(info[j].irq);
947 + irq_attr.ioapic = ioapic;
948 + irq_attr.ioapic_pin = info[j].irq;
949 + irq_attr.trigger = 1;
950 + irq_attr.polarity = 1;
951 + io_apic_set_pci_routing(NULL, info[j].irq,
952 &irq_attr);
953 - }
954 - info[j].platform_data = pentry->dev_info;
955 + }
956
957 - if (!strcmp(pentry->name, "pmic_gpio")) {
958 - memcpy(&pmic_gpio_pdata, pentry->dev_info, 8);
959 - pmic_gpio_pdata.gpiointr = 0xffffeff8;
960 - info[j].platform_data = &pmic_gpio_pdata;
961 + info[j].platform_data = pentry->dev_info;
962 +
963 + if (!strcmp(pentry->name, "pmic_gpio")) {
964 + memcpy(&pmic_gpio_pdata, pentry->dev_info, 8);
965 + pmic_gpio_pdata.gpiointr = 0xffffeff8;
966 + info[j].platform_data = &pmic_gpio_pdata;
967 + }
968 +#ifdef CONFIG_SERIAL_MAX3107
969 + } else { /*MAX3107 info*/
970 + info[j] = mrst_spi_board_info[0];
971 + }
972 +
973 +#endif
974 + /* jhuot edit start: change GPS chip select from 2 to 3 */
975 + if (info[j].bus_num == 0 && info[j].chip_select == 2) {
976 + info[j].chip_select = 3;
977 + } else if (info[j].bus_num == 0 && info[j].chip_select == 3) {
978 + info[j].chip_select = 2;
979 }
980 + /* jhuot edit end */
981 pr_info("info[%d]: name = %16s, irq = 0x%04x, bus = %d, "
982 "cs = %d\n", j, info[j].modalias, info[j].irq,
983 info[j].bus_num, info[j].chip_select);
984 Index: linux-2.6.33/drivers/serial/Kconfig
985 ===================================================================
986 --- linux-2.6.33.orig/drivers/serial/Kconfig
987 +++ linux-2.6.33/drivers/serial/Kconfig
988 @@ -540,6 +540,21 @@ config SERIAL_S5PC100
989 help
990 Serial port support for the Samsung S5PC100 SoCs
991
992 +config SERIAL_MAX3107
993 + tristate "MAX3107 support"
994 + depends on SPI
995 + select SERIAL_CORE
996 + help
997 + MAX3107 chip support
998 +
999 +config MAX3107_LOW_POWER
1000 + boolean "Enable very low power consumption scheme for Max3107"
1001 + default n
1002 + depends on SERIAL_MAX3107
1003 + help
1004 + Adds hardware suspend for MAX3107 instead of sleep/auto-sleep,
1005 + but causes longer latency in wake-up (re-initialization of the chip).
1006 +
1007 config SERIAL_MAX3100
1008 tristate "MAX3100 support"
1009 depends on SPI
1010 Index: linux-2.6.33/drivers/serial/Makefile
1011 ===================================================================
1012 --- linux-2.6.33.orig/drivers/serial/Makefile
1013 +++ linux-2.6.33/drivers/serial/Makefile
1014 @@ -46,6 +46,7 @@ obj-$(CONFIG_SERIAL_S3C24A0) += s3c24a0.
1015 obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o
1016 obj-$(CONFIG_SERIAL_S5PC100) += s3c6400.o
1017 obj-$(CONFIG_SERIAL_MAX3100) += max3100.o
1018 +obj-$(CONFIG_SERIAL_MAX3107) += max3107.o
1019 obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o
1020 obj-$(CONFIG_SERIAL_MUX) += mux.o
1021 obj-$(CONFIG_SERIAL_68328) += 68328serial.o
1022 Index: linux-2.6.33/drivers/serial/max3107.c
1023 ===================================================================
1024 --- /dev/null
1025 +++ linux-2.6.33/drivers/serial/max3107.c
1026 @@ -0,0 +1,1484 @@
1027 +/*
1028 + * max3107.c - spi uart protocol driver for Maxim 3107
1029 + * Based on max3100.c
1030 + * by Christian Pellegrin <chripell@evolware.org>
1031 + * and max3110.c
1032 + * by Feng Tang <feng.tang@intel.com>
1033 + *
1034 + * Copyright (C) Aavamobile 2009
1035 + *
1036 + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1037 + *
1038 + * This program is free software; you can redistribute it and/or modify
1039 + * it under the terms of the GNU General Public License as published by
1040 + * the Free Software Foundation; either version 2 of the License, or
1041 + * (at your option) any later version.
1042 + *
1043 + * This program is distributed in the hope that it will be useful,
1044 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1045 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1046 + * GNU General Public License for more details.
1047 + *
1048 + * You should have received a copy of the GNU General Public License
1049 + * along with this program; if not, write to the Free Software
1050 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1051 + *
1052 + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1053 + *
1054 + */
1055 +
1056 +#include <linux/delay.h>
1057 +#include <linux/device.h>
1058 +#include <linux/serial_core.h>
1059 +#include <linux/serial.h>
1060 +#include <linux/spi/spi.h>
1061 +#include <linux/spi/mrst_spi.h>
1062 +#include <linux/freezer.h>
1063 +#include <linux/platform_device.h>
1064 +#include <linux/gpio.h>
1065 +#include <linux/serial_max3107.h>
1066 +
1067 +/* Debug trace definitions */
1068 +#define DBG_LEVEL 0
1069 +
1070 +#if (DBG_LEVEL > 0)
1071 +#define DBG_TRACE(format,args...) printk(KERN_ERR "%s: " format, \
1072 + __FUNCTION__ , ## args)
1073 +#else
1074 +#define DBG_TRACE(format,args...)
1075 +#endif
1076 +
1077 +#if (DBG_LEVEL > 1)
1078 +#define DBG_TRACE_SPI_DATA
1079 +#endif
1080 +
1081 +struct max3107_port {
1082 + /* UART port structure */
1083 + struct uart_port port;
1084 +
1085 + /* SPI device structure */
1086 + struct spi_device *spi;
1087 +
1088 + /* GPIO chip stucture */
1089 + struct gpio_chip chip;
1090 +
1091 + /* Workqueue that does all the magic */
1092 + struct workqueue_struct *workqueue;
1093 + struct work_struct work;
1094 +
1095 + /* Lock for shared data */
1096 + spinlock_t data_lock;
1097 +
1098 + /* Device configuration */
1099 + int ext_clk; /* 1 if external clock used */
1100 + int loopback; /* Current loopback mode state */
1101 + int baud; /* Current baud rate */
1102 +
1103 + /* State flags */
1104 + int suspended; /* Indicates suspend mode */
1105 + int tx_fifo_empty; /* Flag for TX FIFO state */
1106 + int rx_enabled; /* Flag for receiver state */
1107 + int tx_enabled; /* Flag for transmitter state */
1108 +
1109 + /* Shared data */
1110 + u16 irqen_reg; /* Current IRQ enable register value */
1111 + u16 mode1_reg; /* Current mode1 register value*/
1112 + int mode1_commit; /* Flag for setting new mode1 register value */
1113 + u16 lcr_reg; /* Current LCR register value */
1114 + int lcr_commit; /* Flag for setting new LCR register value */
1115 + u32 brg_cfg; /* Current Baud rate generator config */
1116 + int brg_commit; /* Flag for setting new baud rate generator
1117 + * config
1118 + */
1119 +
1120 + int handle_irq; /* Indicates that IRQ should be handled */
1121 +};
1122 +
1123 +/* Platform data structure */
1124 +struct max3107_plat {
1125 + /* Loopback mode enable */
1126 + int loopback;
1127 + /* External clock enable */
1128 + int ext_clk;
1129 + /* HW suspend function */
1130 + void (*max3107_hw_suspend) (struct max3107_port *s, int suspend);
1131 + /* Polling mode enable */
1132 + int polled_mode;
1133 + /* Polling period if polling mode enabled */
1134 + int poll_time;
1135 +};
1136 +
1137 +
1138 +/* Perform SPI transfer for write/read of device register(s) */
1139 +static int max3107_rw(struct max3107_port *s, u8 *tx, u8 *rx, int len)
1140 +{
1141 + struct spi_message spi_msg;
1142 + struct spi_transfer spi_xfer;
1143 +
1144 + DBG_TRACE("enter\n");
1145 +
1146 + /* Initialize SPI ,message */
1147 + spi_message_init(&spi_msg);
1148 +
1149 + /* Initialize SPI transfer */
1150 + memset(&spi_xfer, 0, sizeof spi_xfer);
1151 + spi_xfer.len = len;
1152 + spi_xfer.tx_buf = tx;
1153 + spi_xfer.rx_buf = rx;
1154 + spi_xfer.speed_hz = MAX3107_SPI_SPEED;
1155 +
1156 + /* Add SPI transfer to SPI message */
1157 + spi_message_add_tail(&spi_xfer, &spi_msg);
1158 +
1159 +#ifdef DBG_TRACE_SPI_DATA
1160 + {
1161 + int i;
1162 + printk("tx len %d:\n", spi_xfer.len);
1163 + for (i = 0 ; i < spi_xfer.len && i < 32 ; i++) {
1164 + printk(" %x", ((u8*)spi_xfer.tx_buf)[i]);
1165 + }
1166 + printk("\n");
1167 + }
1168 +#endif
1169 +
1170 + /* Perform synchronous SPI transfer */
1171 + if (spi_sync(s->spi, &spi_msg)) {
1172 + dev_err(&s->spi->dev, "spi_sync failure\n");
1173 + return -EIO;
1174 + }
1175 +
1176 +#ifdef DBG_TRACE_SPI_DATA
1177 + if (spi_xfer.rx_buf) {
1178 + int i;
1179 + printk("rx len %d:\n", spi_xfer.len);
1180 + for (i = 0 ; i < spi_xfer.len && i < 32 ; i++) {
1181 + printk(" %x", ((u8*)spi_xfer.rx_buf)[i]);
1182 + }
1183 + printk("\n");
1184 + }
1185 +#endif
1186 + return 0;
1187 +}
1188 +
1189 +/* Puts received data to circular buffer */
1190 +static void put_data_to_circ_buf(struct max3107_port *s, unsigned char *data,
1191 + int len)
1192 +{
1193 + struct uart_port *port = &s->port;
1194 + struct tty_struct *tty;
1195 +
1196 + DBG_TRACE("enter\n");
1197 +
1198 + if (!port->state) {
1199 + /* UART is not open */
1200 + dev_warn(&s->spi->dev, "UART is closed\n");
1201 + return;
1202 + }
1203 +
1204 + tty = port->state->port.tty;
1205 + if (!tty) {
1206 + /* TTY is not open */
1207 + dev_warn(&s->spi->dev, "TTY is closed\n");
1208 + return;
1209 + }
1210 +
1211 + /* Insert received data */
1212 + tty_insert_flip_string(tty, data, len);
1213 + /* Update RX counter */
1214 + port->icount.rx += len;
1215 +}
1216 +
1217 +/* Handle data receiving */
1218 +static void max3107_handlerx(struct max3107_port *s, u16 rxlvl)
1219 +{
1220 + int i;
1221 + int j;
1222 + int len; /* SPI transfer buffer length */
1223 + u16 buf[MAX3107_RX_FIFO_SIZE+2]; /* SPI transfer buffer
1224 + * +2 for RX FIFO interrupt
1225 + * disabling and RX level query
1226 + */
1227 + u8 valid_str[MAX3107_RX_FIFO_SIZE];
1228 +
1229 + DBG_TRACE("enter\n");
1230 +
1231 + if (!s->rx_enabled) {
1232 + /* RX is disabled */
1233 + return;
1234 + }
1235 +
1236 + if (rxlvl == 0) {
1237 + /* RX fifo is empty */
1238 + return;
1239 + } else if (rxlvl >= MAX3107_RX_FIFO_SIZE) {
1240 + dev_warn(&s->spi->dev, "Possible RX FIFO overrun %d\n", rxlvl);
1241 + /* Ensure sanity of RX level */
1242 + rxlvl = MAX3107_RX_FIFO_SIZE;
1243 + }
1244 +
1245 + while (rxlvl) {
1246 + DBG_TRACE("rxlvl %d\n", rxlvl);
1247 + /* Clear buffer */
1248 + memset(buf, 0, sizeof(buf));
1249 + len = 0;
1250 + if (s->irqen_reg & MAX3107_IRQ_RXFIFO_BIT) {
1251 + /* First disable RX FIFO interrupt */
1252 + DBG_TRACE("Disabling RX INT\n");
1253 + buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
1254 + spin_lock(&s->data_lock);
1255 + s->irqen_reg &= ~MAX3107_IRQ_RXFIFO_BIT;
1256 + buf[0] |= s->irqen_reg;
1257 + spin_unlock(&s->data_lock);
1258 + len++;
1259 + }
1260 + /* Just increase the length by amount of words in FIFO since
1261 + * buffer was zeroed and SPI transfer of 0x0000 means reading
1262 + * from RX FIFO
1263 + */
1264 + len += rxlvl;
1265 + /* Append RX level query */
1266 + buf[len] = MAX3107_RXFIFOLVL_REG;
1267 + len++;
1268 +
1269 + /* Perform the SPI transfer */
1270 + if (max3107_rw(s, (u8 *)buf, (u8 *)buf, len*2)) {
1271 + dev_err(&s->spi->dev,
1272 + "SPI transfer for RX handling failed\n");
1273 + return;
1274 + }
1275 +
1276 + /* Skip RX FIFO interrupt disabling word if it was added */
1277 + j = ((len-1)-rxlvl);
1278 + /* Read received words */
1279 + for (i = 0; i < rxlvl; i++, j++) {
1280 + valid_str[i] = (u8)buf[j];
1281 + }
1282 + put_data_to_circ_buf(s, valid_str, rxlvl);
1283 + /* Get new RX level */
1284 + rxlvl = (buf[len-1] & MAX3107_SPI_RX_DATA_MASK);
1285 + }
1286 +
1287 + if (s->rx_enabled) {
1288 + /* RX still enabled, re-enable RX FIFO interrupt */
1289 + DBG_TRACE("Enabling RX INT\n");
1290 + buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
1291 + spin_lock(&s->data_lock);
1292 + s->irqen_reg |= MAX3107_IRQ_RXFIFO_BIT;
1293 + buf[0] |= s->irqen_reg;
1294 + spin_unlock(&s->data_lock);
1295 + if (max3107_rw(s, (u8 *)buf, NULL, 2)) {
1296 + dev_err(&s->spi->dev,
1297 + "RX FIFO interrupt enabling failed\n");
1298 + }
1299 + }
1300 +
1301 + /* Push the received data to receivers */
1302 + tty_flip_buffer_push(s->port.state->port.tty);
1303 +}
1304 +
1305 +
1306 +/* Handle data sending */
1307 +static void max3107_handletx(struct max3107_port *s)
1308 +{
1309 + struct circ_buf *xmit = &s->port.state->xmit;
1310 + int i;
1311 + int len; /* SPI transfer buffer length */
1312 + u16 buf[MAX3107_TX_FIFO_SIZE+3]; /* SPI transfer buffer
1313 + * +3 for TX FIFO empty
1314 + * interrupt disabling and
1315 + * enabling and TX enabling
1316 + */
1317 +
1318 + DBG_TRACE("enter\n");
1319 +
1320 + if (!s->tx_fifo_empty) {
1321 + /* Don't send more data before previous data is sent */
1322 + return;
1323 + }
1324 +
1325 + if (uart_circ_empty(xmit) || uart_tx_stopped(&s->port)) {
1326 + /* No data to send or TX is stopped */
1327 + return;
1328 + }
1329 +
1330 + /* Get length of data pending in circular buffer */
1331 + len = uart_circ_chars_pending(xmit);
1332 + if (len) {
1333 + /* Limit to size of TX FIFO */
1334 + if (len > MAX3107_TX_FIFO_SIZE)
1335 + len = MAX3107_TX_FIFO_SIZE;
1336 +
1337 + DBG_TRACE("txlen %d\n", len);
1338 +
1339 + /* Update TX counter */
1340 + s->port.icount.tx += len;
1341 +
1342 + /* TX FIFO will no longer be empty */
1343 + s->tx_fifo_empty = 0;
1344 +
1345 + i = 0;
1346 + if (s->irqen_reg & MAX3107_IRQ_TXEMPTY_BIT) {
1347 + /* First disable TX empty interrupt */
1348 + DBG_TRACE("Disabling TE INT\n");
1349 + buf[i] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
1350 + spin_lock(&s->data_lock);
1351 + s->irqen_reg &= ~MAX3107_IRQ_TXEMPTY_BIT;
1352 + buf[i] |= s->irqen_reg;
1353 + spin_unlock(&s->data_lock);
1354 + i++;
1355 + len++;
1356 + }
1357 +
1358 + /* Add data to send */
1359 + for ( ; i < len ; i++ ) {
1360 + buf[i] = (MAX3107_WRITE_BIT | MAX3107_THR_REG);
1361 + buf[i] |= ((u16)xmit->buf[xmit->tail] &
1362 + MAX3107_SPI_TX_DATA_MASK);
1363 + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1364 + }
1365 +
1366 + if (!(s->irqen_reg & MAX3107_IRQ_TXEMPTY_BIT)) {
1367 + /* Enable TX empty interrupt */
1368 + DBG_TRACE("Enabling TE INT\n");
1369 + buf[i] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
1370 + spin_lock(&s->data_lock);
1371 + s->irqen_reg |= MAX3107_IRQ_TXEMPTY_BIT;
1372 + buf[i] |= s->irqen_reg;
1373 + spin_unlock(&s->data_lock);
1374 + i++;
1375 + len++;
1376 + }
1377 + if (!s->tx_enabled) {
1378 + /* Enable TX */
1379 + DBG_TRACE("Enable TX\n");
1380 + buf[i] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
1381 + spin_lock(&s->data_lock);
1382 + s->mode1_reg &= ~MAX3107_MODE1_TXDIS_BIT;
1383 + buf[i] |= s->mode1_reg;
1384 + spin_unlock(&s->data_lock);
1385 + s->tx_enabled = 1;
1386 + i++;
1387 + len++;
1388 + }
1389 +
1390 + /* Perform the SPI transfer */
1391 + if (max3107_rw(s, (u8 *)buf, NULL, len*2)) {
1392 + dev_err(&s->spi->dev,
1393 + "SPI transfer for TX handling failed\n");
1394 + return;
1395 + }
1396 + }
1397 +
1398 + /* Indicate wake up if circular buffer is getting low on data */
1399 + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1400 + uart_write_wakeup(&s->port);
1401 +
1402 +}
1403 +
1404 +/* Handle interrupts
1405 + * Also reads and returns current RX FIFO level
1406 + */
1407 +static u16 handle_interrupt(struct max3107_port *s)
1408 +{
1409 + u16 buf[4]; /* Buffer for SPI transfers */
1410 + u8 irq_status;
1411 + u16 rx_level;
1412 +
1413 + DBG_TRACE("enter\n");
1414 +
1415 + /* Read IRQ status register */
1416 + buf[0] = MAX3107_IRQSTS_REG;
1417 + /* Read status IRQ status register */
1418 + buf[1] = MAX3107_STS_IRQSTS_REG;
1419 + /* Read LSR IRQ status register */
1420 + buf[2] = MAX3107_LSR_IRQSTS_REG;
1421 + /* Query RX level */
1422 + buf[3] = MAX3107_RXFIFOLVL_REG;
1423 +
1424 + if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 8)) {
1425 + dev_err(&s->spi->dev,
1426 + "SPI transfer for interrupt handling failed\n");
1427 + return 0;
1428 + }
1429 +
1430 + irq_status = (u8)buf[0];
1431 + DBG_TRACE("IRQSTS %x\n", irq_status);
1432 + rx_level = (buf[3] & MAX3107_SPI_RX_DATA_MASK);
1433 +
1434 + if (irq_status & MAX3107_IRQ_LSR_BIT) {
1435 + /* LSR interrupt */
1436 + if ( buf[2] & MAX3107_LSR_RXTO_BIT ) {
1437 + /* RX timeout interrupt,
1438 + * handled by normal RX handling
1439 + */
1440 + DBG_TRACE("RX TO INT\n");
1441 + }
1442 + }
1443 +
1444 + if (irq_status & MAX3107_IRQ_TXEMPTY_BIT) {
1445 + /* Tx empty interrupt,
1446 + * disable TX and set tx_fifo_empty flag
1447 + */
1448 + DBG_TRACE("TE INT, disabling TX\n");
1449 + buf[0] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
1450 + spin_lock(&s->data_lock);
1451 + s->mode1_reg |= MAX3107_MODE1_TXDIS_BIT;
1452 + buf[0] |= s->mode1_reg;
1453 + spin_unlock(&s->data_lock);
1454 + if (max3107_rw(s, (u8 *)buf, NULL, 2))
1455 + dev_err(&s->spi->dev,
1456 + "SPI transfer for TX disabling failed\n");
1457 + s->tx_enabled = 0;
1458 + s->tx_fifo_empty = 1;
1459 + }
1460 +
1461 + if (irq_status & MAX3107_IRQ_RXFIFO_BIT) {
1462 + /* RX FIFO interrupt,
1463 + * handled by normal RX handling
1464 + */
1465 + DBG_TRACE("RFIFO INT\n");
1466 + }
1467 +
1468 + /* Return RX level */
1469 + return rx_level;
1470 +}
1471 +
1472 +/* Trigger work thread*/
1473 +static void max3107_dowork(struct max3107_port *s)
1474 +{
1475 + if (!work_pending(&s->work) && !freezing(current) && !s->suspended)
1476 + queue_work(s->workqueue, &s->work);
1477 +}
1478 +
1479 +/* Work thread */
1480 +static void max3107_work(struct work_struct *w)
1481 +{
1482 + struct max3107_port *s = container_of(w, struct max3107_port, work);
1483 + u16 rxlvl = 0;
1484 + int len; /* SPI transfer buffer length */
1485 + u16 buf[5]; /* Buffer for SPI transfers */
1486 +
1487 + DBG_TRACE("enter\n");
1488 +
1489 + /* Start by reading current RX FIFO level */
1490 + buf[0] = MAX3107_RXFIFOLVL_REG;
1491 + if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
1492 + dev_err(&s->spi->dev,
1493 + "SPI transfer for RX level query failed\n");
1494 + rxlvl = 0;
1495 + } else {
1496 + rxlvl = (buf[0] & MAX3107_SPI_RX_DATA_MASK);
1497 + }
1498 +
1499 + do {
1500 + DBG_TRACE("rxlvl %d\n", rxlvl);
1501 +
1502 + /* Handle RX */
1503 + max3107_handlerx(s, rxlvl);
1504 + rxlvl = 0;
1505 +
1506 + if (s->handle_irq) {
1507 + /* Handle pending interrupts
1508 + * We also get new RX FIFO level since new data may
1509 + * have been received while pushing received data to
1510 + * receivers
1511 + */
1512 + s->handle_irq = 0;
1513 + rxlvl = handle_interrupt(s);
1514 + }
1515 +
1516 + /* Handle TX */
1517 + max3107_handletx(s);
1518 +
1519 + /* Handle configuration changes */
1520 + len = 0;
1521 + spin_lock(&s->data_lock);
1522 + if (s->mode1_commit) {
1523 + DBG_TRACE("mode1_commit\n");
1524 + buf[len] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
1525 + buf[len++] |= s->mode1_reg;
1526 + s->mode1_commit = 0;
1527 + }
1528 + if (s->lcr_commit) {
1529 + DBG_TRACE("lcr_commit\n");
1530 + buf[len] = (MAX3107_WRITE_BIT | MAX3107_LCR_REG);
1531 + buf[len++] |= s->lcr_reg;
1532 + s->lcr_commit = 0;
1533 + }
1534 + if (s->brg_commit) {
1535 + DBG_TRACE("brg_commit\n");
1536 + buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVMSB_REG);
1537 + buf[len++] |= ((s->brg_cfg >> 16) &
1538 + MAX3107_SPI_TX_DATA_MASK);
1539 + buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVLSB_REG);
1540 + buf[len++] |= ((s->brg_cfg >> 8) &
1541 + MAX3107_SPI_TX_DATA_MASK);
1542 + buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGCFG_REG);
1543 + buf[len++] |= ((s->brg_cfg) & 0xff);
1544 + s->brg_commit = 0;
1545 + }
1546 + spin_unlock(&s->data_lock);
1547 +
1548 + if (len > 0) {
1549 + if (max3107_rw(s, (u8 *)buf, NULL, len*2))
1550 + dev_err(&s->spi->dev,
1551 + "SPI transfer for config failed\n");
1552 + }
1553 +
1554 + /* Reloop if interrupt handling indicated data in RX FIFO */
1555 + } while (rxlvl);
1556 +
1557 +}
1558 +
1559 +/* Set sleep mode */
1560 +static void max3107_set_sleep(struct max3107_port *s, int mode)
1561 +{
1562 + u16 buf[1]; /* Buffer for SPI transfer */
1563 +
1564 + DBG_TRACE("enter, mode %d\n", mode);
1565 +
1566 + buf[0] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
1567 + spin_lock(&s->data_lock);
1568 + switch (mode) {
1569 + case MAX3107_DISABLE_FORCED_SLEEP:
1570 + s->mode1_reg &= ~MAX3107_MODE1_FORCESLEEP_BIT;
1571 + break;
1572 + case MAX3107_ENABLE_FORCED_SLEEP:
1573 + s->mode1_reg |= MAX3107_MODE1_FORCESLEEP_BIT;
1574 + break;
1575 + case MAX3107_DISABLE_AUTOSLEEP:
1576 + s->mode1_reg &= ~MAX3107_MODE1_AUTOSLEEP_BIT;
1577 + break;
1578 + case MAX3107_ENABLE_AUTOSLEEP:
1579 + s->mode1_reg |= MAX3107_MODE1_AUTOSLEEP_BIT;
1580 + break;
1581 + default:
1582 + spin_unlock(&s->data_lock);
1583 + dev_warn(&s->spi->dev, "invalid sleep mode\n");
1584 + return;
1585 + }
1586 + buf[0] |= s->mode1_reg;
1587 + spin_unlock(&s->data_lock);
1588 +
1589 + if (max3107_rw(s, (u8 *)buf, NULL, 2))
1590 + dev_err(&s->spi->dev, "SPI transfer for sleep mode failed\n");
1591 +
1592 + if (mode == MAX3107_DISABLE_AUTOSLEEP ||
1593 + mode == MAX3107_DISABLE_FORCED_SLEEP ) {
1594 + msleep(MAX3107_WAKEUP_DELAY);
1595 + }
1596 +}
1597 +
1598 +/* Perform full register initialization */
1599 +static void max3107_register_init(struct max3107_port *s)
1600 +{
1601 + int len = 0; /* SPI transfer buffer length */
1602 + u16 buf[11]; /* Buffer for SPI transfers */
1603 +
1604 + DBG_TRACE("enter\n");
1605 +
1606 + /* 1. Configure baud rate, 9600 as default */
1607 + s->baud = 9600;
1608 + if (s->ext_clk)
1609 + s->brg_cfg = MAX3107_BRG_B9600;
1610 + else
1611 + s->brg_cfg = MAX3107_BRG_IB9600;
1612 + buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVMSB_REG);
1613 + buf[len++] |= ((s->brg_cfg >> 16) & MAX3107_SPI_TX_DATA_MASK);
1614 + buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVLSB_REG);
1615 + buf[len++] |= ((s->brg_cfg >> 8) & MAX3107_SPI_TX_DATA_MASK);
1616 + buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGCFG_REG);
1617 + buf[len++] |= ((s->brg_cfg) & 0xff);
1618 +
1619 + /* 2. Configure LCR register, 8N1 mode by default */
1620 + s->lcr_reg = MAX3107_LCR_WORD_LEN_8;
1621 + buf[len] = (MAX3107_WRITE_BIT | MAX3107_LCR_REG);
1622 + buf[len++] |= s->lcr_reg;
1623 +
1624 + /* 3. Configure MODE 1 register */
1625 + s->mode1_reg = 0;
1626 + /* Enable IRQ pin */
1627 + s->mode1_reg |= MAX3107_MODE1_IRQSEL_BIT;
1628 + /* Disable TX */
1629 + s->mode1_reg |= MAX3107_MODE1_TXDIS_BIT;
1630 + s->tx_enabled = 0;
1631 + /* RX is enabled */
1632 + s->rx_enabled = 1;
1633 + buf[len] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
1634 + buf[len++] |= s->mode1_reg;
1635 +
1636 + /* 4. Configure MODE 2 register */
1637 + buf[len] = (MAX3107_WRITE_BIT | MAX3107_MODE2_REG);
1638 + if (s->loopback) {
1639 + /* Enable loopback */
1640 + buf[len] |= MAX3107_MODE2_LOOPBACK_BIT;
1641 + }
1642 + /* Reset FIFOs */
1643 + buf[len++] |= MAX3107_MODE2_FIFORST_BIT;
1644 + s->tx_fifo_empty = 1;
1645 +
1646 + /* 5. Configure FIFO trigger level register */
1647 + buf[len] = (MAX3107_WRITE_BIT | MAX3107_FIFOTRIGLVL_REG);
1648 + /* RX FIFO trigger for 16 words, TX FIFO trigger not used */
1649 + buf[len++] |= (MAX3107_FIFOTRIGLVL_RX(16) | MAX3107_FIFOTRIGLVL_TX(0));
1650 +
1651 + /* 6. Configure flow control levels */
1652 + buf[len] = (MAX3107_WRITE_BIT | MAX3107_FLOWLVL_REG);
1653 + /* Flow control halt level 96, resume level 48 */
1654 + buf[len++] |= (MAX3107_FLOWLVL_RES(48) | MAX3107_FLOWLVL_HALT(96));
1655 +
1656 + /* 7. Configure flow control */
1657 + buf[len] = (MAX3107_WRITE_BIT | MAX3107_FLOWCTRL_REG);
1658 + /* Enable auto CTS and auto RTS flow control */
1659 + buf[len++] |= (MAX3107_FLOWCTRL_AUTOCTS_BIT |
1660 + MAX3107_FLOWCTRL_AUTORTS_BIT);
1661 +
1662 + /* 8. Configure RX timeout register */
1663 + buf[len] = (MAX3107_WRITE_BIT | MAX3107_RXTO_REG);
1664 + /* Timeout after 48 character intervals */
1665 + buf[len++] |= 0x0030;
1666 +
1667 + /* 9. Configure LSR interrupt enable register */
1668 + buf[len] = (MAX3107_WRITE_BIT | MAX3107_LSR_IRQEN_REG);
1669 + /* Enable RX timeout interrupt */
1670 + buf[len++] |= MAX3107_LSR_RXTO_BIT;
1671 +
1672 + /* Perform SPI transfer */
1673 + if (max3107_rw(s, (u8 *)buf, NULL, len*2))
1674 + dev_err(&s->spi->dev, "SPI transfer for init failed\n");
1675 +
1676 + len = 0;
1677 + /* 10. Clear IRQ status register by reading it */
1678 + buf[len++] = MAX3107_IRQSTS_REG;
1679 +
1680 + /* 11. Configure interrupt enable register */
1681 + /* Enable LSR interrupt */
1682 + s->irqen_reg = MAX3107_IRQ_LSR_BIT;
1683 + /* Enable RX FIFO interrupt */
1684 + s->irqen_reg |= MAX3107_IRQ_RXFIFO_BIT;
1685 + buf[len] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
1686 + buf[len++] |= s->irqen_reg;
1687 +
1688 + /* 12. Clear FIFO reset that was set in step 6 */
1689 + buf[len] = (MAX3107_WRITE_BIT | MAX3107_MODE2_REG);
1690 + if (s->loopback) {
1691 + /* Keep loopback enabled */
1692 + buf[len] |= MAX3107_MODE2_LOOPBACK_BIT;
1693 + }
1694 + buf[len++] |= 0x0000;
1695 +
1696 + /* Perform SPI transfer */
1697 + if (max3107_rw(s, (u8 *)buf, (u8 *)buf, len*2))
1698 + dev_err(&s->spi->dev, "SPI transfer for init failed\n");
1699 +
1700 +}
1701 +
1702 +/* IRQ handler */
1703 +static irqreturn_t max3107_irq(int irqno, void *dev_id)
1704 +{
1705 + struct max3107_port *s = dev_id;
1706 +
1707 + if (irqno != s->spi->irq) {
1708 + /* Unexpected IRQ */
1709 + return IRQ_NONE;
1710 + }
1711 +
1712 + /* Indicate irq */
1713 + s->handle_irq = 1;
1714 +
1715 + /* Trigger work thread */
1716 + max3107_dowork(s);
1717 +
1718 + return IRQ_HANDLED;
1719 +}
1720 +
1721 +/* HW suspension function
1722 + *
1723 + * Currently autosleep is used to decrease current consumption, alternative
1724 + * approach would be to set the chip to reset mode if UART is not being
1725 + * used but that would mess the GPIOs
1726 + *
1727 + */
1728 +static void max3107_hw_susp(struct max3107_port *s, int suspend)
1729 +{
1730 + DBG_TRACE("enter, suspend %d\n", suspend);
1731 +
1732 + if (suspend) {
1733 + /* Suspend requested,
1734 + * enable autosleep to decrease current consumption
1735 + */
1736 + s->suspended = 1;
1737 + max3107_set_sleep(s, MAX3107_ENABLE_AUTOSLEEP);
1738 + } else {
1739 + /* Resume requested,
1740 + * disable autosleep
1741 + */
1742 + s->suspended = 0;
1743 + max3107_set_sleep(s, MAX3107_DISABLE_AUTOSLEEP);
1744 + }
1745 +}
1746 +
1747 +/* Modem status IRQ enabling */
1748 +static void max3107_enable_ms(struct uart_port *port)
1749 +{
1750 + /* Modem status not supported */
1751 +}
1752 +
1753 +/* Data send function */
1754 +static void max3107_start_tx(struct uart_port *port)
1755 +{
1756 + struct max3107_port *s = container_of(port, struct max3107_port, port);
1757 +
1758 + DBG_TRACE("enter\n");
1759 +
1760 + /* Trigger work thread for sending data */
1761 + max3107_dowork(s);
1762 +}
1763 +
1764 +/* Function for checking that there is no pending transfers */
1765 +static unsigned int max3107_tx_empty(struct uart_port *port)
1766 +{
1767 + struct max3107_port *s = container_of(port, struct max3107_port, port);
1768 +
1769 + DBG_TRACE("returning %d\n",
1770 + (s->tx_fifo_empty && uart_circ_empty(&s->port.state->xmit)));
1771 + return (s->tx_fifo_empty && uart_circ_empty(&s->port.state->xmit));
1772 +}
1773 +
1774 +/* Function for stopping RX */
1775 +static void max3107_stop_rx(struct uart_port *port)
1776 +{
1777 + struct max3107_port *s = container_of(port, struct max3107_port, port);
1778 +
1779 + DBG_TRACE("enter\n");
1780 +
1781 + /* Set RX disabled in MODE 1 register */
1782 + spin_lock(&s->data_lock);
1783 + s->mode1_reg |= MAX3107_MODE1_RXDIS_BIT;
1784 + s->mode1_commit = 1;
1785 + spin_unlock(&s->data_lock);
1786 + /* Set RX disabled */
1787 + s->rx_enabled = 0;
1788 + /* Trigger work thread for doing the actual configuration change */
1789 + max3107_dowork(s);
1790 +}
1791 +
1792 +/* Function for returning control pin states */
1793 +static unsigned int max3107_get_mctrl(struct uart_port *port)
1794 +{
1795 + /* DCD and DSR are not wired and CTS/RTS is handled automatically
1796 + * so just indicate DSR and CAR asserted
1797 + */
1798 + return (TIOCM_DSR | TIOCM_CAR);
1799 +}
1800 +
1801 +/* Function for setting control pin states */
1802 +static void max3107_set_mctrl(struct uart_port *port, unsigned int mctrl)
1803 +{
1804 + /* DCD and DSR are not wired and CTS/RTS is hadnled automatically
1805 + * so do nothing
1806 + */
1807 +}
1808 +
1809 +/* Function for configuring UART parameters */
1810 +static void max3107_set_termios(struct uart_port *port,
1811 + struct ktermios *termios,
1812 + struct ktermios *old)
1813 +{
1814 + struct max3107_port *s = container_of(port, struct max3107_port, port);
1815 + struct tty_struct *tty;
1816 + int baud;
1817 + u16 new_lcr = 0;
1818 + u32 new_brg = 0;
1819 +
1820 + DBG_TRACE("enter\n");
1821 +
1822 + if (!port->state) {
1823 + /* UART is not open */
1824 + dev_warn(&s->spi->dev, "UART is closed\n");
1825 + return;
1826 + }
1827 +
1828 + tty = port->state->port.tty;
1829 + if (!tty) {
1830 + /* TTY is not open */
1831 + dev_warn(&s->spi->dev, "TTY is closed\n");
1832 + return;
1833 + }
1834 +
1835 + if (old) {
1836 + if ((termios->c_cflag == old->c_cflag) &&
1837 + (RELEVANT_IFLAG(termios->c_iflag) ==
1838 + RELEVANT_IFLAG(old->c_iflag))) {
1839 + /* Nothing relevant is changing */
1840 + return;
1841 + }
1842 + }
1843 +
1844 + /* Get new LCR register values */
1845 + /* Word size */
1846 + if ((termios->c_cflag & CSIZE) == CS7)
1847 + new_lcr |= MAX3107_LCR_WORD_LEN_7;
1848 + else
1849 + new_lcr |= MAX3107_LCR_WORD_LEN_8;
1850 +
1851 + /* Parity */
1852 + if (termios->c_cflag & PARENB) {
1853 + new_lcr |= MAX3107_LCR_PARITY_BIT;
1854 + if (!(termios->c_cflag & PARODD))
1855 + new_lcr |= MAX3107_LCR_EVENPARITY_BIT;
1856 + }
1857 +
1858 + /* Stop bits */
1859 + if (termios->c_cflag & CSTOPB) {
1860 + /* 2 stop bits */
1861 + new_lcr |= MAX3107_LCR_STOPLEN_BIT;
1862 + }
1863 +
1864 + /* Mask termios capabilities we don't support */
1865 + termios->c_cflag &= ~CMSPAR;
1866 +
1867 + /* Set status ignore mask */
1868 + s->port.ignore_status_mask = 0;
1869 + if (termios->c_iflag & IGNPAR)
1870 + s->port.ignore_status_mask |= MAX3107_ALL_ERRORS;
1871 +
1872 + /* Set low latency to immediately handle pushed data */
1873 + s->port.state->port.tty->low_latency = 1;
1874 +
1875 + /* Get new baud rate generator configuration */
1876 + baud = tty_get_baud_rate(tty);
1877 + switch (baud) {
1878 + case 300:
1879 + new_brg = s->ext_clk ? MAX3107_BRG_B300 : MAX3107_BRG_IB300;
1880 + break;
1881 + case 600:
1882 + new_brg = s->ext_clk ? MAX3107_BRG_B600 : MAX3107_BRG_IB600;
1883 + break;
1884 + case 1200:
1885 + new_brg = s->ext_clk ? MAX3107_BRG_B1200 : MAX3107_BRG_IB1200;
1886 + break;
1887 + case 2400:
1888 + new_brg = s->ext_clk ? MAX3107_BRG_B2400 : MAX3107_BRG_IB2400;
1889 + break;
1890 + case 4800:
1891 + new_brg = s->ext_clk ? MAX3107_BRG_B4800 : MAX3107_BRG_IB4800;
1892 + break;
1893 + case 9600:
1894 + new_brg = s->ext_clk ? MAX3107_BRG_B9600 : MAX3107_BRG_IB9600;
1895 + break;
1896 + case 19200:
1897 + new_brg = s->ext_clk ? MAX3107_BRG_B19200 : MAX3107_BRG_IB19200;
1898 + break;
1899 + case 38400:
1900 + new_brg = s->ext_clk ? MAX3107_BRG_B38400 : MAX3107_BRG_IB38400;
1901 + break;
1902 + case 57600:
1903 + new_brg = s->ext_clk ? MAX3107_BRG_B57600 : MAX3107_BRG_IB57600;
1904 + break;
1905 + case 115200:
1906 + new_brg = s->ext_clk ? MAX3107_BRG_B115200 : MAX3107_BRG_IB115200;
1907 + break;
1908 + case 230400:
1909 + new_brg = s->ext_clk ? MAX3107_BRG_B230400 : MAX3107_BRG_IB230400;
1910 + break;
1911 + case 460800:
1912 + new_brg = s->ext_clk ? MAX3107_BRG_B460800 : MAX3107_BRG_IB460800;
1913 + break;
1914 + case 921600:
1915 + new_brg = s->ext_clk ? MAX3107_BRG_B921600 : MAX3107_BRG_IB921600;
1916 + break;
1917 + default:
1918 + /* Use previous */
1919 + baud = s->baud;
1920 + new_brg = s->brg_cfg;
1921 + tty_termios_encode_baud_rate(termios, baud, baud);
1922 + }
1923 + s->baud = baud;
1924 +
1925 + /* Update timeout according to new baud rate */
1926 + uart_update_timeout(port, termios->c_cflag, baud);
1927 +
1928 + spin_lock(&s->data_lock);
1929 + if (s->lcr_reg != new_lcr) {
1930 + s->lcr_reg = new_lcr;
1931 + s->lcr_commit = 1;
1932 + }
1933 + if (s->brg_cfg != new_brg) {
1934 + s->brg_cfg = new_brg;
1935 + s->brg_commit = 1;
1936 + }
1937 + spin_unlock(&s->data_lock);
1938 +
1939 + /* Trigger work thread for doing the actual configuration change */
1940 + max3107_dowork(s);
1941 +}
1942 +
1943 +/* Port shutdown function */
1944 +static void max3107_shutdown(struct uart_port *port)
1945 +{
1946 + struct max3107_port *s = container_of(port, struct max3107_port, port);
1947 +
1948 + DBG_TRACE("enter\n");
1949 +
1950 + if (s->suspended) {
1951 + /* Resume HW */
1952 + max3107_hw_susp(s, 0);
1953 + }
1954 +
1955 + /* Free the interrupt */
1956 + free_irq(s->spi->irq, s);
1957 +
1958 + if (s->workqueue) {
1959 + /* Flush and destroy work queue */
1960 + flush_workqueue(s->workqueue);
1961 + destroy_workqueue(s->workqueue);
1962 + s->workqueue = NULL;
1963 + }
1964 +
1965 + /* Suspend HW */
1966 + max3107_hw_susp(s, 1);
1967 +}
1968 +
1969 +/* Port startup function */
1970 +static int max3107_startup(struct uart_port *port)
1971 +{
1972 + struct max3107_port *s = container_of(port, struct max3107_port, port);
1973 +
1974 + DBG_TRACE("enter\n");
1975 +
1976 + /* Initialize work queue */
1977 + s->workqueue = create_freezeable_workqueue("max3107");
1978 + if (!s->workqueue) {
1979 + dev_err(&s->spi->dev, "Workqueue creation failed\n");
1980 + return -EBUSY;
1981 + }
1982 + INIT_WORK(&s->work, max3107_work);
1983 +
1984 + /* Setup IRQ */
1985 + if (request_irq(s->spi->irq, max3107_irq, IRQF_TRIGGER_FALLING,
1986 + "max3107", s)) {
1987 + dev_err(&s->spi->dev, "IRQ reguest failed\n");
1988 + destroy_workqueue(s->workqueue);
1989 + s->workqueue = NULL;
1990 + return -EBUSY;
1991 + }
1992 +
1993 + /* Resume HW */
1994 + max3107_hw_susp(s, 0);
1995 +
1996 + /* Init registers */
1997 + max3107_register_init(s);
1998 +
1999 + return 0;
2000 +}
2001 +
2002 +/* Port type function */
2003 +static const char *max3107_type(struct uart_port *port)
2004 +{
2005 + struct max3107_port *s = container_of(port, struct max3107_port, port);
2006 + return s->spi->modalias;
2007 +}
2008 +
2009 +/* Port release function */
2010 +static void max3107_release_port(struct uart_port *port)
2011 +{
2012 + /* Do nothing */
2013 +}
2014 +
2015 +/* Port request function */
2016 +static int max3107_request_port(struct uart_port *port)
2017 +{
2018 + /* Do nothing */
2019 + return 0;
2020 +}
2021 +
2022 +/* Port config function */
2023 +static void max3107_config_port(struct uart_port *port, int flags)
2024 +{
2025 + struct max3107_port *s = container_of(port, struct max3107_port, port);
2026 +
2027 + /* Use PORT_MAX3100 since we are at least int the same serie */
2028 + s->port.type = PORT_MAX3100;
2029 +}
2030 +
2031 +/* Port verify function */
2032 +static int max3107_verify_port(struct uart_port *port,
2033 + struct serial_struct *ser)
2034 +{
2035 + if (ser->type == PORT_UNKNOWN || ser->type == PORT_MAX3100)
2036 + return 0;
2037 +
2038 + return -EINVAL;
2039 +}
2040 +
2041 +/* Port stop TX function */
2042 +static void max3107_stop_tx(struct uart_port *port)
2043 +{
2044 + /* Do nothing */
2045 +}
2046 +
2047 +/* Port break control function */
2048 +static void max3107_break_ctl(struct uart_port *port, int break_state)
2049 +{
2050 + /* We don't support break control, do nothing */
2051 +}
2052 +
2053 +/* GPIO direction query function */
2054 +static enum gpio_direction max3107_gpio_get_direction(struct gpio_chip *chip,
2055 + unsigned offset)
2056 +{
2057 + struct max3107_port *s = container_of(chip, struct max3107_port, chip);
2058 + u16 buf[1]; /* Buffer for SPI transfer */
2059 +
2060 + DBG_TRACE("enter\n");
2061 +
2062 + if (offset >= MAX3107_GPIO_COUNT) {
2063 + dev_err(&s->spi->dev, "Invalid GPIO\n");
2064 + return -EINVAL;
2065 + }
2066 +
2067 + /* Read current GPIO configuration register */
2068 + buf[0] = MAX3107_GPIOCFG_REG;
2069 + /* Perform SPI transfer */
2070 + if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
2071 + dev_err(&s->spi->dev,
2072 + "SPI transfer for GPIO config read failed\n");
2073 + return -EIO;
2074 + }
2075 + buf[0] &= MAX3107_SPI_RX_DATA_MASK;
2076 +
2077 + /* Check the direction bit */
2078 + if (buf[0] & (0x0001 << offset))
2079 + return DIRECTION_OUT;
2080 + return DIRECTION_IN;
2081 +}
2082 +
2083 +/* GPIO direction to input function */
2084 +static int max3107_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2085 +{
2086 + struct max3107_port *s = container_of(chip, struct max3107_port, chip);
2087 + u16 buf[1]; /* Buffer for SPI transfer */
2088 +
2089 + DBG_TRACE("enter\n");
2090 +
2091 + if (offset >= MAX3107_GPIO_COUNT) {
2092 + dev_err(&s->spi->dev, "Invalid GPIO\n");
2093 + return -EINVAL;
2094 + }
2095 +
2096 + /* Read current GPIO configuration register */
2097 + buf[0] = MAX3107_GPIOCFG_REG;
2098 + /* Perform SPI transfer */
2099 + if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
2100 + dev_err(&s->spi->dev,
2101 + "SPI transfer for GPIO config read failed\n");
2102 + return -EIO;
2103 + }
2104 + buf[0] &= MAX3107_SPI_RX_DATA_MASK;
2105 +
2106 + /* Set GPIO to input */
2107 + buf[0] &= ~(0x0001 << offset);
2108 +
2109 + /* Write new GPIO configuration register value */
2110 + buf[0] |= (MAX3107_WRITE_BIT | MAX3107_GPIOCFG_REG);
2111 + /* Perform SPI transfer */
2112 + if (max3107_rw(s, (u8 *)buf, NULL, 2)) {
2113 + dev_err(&s->spi->dev,
2114 + "SPI transfer for GPIO config write failed\n");
2115 + return -EIO;
2116 + }
2117 + return 0;
2118 +}
2119 +
2120 +/* GPIO direction to output function */
2121 +static int max3107_gpio_direction_out(struct gpio_chip *chip, unsigned offset,
2122 + int value)
2123 +{
2124 + struct max3107_port *s = container_of(chip, struct max3107_port, chip);
2125 + u16 buf[2]; /* Buffer for SPI transfers */
2126 +
2127 + DBG_TRACE("enter\n");
2128 +
2129 + if (offset >= MAX3107_GPIO_COUNT) {
2130 + dev_err(&s->spi->dev, "Invalid GPIO\n");
2131 + return -EINVAL;
2132 + }
2133 +
2134 + /* Read current GPIO configuration and data registers */
2135 + buf[0] = MAX3107_GPIOCFG_REG;
2136 + buf[1] = MAX3107_GPIODATA_REG;
2137 + /* Perform SPI transfer */
2138 + if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 4)) {
2139 + dev_err(&s->spi->dev,
2140 + "SPI transfer for GPIO config and data read failed\n");
2141 + return -EIO;
2142 + }
2143 + buf[0] &= MAX3107_SPI_RX_DATA_MASK;
2144 + buf[1] &= MAX3107_SPI_RX_DATA_MASK;
2145 +
2146 + /* Set GPIO to output */
2147 + buf[0] |= (0x0001 << offset);
2148 + /* Set value */
2149 + if (value)
2150 + buf[1] |= (0x0001 << offset);
2151 + else
2152 + buf[1] &= ~(0x0001 << offset);
2153 +
2154 + /* Write new GPIO configuration and data register values */
2155 + buf[0] |= (MAX3107_WRITE_BIT | MAX3107_GPIOCFG_REG);
2156 + buf[1] |= (MAX3107_WRITE_BIT | MAX3107_GPIODATA_REG);
2157 + /* Perform SPI transfer */
2158 + if (max3107_rw(s, (u8 *)buf, NULL, 4)) {
2159 + dev_err(&s->spi->dev,
2160 + "SPI transfer for GPIO config and data write failed\n");
2161 + return -EIO;
2162 + }
2163 + return 0;
2164 +}
2165 +
2166 +/* GPIO value query function */
2167 +static int max3107_gpio_get(struct gpio_chip *chip, unsigned offset)
2168 +{
2169 + struct max3107_port *s = container_of(chip, struct max3107_port, chip);
2170 + u16 buf[1]; /* Buffer for SPI transfer */
2171 +
2172 + DBG_TRACE("enter\n");
2173 +
2174 + if (offset >= MAX3107_GPIO_COUNT) {
2175 + dev_err(&s->spi->dev, "Invalid GPIO\n");
2176 + return -EINVAL;
2177 + }
2178 +
2179 + /* Read current GPIO data register */
2180 + buf[0] = MAX3107_GPIODATA_REG;
2181 + /* Perform SPI transfer */
2182 + if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
2183 + dev_err(&s->spi->dev,
2184 + "SPI transfer for GPIO data read failed\n");
2185 + return -EIO;
2186 + }
2187 + buf[0] &= MAX3107_SPI_RX_DATA_MASK;
2188 +
2189 + /* Return value */
2190 + return buf[0] & (0x0001 << offset);
2191 +}
2192 +
2193 +/* GPIO value set function */
2194 +static void max3107_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2195 +{
2196 + struct max3107_port *s = container_of(chip, struct max3107_port, chip);
2197 + u16 buf[2]; /* Buffer for SPI transfers */
2198 +
2199 + DBG_TRACE("enter\n");
2200 +
2201 + if (offset >= MAX3107_GPIO_COUNT) {
2202 + dev_err(&s->spi->dev, "Invalid GPIO\n");
2203 + return;
2204 + }
2205 +
2206 + /* Read current GPIO configuration registers*/
2207 + buf[0] = MAX3107_GPIODATA_REG;
2208 + buf[1] = MAX3107_GPIOCFG_REG;
2209 + /* Perform SPI transfer */
2210 + if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 4)) {
2211 + dev_err(&s->spi->dev,
2212 + "SPI transfer for GPIO data and config read failed\n");
2213 + return;
2214 + }
2215 + buf[0] &= MAX3107_SPI_RX_DATA_MASK;
2216 + buf[1] &= MAX3107_SPI_RX_DATA_MASK;
2217 +
2218 + if (!(buf[1] & (0x0001 << offset))) {
2219 + /* Configured as input, can't set value */
2220 + dev_warn(&s->spi->dev,
2221 + "Trying to set value for input GPIO\n");
2222 + return;
2223 + }
2224 +
2225 + /* Set value */
2226 + if (value)
2227 + buf[0] |= (0x0001 << offset);
2228 + else
2229 + buf[0] &= ~(0x0001 << offset);
2230 +
2231 + /* Write new GPIO data register value */
2232 + buf[0] |= (MAX3107_WRITE_BIT | MAX3107_GPIODATA_REG);
2233 + /* Perform SPI transfer */
2234 + if (max3107_rw(s, (u8 *)buf, NULL, 2)) {
2235 + dev_err(&s->spi->dev,
2236 + "SPI transfer for GPIO data write failed\n");
2237 + }
2238 +}
2239 +
2240 +/* Platform data */
2241 +static struct max3107_plat max3107_plat_data = {
2242 + .loopback = 0,
2243 + .ext_clk = 1,
2244 +#ifdef CONFIG_MAX3107_LOW_POWER
2245 + .max3107_hw_suspend = &max3107_hw_susp,
2246 +#endif /* CONFIG_MAX3107_LOW_POWER */
2247 + .polled_mode = 0,
2248 + .poll_time = 0,
2249 +};
2250 +
2251 +/* Port functions */
2252 +static struct uart_ops max3107_ops = {
2253 + .tx_empty = max3107_tx_empty,
2254 + .set_mctrl = max3107_set_mctrl,
2255 + .get_mctrl = max3107_get_mctrl,
2256 + .stop_tx = max3107_stop_tx,
2257 + .start_tx = max3107_start_tx,
2258 + .stop_rx = max3107_stop_rx,
2259 + .enable_ms = max3107_enable_ms,
2260 + .break_ctl = max3107_break_ctl,
2261 + .startup = max3107_startup,
2262 + .shutdown = max3107_shutdown,
2263 + .set_termios = max3107_set_termios,
2264 + .type = max3107_type,
2265 + .release_port = max3107_release_port,
2266 + .request_port = max3107_request_port,
2267 + .config_port = max3107_config_port,
2268 + .verify_port = max3107_verify_port,
2269 +};
2270 +
2271 +/* UART driver data */
2272 +static struct uart_driver max3107_uart_driver = {
2273 + .owner = THIS_MODULE,
2274 + .driver_name = "ttyMAX",
2275 + .dev_name = "ttyMAX",
2276 + .major = MAX3107_MAJOR,
2277 + .minor = MAX3107_MINOR,
2278 + .nr = 1,
2279 +};
2280 +
2281 +/* GPIO chip data */
2282 +static struct gpio_chip max3107_gpio_chip = {
2283 + .owner = THIS_MODULE,
2284 + .get_direction = max3107_gpio_get_direction,
2285 + .direction_input = max3107_gpio_direction_in,
2286 + .direction_output = max3107_gpio_direction_out,
2287 + .get = max3107_gpio_get,
2288 + .set = max3107_gpio_set,
2289 + .can_sleep = 1,
2290 + .base = MAX3107_GPIO_BASE,
2291 + .ngpio = MAX3107_GPIO_COUNT,
2292 +};
2293 +
2294 +/* Device probe function */
2295 +static int __devinit max3107_probe(struct spi_device *spi)
2296 +{
2297 + struct max3107_port *s;
2298 + struct max3107_plat *pdata = &max3107_plat_data;
2299 + u16 buf[2]; /* Buffer for SPI transfers */
2300 + int retval;
2301 +
2302 + DBG_TRACE("enter\n");
2303 +
2304 + /* Reset the chip */
2305 + if (gpio_request(MAX3107_RESET_GPIO, "max3107")) {
2306 + printk(KERN_ERR "Requesting RESET GPIO failed\n");
2307 + return -EIO;
2308 + }
2309 + if (gpio_direction_output(MAX3107_RESET_GPIO, 0)) {
2310 + printk(KERN_ERR "Setting RESET GPIO to 0 failed\n");
2311 + gpio_free(MAX3107_RESET_GPIO);
2312 + return -EIO;
2313 + }
2314 + msleep(MAX3107_RESET_DELAY);
2315 + if (gpio_direction_output(MAX3107_RESET_GPIO, 1)) {
2316 + printk(KERN_ERR "Setting RESET GPIO to 1 failed\n");
2317 + gpio_free(MAX3107_RESET_GPIO);
2318 + return -EIO;
2319 + }
2320 + gpio_free(MAX3107_RESET_GPIO);
2321 + msleep(MAX3107_WAKEUP_DELAY);
2322 +
2323 + /* Allocate port structure */
2324 + s = kzalloc(sizeof(*s), GFP_KERNEL);
2325 + if (!s) {
2326 + printk(KERN_ERR "Allocating port structure failed\n");
2327 + return -ENOMEM;
2328 + }
2329 +
2330 + /* Initialize shared data lock */
2331 + spin_lock_init(&s->data_lock);
2332 +
2333 + /* SPI intializations */
2334 + dev_set_drvdata(&spi->dev, s);
2335 + spi->mode = SPI_MODE_0;
2336 + spi->dev.platform_data = pdata;
2337 + spi->bits_per_word = 16;
2338 + s->ext_clk = pdata->ext_clk;
2339 + s->loopback = pdata->loopback;
2340 + spi_setup(spi);
2341 + s->spi = spi;
2342 +
2343 + /* Check REV ID to ensure we are talking to what we expect */
2344 + buf[0] = MAX3107_REVID_REG;
2345 + if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
2346 + dev_err(&s->spi->dev, "SPI transfer for REVID read failed\n");
2347 + return -EIO;
2348 + }
2349 + if ((buf[0] & MAX3107_SPI_RX_DATA_MASK) != MAX3107_REVID1 &&
2350 + (buf[0] & MAX3107_SPI_RX_DATA_MASK) != MAX3107_REVID2) {
2351 + dev_err(&s->spi->dev, "REVID %x does not match\n",
2352 + (buf[0] & MAX3107_SPI_RX_DATA_MASK) );
2353 + return -ENODEV;
2354 + }
2355 +
2356 + /* Disable all interrupts */
2357 + buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG | 0x0000);
2358 + buf[0] |= 0x0000;
2359 +
2360 + /* Configure clock source */
2361 + buf[1] = (MAX3107_WRITE_BIT | MAX3107_CLKSRC_REG);
2362 + if (s->ext_clk) {
2363 + /* External clock */
2364 + buf[1] |= MAX3107_CLKSRC_EXTCLK_BIT;
2365 + }
2366 + /* PLL bypass */
2367 + buf[1] |= MAX3107_CLKSRC_PLLBYP_BIT;
2368 +
2369 + /* Perform SPI transfer */
2370 + if (max3107_rw(s, (u8 *)buf, NULL, 4)) {
2371 + dev_err(&s->spi->dev, "SPI transfer for init failed\n");
2372 + return -EIO;
2373 + }
2374 +
2375 +
2376 + /* Register UART driver */
2377 + retval = uart_register_driver(&max3107_uart_driver);
2378 + if (retval) {
2379 + dev_err(&s->spi->dev, "Registering UART driver failed\n");
2380 + return retval;
2381 + }
2382 +
2383 + /* Initialize UART port data */
2384 + s->port.fifosize = 128;
2385 + s->port.ops = &max3107_ops;
2386 + s->port.line = 0;
2387 + s->port.dev = &spi->dev;
2388 + s->port.uartclk = 9600;
2389 + s->port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
2390 + s->port.irq = s->spi->irq;
2391 + /* Use PORT_MAX3100 since we are at least int the same serie */
2392 + s->port.type = PORT_MAX3100;
2393 +
2394 + /* Add UART port */
2395 + retval = uart_add_one_port(&max3107_uart_driver, &s->port);
2396 + if (retval < 0) {
2397 + dev_err(&s->spi->dev, "Adding UART port failed\n");
2398 + return retval;
2399 + }
2400 +
2401 + /* Initialize GPIO chip data */
2402 + s->chip = max3107_gpio_chip;
2403 + s->chip.label = spi->modalias;
2404 + s->chip.dev = &spi->dev;
2405 +
2406 + /* Add GPIO chip */
2407 + retval = gpiochip_add(&s->chip);
2408 + if (retval) {
2409 + dev_err(&s->spi->dev, "Adding GPIO chip failed\n");
2410 + return retval;
2411 + }
2412 +
2413 + /* Go to suspend mode */
2414 + max3107_hw_susp(s, 1);
2415 +
2416 + return 0;
2417 +}
2418 +
2419 +/* Driver remove function */
2420 +static int __devexit max3107_remove(struct spi_device *spi)
2421 +{
2422 + struct max3107_port *s = dev_get_drvdata(&spi->dev);
2423 +
2424 + DBG_TRACE("enter\n");
2425 +
2426 + /* Remove GPIO chip */
2427 + if (gpiochip_remove(&s->chip))
2428 + dev_warn(&s->spi->dev, "Removing GPIO chip failed\n");
2429 +
2430 + /* Remove port */
2431 + if (uart_remove_one_port(&max3107_uart_driver, &s->port))
2432 + dev_warn(&s->spi->dev, "Removing UART port failed\n");
2433 +
2434 + /* Unregister UART driver */
2435 + uart_unregister_driver(&max3107_uart_driver);
2436 +
2437 + /* Free port structure */
2438 + kfree(s);
2439 +
2440 + return 0;
2441 +}
2442 +
2443 +/* Driver suspend function */
2444 +static int max3107_suspend(struct spi_device *spi, pm_message_t state)
2445 +{
2446 +#ifdef CONFIG_PM
2447 + struct max3107_port *s = dev_get_drvdata(&spi->dev);
2448 +
2449 + DBG_TRACE("enter\n");
2450 +
2451 + /* Suspend UART port */
2452 + uart_suspend_port(&max3107_uart_driver, &s->port);
2453 +
2454 + /* Go to suspend mode */
2455 + max3107_hw_susp(s, 1);
2456 +#endif /* CONFIG_PM */
2457 + return 0;
2458 +}
2459 +
2460 +/* Driver resume function */
2461 +static int max3107_resume(struct spi_device *spi)
2462 +{
2463 +#ifdef CONFIG_PM
2464 + struct max3107_port *s = dev_get_drvdata(&spi->dev);
2465 +
2466 + DBG_TRACE("enter\n");
2467 +
2468 + /* Resume from suspend */
2469 + max3107_hw_susp(s, 0);
2470 +
2471 + /* Resume UART port */
2472 + uart_resume_port(&max3107_uart_driver, &s->port);
2473 +#endif /* CONFIG_PM */
2474 + return 0;
2475 +}
2476 +
2477 +/* Spi driver data */
2478 +static struct spi_driver max3107_driver = {
2479 + .driver = {
2480 + .name = "max3107",
2481 + .bus = &spi_bus_type,
2482 + .owner = THIS_MODULE,
2483 + },
2484 + .probe = max3107_probe,
2485 + .remove = __devexit_p(max3107_remove),
2486 + .suspend = max3107_suspend,
2487 + .resume = max3107_resume,
2488 +};
2489 +
2490 +/* Driver init function */
2491 +static int __init max3107_init(void)
2492 +{
2493 + DBG_TRACE("enter\n");
2494 + return spi_register_driver(&max3107_driver);
2495 +}
2496 +
2497 +/* Driver exit function */
2498 +static void __exit max3107_exit(void)
2499 +{
2500 + DBG_TRACE("enter\n");
2501 + spi_unregister_driver(&max3107_driver);
2502 +}
2503 +
2504 +module_init(max3107_init);
2505 +module_exit(max3107_exit);
2506 +
2507 +MODULE_DESCRIPTION("MAX3107 driver");
2508 +MODULE_AUTHOR("Aavamobile");
2509 +MODULE_ALIAS("max3107-spi-uart");
2510 +MODULE_LICENSE("GPLv2");
2511 Index: linux-2.6.33/drivers/spi/mrst_spi.c
2512 ===================================================================
2513 --- linux-2.6.33.orig/drivers/spi/mrst_spi.c
2514 +++ linux-2.6.33/drivers/spi/mrst_spi.c
2515 @@ -1364,8 +1364,16 @@ static struct pci_driver mrst_spi_driver
2516 .resume = mrst_spi_resume,
2517 };
2518
2519 +/*
2520 + * spi_register_master will call scan board info, and MRST
2521 + * should only have one board_info registered
2522 + */
2523 static int __init mrst_spi_init(void)
2524 {
2525 +/*#ifdef CONFIG_SERIAL_MAX3107*/
2526 +/* spi_register_board_info(mrst_spi_board_info,*/
2527 +/* ARRAY_SIZE(mrst_spi_board_info));*/
2528 +/*#endif*/
2529 return pci_register_driver(&mrst_spi_driver);
2530 }
2531
2532 Index: linux-2.6.33/include/linux/serial_max3107.h
2533 ===================================================================
2534 --- /dev/null
2535 +++ linux-2.6.33/include/linux/serial_max3107.h
2536 @@ -0,0 +1,352 @@
2537 +/*
2538 + * max3107.h - spi uart protocol driver header for Maxim 3107
2539 + *
2540 + * Copyright (C) Aavamobile 2009
2541 + * Based on serial_max3100.h by Christian Pellegrin
2542 + *
2543 + * This program is free software; you can redistribute it and/or modify
2544 + * it under the terms of the GNU General Public License as published by
2545 + * the Free Software Foundation; either version 2 of the License, or
2546 + * (at your option) any later version.
2547 + */
2548 +
2549 +#ifndef _LINUX_SERIAL_MAX3107_H
2550 +#define _LINUX_SERIAL_MAX3107_H
2551 +
2552 +/* Serial definitions */
2553 +#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
2554 +
2555 +/* Serial error status definitions */
2556 +#define MAX3107_PARITY_ERROR 1
2557 +#define MAX3107_FRAME_ERROR 2
2558 +#define MAX3107_OVERRUN_ERROR 4
2559 +#define MAX3107_ALL_ERRORS (MAX3107_PARITY_ERROR | \
2560 + MAX3107_FRAME_ERROR | \
2561 + MAX3107_OVERRUN_ERROR)
2562 +
2563 +
2564 +/* TTY definitions */
2565 +#define MAX3107_MAJOR TTY_MAJOR
2566 +#define MAX3107_MINOR 65
2567 +
2568 +
2569 +/* GPIO definitions */
2570 +#define MAX3107_GPIO_BASE 88
2571 +#define MAX3107_GPIO_COUNT 4
2572 +
2573 +
2574 +/* GPIO connected to chip's reset pin */
2575 +#define MAX3107_RESET_GPIO 87
2576 +
2577 +
2578 +/* Chip reset delay */
2579 +#define MAX3107_RESET_DELAY 10
2580 +
2581 +/* Chip wakeup delay */
2582 +#define MAX3107_WAKEUP_DELAY 50
2583 +
2584 +
2585 +/* Sleep mode definitions */
2586 +#define MAX3107_DISABLE_FORCED_SLEEP 0
2587 +#define MAX3107_ENABLE_FORCED_SLEEP 1
2588 +#define MAX3107_DISABLE_AUTOSLEEP 2
2589 +#define MAX3107_ENABLE_AUTOSLEEP 3
2590 +
2591 +
2592 +/* Definitions for register access with SPI transfers
2593 + *
2594 + * SPI transfer format:
2595 + *
2596 + * Master to slave bits xzzzzzzzyyyyyyyy
2597 + * Slave to master bits aaaaaaaabbbbbbbb
2598 + *
2599 + * where:
2600 + * x = 0 for reads, 1 for writes
2601 + * z = register address
2602 + * y = new register value if write, 0 if read
2603 + * a = unspecified
2604 + * b = register value if read, unspecified if write
2605 + */
2606 +
2607 +/* SPI speed */
2608 +#define MAX3107_SPI_SPEED (3125000 * 2)
2609 +
2610 +/* Write bit */
2611 +#define MAX3107_WRITE_BIT (1 << 15)
2612 +
2613 +/* SPI TX data mask */
2614 +#define MAX3107_SPI_RX_DATA_MASK (0x00ff)
2615 +
2616 +/* SPI RX data mask */
2617 +#define MAX3107_SPI_TX_DATA_MASK (0x00ff)
2618 +
2619 +/* Register access masks */
2620 +#define MAX3107_RHR_REG (0x0000) /* RX FIFO */
2621 +#define MAX3107_THR_REG (0x0000) /* TX FIFO */
2622 +#define MAX3107_IRQEN_REG (0x0100) /* IRQ enable */
2623 +#define MAX3107_IRQSTS_REG (0x0200) /* IRQ status */
2624 +#define MAX3107_LSR_IRQEN_REG (0x0300) /* LSR IRQ enable */
2625 +#define MAX3107_LSR_IRQSTS_REG (0x0400) /* LSR IRQ status */
2626 +#define MAX3107_SPCHR_IRQEN_REG (0x0500) /* Special char IRQ enable */
2627 +#define MAX3107_SPCHR_IRQSTS_REG (0x0600) /* Special char IRQ status */
2628 +#define MAX3107_STS_IRQEN_REG (0x0700) /* Status IRQ enable */
2629 +#define MAX3107_STS_IRQSTS_REG (0x0800) /* Status IRQ status */
2630 +#define MAX3107_MODE1_REG (0x0900) /* MODE1 */
2631 +#define MAX3107_MODE2_REG (0x0a00) /* MODE2 */
2632 +#define MAX3107_LCR_REG (0x0b00) /* LCR */
2633 +#define MAX3107_RXTO_REG (0x0c00) /* RX timeout */
2634 +#define MAX3107_HDPIXDELAY_REG (0x0d00) /* Auto transceiver delays */
2635 +#define MAX3107_IRDA_REG (0x0e00) /* IRDA settings */
2636 +#define MAX3107_FLOWLVL_REG (0x0f00) /* Flow control levels */
2637 +#define MAX3107_FIFOTRIGLVL_REG (0x1000) /* FIFO IRQ trigger levels */
2638 +#define MAX3107_TXFIFOLVL_REG (0x1100) /* TX FIFO level */
2639 +#define MAX3107_RXFIFOLVL_REG (0x1200) /* RX FIFO level */
2640 +#define MAX3107_FLOWCTRL_REG (0x1300) /* Flow control */
2641 +#define MAX3107_XON1_REG (0x1400) /* XON1 character */
2642 +#define MAX3107_XON2_REG (0x1500) /* XON2 character */
2643 +#define MAX3107_XOFF1_REG (0x1600) /* XOFF1 character */
2644 +#define MAX3107_XOFF2_REG (0x1700) /* XOFF2 character */
2645 +#define MAX3107_GPIOCFG_REG (0x1800) /* GPIO config */
2646 +#define MAX3107_GPIODATA_REG (0x1900) /* GPIO data */
2647 +#define MAX3107_PLLCFG_REG (0x1a00) /* PLL config */
2648 +#define MAX3107_BRGCFG_REG (0x1b00) /* Baud rate generator conf */
2649 +#define MAX3107_BRGDIVLSB_REG (0x1c00) /* Baud rate divisor LSB */
2650 +#define MAX3107_BRGDIVMSB_REG (0x1d00) /* Baud rate divisor MSB */
2651 +#define MAX3107_CLKSRC_REG (0x1e00) /* Clock source */
2652 +#define MAX3107_REVID_REG (0x1f00) /* Revision identification */
2653 +
2654 +/* IRQ register bits */
2655 +#define MAX3107_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */
2656 +#define MAX3107_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */
2657 +#define MAX3107_IRQ_STS_BIT (1 << 2) /* Status interrupt */
2658 +#define MAX3107_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */
2659 +#define MAX3107_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */
2660 +#define MAX3107_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */
2661 +#define MAX3107_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */
2662 +#define MAX3107_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */
2663 +
2664 +/* LSR register bits */
2665 +#define MAX3107_LSR_RXTO_BIT (1 << 0) /* RX timeout */
2666 +#define MAX3107_LSR_RXOVR_BIT (1 << 1) /* RX overrun */
2667 +#define MAX3107_LSR_RXPAR_BIT (1 << 2) /* RX parity error */
2668 +#define MAX3107_LSR_FRERR_BIT (1 << 3) /* Frame error */
2669 +#define MAX3107_LSR_RXBRK_BIT (1 << 4) /* RX break */
2670 +#define MAX3107_LSR_RXNOISE_BIT (1 << 5) /* RX noise */
2671 +#define MAX3107_LSR_UNDEF6_BIT (1 << 6) /* Undefined/not used */
2672 +#define MAX3107_LSR_CTS_BIT (1 << 7) /* CTS pin state */
2673 +
2674 +/* Special character register bits */
2675 +#define MAX3107_SPCHR_XON1_BIT (1 << 0) /* XON1 character */
2676 +#define MAX3107_SPCHR_XON2_BIT (1 << 1) /* XON2 character */
2677 +#define MAX3107_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */
2678 +#define MAX3107_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */
2679 +#define MAX3107_SPCHR_BREAK_BIT (1 << 4) /* RX break */
2680 +#define MAX3107_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
2681 +#define MAX3107_SPCHR_UNDEF6_BIT (1 << 6) /* Undefined/not used */
2682 +#define MAX3107_SPCHR_UNDEF7_BIT (1 << 7) /* Undefined/not used */
2683 +
2684 +/* Status register bits */
2685 +#define MAX3107_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */
2686 +#define MAX3107_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */
2687 +#define MAX3107_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */
2688 +#define MAX3107_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */
2689 +#define MAX3107_STS_UNDEF4_BIT (1 << 4) /* Undefined/not used */
2690 +#define MAX3107_STS_CLKREADY_BIT (1 << 5) /* Clock ready */
2691 +#define MAX3107_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */
2692 +#define MAX3107_STS_UNDEF7_BIT (1 << 7) /* Undefined/not used */
2693 +
2694 +/* MODE1 register bits */
2695 +#define MAX3107_MODE1_RXDIS_BIT (1 << 0) /* RX disable */
2696 +#define MAX3107_MODE1_TXDIS_BIT (1 << 1) /* TX disable */
2697 +#define MAX3107_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
2698 +#define MAX3107_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
2699 +#define MAX3107_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */
2700 +#define MAX3107_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */
2701 +#define MAX3107_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */
2702 +#define MAX3107_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */
2703 +
2704 +/* MODE2 register bits */
2705 +#define MAX3107_MODE2_RST_BIT (1 << 0) /* Chip reset */
2706 +#define MAX3107_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */
2707 +#define MAX3107_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */
2708 +#define MAX3107_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */
2709 +#define MAX3107_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */
2710 +#define MAX3107_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */
2711 +#define MAX3107_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
2712 +#define MAX3107_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */
2713 +
2714 +/* LCR register bits */
2715 +#define MAX3107_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
2716 +#define MAX3107_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
2717 + *
2718 + * Word length bits table:
2719 + * 00 -> 5 bit words
2720 + * 01 -> 6 bit words
2721 + * 10 -> 7 bit words
2722 + * 11 -> 8 bit words
2723 + */
2724 +#define MAX3107_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
2725 + *
2726 + * STOP length bit table:
2727 + * 0 -> 1 stop bit
2728 + * 1 -> 1-1.5 stop bits if
2729 + * word length is 5,
2730 + * 2 stop bits otherwise
2731 + */
2732 +#define MAX3107_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
2733 +#define MAX3107_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
2734 +#define MAX3107_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
2735 +#define MAX3107_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
2736 +#define MAX3107_LCR_RTS_BIT (1 << 7) /* RTS pin control */
2737 +#define MAX3107_LCR_WORD_LEN_5 (0x0000)
2738 +#define MAX3107_LCR_WORD_LEN_6 (0x0001)
2739 +#define MAX3107_LCR_WORD_LEN_7 (0x0002)
2740 +#define MAX3107_LCR_WORD_LEN_8 (0x0003)
2741 +
2742 +
2743 +/* IRDA register bits */
2744 +#define MAX3107_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */
2745 +#define MAX3107_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */
2746 +#define MAX3107_IRDA_SHORTIR_BIT (1 << 2) /* Short SIR mode enable */
2747 +#define MAX3107_IRDA_MIR_BIT (1 << 3) /* MIR mode enable */
2748 +#define MAX3107_IRDA_RXINV_BIT (1 << 4) /* RX logic inversion enable */
2749 +#define MAX3107_IRDA_TXINV_BIT (1 << 5) /* TX logic inversion enable */
2750 +#define MAX3107_IRDA_UNDEF6_BIT (1 << 6) /* Undefined/not used */
2751 +#define MAX3107_IRDA_UNDEF7_BIT (1 << 7) /* Undefined/not used */
2752 +
2753 +/* Flow control trigger level register masks */
2754 +#define MAX3107_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */
2755 +#define MAX3107_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */
2756 +#define MAX3107_FLOWLVL_HALT(words) ((words/8) & 0x000f)
2757 +#define MAX3107_FLOWLVL_RES(words) (((words/8) & 0x000f) << 4)
2758 +
2759 +/* FIFO interrupt trigger level register masks */
2760 +#define MAX3107_FIFOTRIGLVL_TX_MASK (0x000f) /* TX FIFO trigger level */
2761 +#define MAX3107_FIFOTRIGLVL_RX_MASK (0x00f0) /* RX FIFO trigger level */
2762 +#define MAX3107_FIFOTRIGLVL_TX(words) ((words/8) & 0x000f)
2763 +#define MAX3107_FIFOTRIGLVL_RX(words) (((words/8) & 0x000f) << 4)
2764 +
2765 +/* Flow control register bits */
2766 +#define MAX3107_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */
2767 +#define MAX3107_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */
2768 +#define MAX3107_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs
2769 + * are used in conjunction with
2770 + * XOFF2 for definition of
2771 + * special character */
2772 +#define MAX3107_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */
2773 +#define MAX3107_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */
2774 +#define MAX3107_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1
2775 + *
2776 + * SWFLOW bits 1 & 0 table:
2777 + * 00 -> no transmitter flow
2778 + * control
2779 + * 01 -> receiver compares
2780 + * XON2 and XOFF2
2781 + * and controls
2782 + * transmitter
2783 + * 10 -> receiver compares
2784 + * XON1 and XOFF1
2785 + * and controls
2786 + * transmitter
2787 + * 11 -> receiver compares
2788 + * XON1, XON2, XOFF1 and
2789 + * XOFF2 and controls
2790 + * transmitter
2791 + */
2792 +#define MAX3107_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */
2793 +#define MAX3107_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3
2794 + *
2795 + * SWFLOW bits 3 & 2 table:
2796 + * 00 -> no received flow
2797 + * control
2798 + * 01 -> transmitter generates
2799 + * XON2 and XOFF2
2800 + * 10 -> transmitter generates
2801 + * XON1 and XOFF1
2802 + * 11 -> transmitter generates
2803 + * XON1, XON2, XOFF1 and
2804 + * XOFF2
2805 + */
2806 +
2807 +/* GPIO configuration register bits */
2808 +#define MAX3107_GPIOCFG_GP0OUT_BIT (1 << 0) /* GPIO 0 output enable */
2809 +#define MAX3107_GPIOCFG_GP1OUT_BIT (1 << 1) /* GPIO 1 output enable */
2810 +#define MAX3107_GPIOCFG_GP2OUT_BIT (1 << 2) /* GPIO 2 output enable */
2811 +#define MAX3107_GPIOCFG_GP3OUT_BIT (1 << 3) /* GPIO 3 output enable */
2812 +#define MAX3107_GPIOCFG_GP0OD_BIT (1 << 4) /* GPIO 0 open-drain enable */
2813 +#define MAX3107_GPIOCFG_GP1OD_BIT (1 << 5) /* GPIO 1 open-drain enable */
2814 +#define MAX3107_GPIOCFG_GP2OD_BIT (1 << 6) /* GPIO 2 open-drain enable */
2815 +#define MAX3107_GPIOCFG_GP3OD_BIT (1 << 7) /* GPIO 3 open-drain enable */
2816 +
2817 +/* GPIO DATA register bits */
2818 +#define MAX3107_GPIODATA_GP0OUT_BIT (1 << 0) /* GPIO 0 output value */
2819 +#define MAX3107_GPIODATA_GP1OUT_BIT (1 << 1) /* GPIO 1 output value */
2820 +#define MAX3107_GPIODATA_GP2OUT_BIT (1 << 2) /* GPIO 2 output value */
2821 +#define MAX3107_GPIODATA_GP3OUT_BIT (1 << 3) /* GPIO 3 output value */
2822 +#define MAX3107_GPIODATA_GP0IN_BIT (1 << 4) /* GPIO 0 input value */
2823 +#define MAX3107_GPIODATA_GP1IN_BIT (1 << 5) /* GPIO 1 input value */
2824 +#define MAX3107_GPIODATA_GP2IN_BIT (1 << 6) /* GPIO 2 input value */
2825 +#define MAX3107_GPIODATA_GP3IN_BIT (1 << 7) /* GPIO 3 input value */
2826 +
2827 +/* PLL configuration register masks */
2828 +#define MAX3107_PLLCFG_PREDIV_MASK (0x003f) /* PLL predivision value */
2829 +#define MAX3107_PLLCFG_PLLFACTOR_MASK (0x00c0) /* PLL multiplication factor */
2830 +
2831 +/* Baud rate generator configuration register masks and bits */
2832 +#define MAX3107_BRGCFG_FRACT_MASK (0x000f) /* Fractional portion of
2833 + * Baud rate generator divisor
2834 + */
2835 +#define MAX3107_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */
2836 +#define MAX3107_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */
2837 +#define MAX3107_BRGCFG_UNDEF6_BIT (1 << 6) /* Undefined/not used */
2838 +#define MAX3107_BRGCFG_UNDEF7_BIT (1 << 7) /* Undefined/not used */
2839 +
2840 +/* Clock source register bits */
2841 +#define MAX3107_CLKSRC_INTOSC_BIT (1 << 0) /* Internal osc enable */
2842 +#define MAX3107_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */
2843 +#define MAX3107_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */
2844 +#define MAX3107_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */
2845 +#define MAX3107_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */
2846 +#define MAX3107_CLKSRC_UNDEF5_BIT (1 << 5) /* Undefined/not used */
2847 +#define MAX3107_CLKSRC_UNDEF6_BIT (1 << 6) /* Undefined/not used */
2848 +#define MAX3107_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */
2849 +
2850 +
2851 +/* HW definitions */
2852 +#define MAX3107_RX_FIFO_SIZE 128
2853 +#define MAX3107_TX_FIFO_SIZE 128
2854 +#define MAX3107_REVID1 0x00a0
2855 +#define MAX3107_REVID2 0x00a1
2856 +
2857 +
2858 +/* Baud rate generator configuration values for external clock */
2859 +#define MAX3107_BRG_B300 (0x0A9400 | 0x05)
2860 +#define MAX3107_BRG_B600 (0x054A00 | 0x03)
2861 +#define MAX3107_BRG_B1200 (0x02A500 | 0x01)
2862 +#define MAX3107_BRG_B2400 (0x015200 | 0x09)
2863 +#define MAX3107_BRG_B4800 (0x00A900 | 0x04)
2864 +#define MAX3107_BRG_B9600 (0x005400 | 0x0A)
2865 +#define MAX3107_BRG_B19200 (0x002A00 | 0x05)
2866 +#define MAX3107_BRG_B38400 (0x001500 | 0x03)
2867 +#define MAX3107_BRG_B57600 (0x000E00 | 0x02)
2868 +#define MAX3107_BRG_B115200 (0x000700 | 0x01)
2869 +#define MAX3107_BRG_B230400 (0x000300 | 0x08)
2870 +#define MAX3107_BRG_B460800 (0x000100 | 0x0c)
2871 +#define MAX3107_BRG_B921600 (0x000100 | 0x1c)
2872 +
2873 +/* Baud rate generator configuration values for internal clock */
2874 +#define MAX3107_BRG_IB300 (0x008000 | 0x00)
2875 +#define MAX3107_BRG_IB600 (0x004000 | 0x00)
2876 +#define MAX3107_BRG_IB1200 (0x002000 | 0x00)
2877 +#define MAX3107_BRG_IB2400 (0x001000 | 0x00)
2878 +#define MAX3107_BRG_IB4800 (0x000800 | 0x00)
2879 +#define MAX3107_BRG_IB9600 (0x000400 | 0x00)
2880 +#define MAX3107_BRG_IB19200 (0x000200 | 0x00)
2881 +#define MAX3107_BRG_IB38400 (0x000100 | 0x00)
2882 +#define MAX3107_BRG_IB57600 (0x000000 | 0x0B)
2883 +#define MAX3107_BRG_IB115200 (0x000000 | 0x05)
2884 +#define MAX3107_BRG_IB230400 (0x000000 | 0x03)
2885 +#define MAX3107_BRG_IB460800 (0x000000 | 0x00)
2886 +#define MAX3107_BRG_IB921600 (0x000000 | 0x00)
2887 +
2888 +#endif /* _LINUX_SERIAL_MAX3107_H */
2889 Index: linux-2.6.33/include/drm/drm_mode.h
2890 ===================================================================
2891 --- linux-2.6.33.orig/include/drm/drm_mode.h
2892 +++ linux-2.6.33/include/drm/drm_mode.h
2893 @@ -160,9 +160,9 @@ struct drm_mode_get_encoder {
2894 #define DRM_MODE_CONNECTOR_DisplayPort 10
2895 #define DRM_MODE_CONNECTOR_HDMIA 11
2896 #define DRM_MODE_CONNECTOR_HDMIB 12
2897 -#define DRM_MODE_CONNECTOR_TV 13
2898 +#define DRM_MODE_CONNECTOR_TV 15
2899 #define DRM_MODE_CONNECTOR_eDP 14
2900 -#define DRM_MODE_CONNECTOR_MIPI 15
2901 +#define DRM_MODE_CONNECTOR_MIPI 13
2902
2903 struct drm_mode_get_connector {
2904
2905 Index: linux-2.6.33/drivers/spi/hh2serial.c
2906 ===================================================================
2907 --- linux-2.6.33.orig/drivers/spi/hh2serial.c
2908 +++ linux-2.6.33/drivers/spi/hh2serial.c
2909 @@ -1,7 +1,17 @@
2910 +/******************************************************************************
2911 +
2912 + Copyright (c) 2009
2913 + Infineon Technologies AG
2914 + Am Campeon 1-12; 81726 Munich, Germany
2915 +
2916 + For licensing information, see the file 'LICENSE' in the root folder of
2917 + this software module.
2918 +
2919 +******************************************************************************/
2920 /*
2921 - * HH2 SPI Serial driver
2922 + * HH2 SPI Serial driver Version 0.2 Beta
2923 *
2924 - * Copyright (C) 2009 Markus Burvall (Markus.Burvall@swedenconnectivity.com)
2925 + * Written by: 2009 Markus Burvall (Markus.Burvall@swedenconnectivity.com)
2926 *
2927 * This program is free software; you can redistribute it and/or modify
2928 * it under the terms of the GNU General Public License as published by
2929 @@ -10,15 +20,10 @@
2930 */
2931
2932
2933 -#define DEBUG 1
2934 -
2935 -//#define HH2_TTY_ECHO
2936 -//#define HH2_TTY_SEND_POLL
2937 -//#define HH2_NO_SPI
2938 #define HH2SERIAL_SPI_16BIT
2939 -//#define HH2SERIAL_ENABLE_DEBUG
2940 #define HH2SERIAL_SPI_POLL
2941
2942 +/*#define HH2SERIAL_SHOW_ERRORS*/
2943
2944 #include <linux/kernel.h>
2945 #include <linux/module.h>
2946 @@ -66,6 +71,7 @@ struct hh2serial_dev {
2947 atomic_t tty_need_read;
2948 atomic_t spi_irq_pending;
2949 int mthread_up;
2950 + int hhRxBufferBytes;
2951 };
2952
2953 static const char driver_name[] = "hh2serial";
2954 @@ -89,13 +95,7 @@ static struct hh2serial_dev priv0;
2955 #define GPSD_DREAD 0xC0 /* bit 7 and 6 */
2956 #define GPSD_CRWRITE 0x00 /* All zero */
2957
2958 -#ifdef HH2SERIAL_SPI_16BIT
2959 -/* HH2 DATA OPERATIONS */
2960 -#define GPSD_16BIT_SRREAD 0x8000 /* bit 7 */
2961 -#define GPSD_16BIT_DWRITE 0x4000 /* bit 6 */
2962 -#define GPSD_16BIT_DREAD 0xC000 /* bit 7 and 6 */
2963 -#define GPSD_16BIT_CRWRITE 0x0000 /* All zero */
2964 -#endif
2965 +
2966
2967 /* HH2 STATUS REGISTER */
2968 #define GPSS_TCNT 0x1F /* bits [4..0] */
2969 @@ -192,9 +192,7 @@ int hh2serial_spi_get_rx_len(struct hh2s
2970 buf_ptr = x.rx_buf;
2971
2972 #ifdef HH2SERIAL_ENABLE_DEBUG
2973 - printk(KERN_INFO "hh2serial RD:%02X, %02X\n",
2974 - *buf_ptr,
2975 - buf_ptr[1]);
2976 + printk(KERN_INFO "hh2serial RD:%02X, %02X\n", *buf_ptr, buf_ptr[1]);
2977 #endif
2978
2979 #ifndef HH2SERIAL_SPI_16BIT
2980 @@ -203,33 +201,56 @@ int hh2serial_spi_get_rx_len(struct hh2s
2981 ret = *buf_ptr & GPSS_TCNT;
2982
2983 /* Check buffer overrun or underrun errors */
2984 +#ifdef HH2SERIAL_SHOW_ERRORS
2985 if (*buf_ptr & GPSS_TERR)
2986 printk(KERN_INFO "hh2serial HH2 transmitter underrun!\n");
2987
2988 if (*buf_ptr & GPSS_RERR)
2989 printk(KERN_INFO "hh2serial HH2 receiver overrun!\n");
2990 -
2991 +#endif
2992 + if (*buf_ptr & GPSS_REMPTY)
2993 + {
2994 + hh2serial->hhRxBufferBytes = HH2SERIAL_SPI_MAX_BYTES;
2995 +#ifdef HH2SERIAL_ENABLE_DEBUG
2996 + printk(KERN_INFO "hh2serial HH2 rx empty!\n");
2997 +#endif
2998 + }
2999 #else
3000 /* 16 bit second byte is status register */
3001 /* Available bytes */
3002 ret = buf_ptr[1] & GPSS_TCNT;
3003
3004 /* Check buffer overrun or underrun errors */
3005 +#ifdef HH2SERIAL_SHOW_ERRORS
3006 if (buf_ptr[1] & GPSS_TERR)
3007 printk(KERN_INFO "hh2serial HH2 transmitter underrun!\n");
3008
3009 if (buf_ptr[1] & GPSS_RERR)
3010 printk(KERN_INFO "hh2serial HH2 receiver overrun!\n");
3011 #endif
3012 +
3013 + if (buf_ptr[1] & GPSS_REMPTY)
3014 + {
3015 + hh2serial->hhRxBufferBytes = HH2SERIAL_SPI_MAX_BYTES;
3016 +#ifdef HH2SERIAL_ENABLE_DEBUG
3017 + printk(KERN_INFO "hh2serial HH2 rx empty!\n");
3018 +#endif
3019 + }
3020 +#endif
3021 /* Take care of errors */
3022 /* FIX ME */
3023
3024 #ifdef HH2SERIAL_ENABLE_DEBUG
3025 - printk(KERN_INFO "hh2serial SR:%02X, rx len %d\n",
3026 - buf_ptr[1],
3027 - ret);
3028 + printk(KERN_INFO "hh2serial SR:%02X, rx len %d\n", buf_ptr[1], ret);
3029 #endif
3030 }
3031 + else
3032 + {
3033 +#ifdef HH2SERIAL_SHOW_ERRORS
3034 +printk(KERN_INFO "hh2serial Rd_status, spi_sync failed: %d\n",ret);
3035 +#endif
3036 + ret = 0;
3037 + }
3038
3039 kfree(local_buf);
3040 return ret;
3041 @@ -332,11 +353,22 @@ int hh2serial_spi_read(struct hh2serial_
3042 available_rd = *buf_ptr & GPSS_TCNT;
3043
3044 /* Check buffer overrun or underrun errors */
3045 +#ifdef HH2SERIAL_SHOW_ERRORS
3046 if (*buf_ptr & GPSS_TERR)
3047 printk(KERN_INFO "hh2serial HH2 transmitter underrun!\n");
3048
3049 if (*buf_ptr & GPSS_RERR)
3050 printk(KERN_INFO "hh2serial HH2 receiver overrun!\n");
3051 +#endif
3052 +
3053 + if (*buf_ptr & GPSS_REMPTY)
3054 + {
3055 + hh2serial->hhRxBufferBytes = HH2SERIAL_SPI_MAX_BYTES;
3056 +#ifdef HH2SERIAL_ENABLE_DEBUG
3057 + printk(KERN_INFO "hh2serial HH2 rx empty!\n");
3058 +#endif
3059 +
3060 + }
3061 #else
3062 /* 16 bit second byte is status register */
3063 /* Every other byte is status register */
3064 @@ -345,6 +377,7 @@ int hh2serial_spi_read(struct hh2serial_
3065 available_rd = (buf_ptr[len_inc_hdr-1] & GPSS_TCNT) - 1;
3066
3067 /* Check buffer overrun or underrun errors */
3068 +#ifdef HH2SERIAL_SHOW_ERRORS
3069 if (buf_ptr[len_inc_hdr-1] & GPSS_TERR)
3070 printk(KERN_INFO "hh2serial HH2 transmitter underrun!\n");
3071
3072 @@ -352,6 +385,14 @@ int hh2serial_spi_read(struct hh2serial_
3073 printk(KERN_INFO "hh2serial HH2 receiver overrun!\n");
3074 #endif
3075
3076 + if (buf_ptr[len_inc_hdr-1] & GPSS_REMPTY)
3077 + {
3078 + hh2serial->hhRxBufferBytes = HH2SERIAL_SPI_MAX_BYTES;
3079 +#ifdef HH2SERIAL_ENABLE_DEBUG
3080 + printk(KERN_INFO "hh2serial HH2 rx empty!\n");
3081 +#endif
3082 + }
3083 +#endif
3084
3085 #ifdef HH2SERIAL_ENABLE_DEBUG
3086 printk(KERN_INFO "hh2serial_spi_read len inc hdr wr:%d, avail rd %d, cs_change:%d\n",
3087 @@ -388,6 +429,13 @@ int hh2serial_spi_read(struct hh2serial_
3088 #endif
3089
3090 }
3091 + else
3092 + {
3093 +#ifdef HH2SERIAL_SHOW_ERRORS
3094 +printk(KERN_INFO "hh2serial spi_read, spi_sync failed: %d\n",status);
3095 +#endif
3096 +
3097 + }
3098
3099 kfree(local_buf);
3100 return status;
3101 @@ -435,8 +483,8 @@ int hh2serial_spi_write(struct hh2serial
3102 x.len = len_inc_hdr;
3103 spi_message_add_tail(&x, &message);
3104
3105 - /* Allocate and make room for 1 byte header */
3106 - local_buf = kzalloc(HH2SERIAL_BUFSIZE+1, GFP_KERNEL);
3107 + /* Allocate and make room for 1 byte header(RX and TX) */
3108 + local_buf = kzalloc(HH2SERIAL_BUFSIZE+2, GFP_KERNEL);
3109 if (!local_buf)
3110 return -ENOMEM;
3111
3112 @@ -453,7 +501,6 @@ int hh2serial_spi_write(struct hh2serial
3113 int byte_index = 2;
3114 while (byte_index < len_inc_hdr)
3115 {
3116 -
3117 local_buf[byte_index] = txbuf[byte_index];
3118 local_buf[byte_index+1] = GPSD_DWRITE;
3119 byte_index = byte_index + 2;
3120 @@ -495,24 +542,55 @@ int hh2serial_spi_write(struct hh2serial
3121 available_rd = *buf_ptr & GPSS_TCNT;
3122
3123 /* Check buffer overrun or underrun errors */
3124 +#ifdef HH2SERIAL_SHOW_ERRORS
3125 if (*buf_ptr & GPSS_TERR)
3126 printk(KERN_INFO "hh2serial HH2 transmitter underrun!\n");
3127
3128 if (*buf_ptr & GPSS_RERR)
3129 printk(KERN_INFO "hh2serial HH2 receiver overrun!\n");
3130 +#endif
3131 + if (*buf_ptr & GPSS_REMPTY)
3132 + {
3133 + /* Buffer was empty but len bytes has been written after that */
3134 + hh2serial->hhRxBufferBytes = HH2SERIAL_SPI_MAX_BYTES-len;
3135 +#ifdef HH2SERIAL_ENABLE_DEBUG
3136 + printk(KERN_INFO "hh2serial HH2 rx empty!\n");
3137 +#endif
3138 + }
3139 + else
3140 + {
3141 + hh2serial->hhRxBufferBytes -= len;
3142 + }
3143 #else
3144 + /* FIXME_Only last status is interesting or? */
3145 + /* Might have to check every status register to se if empty */
3146 /* 16 bit second byte is status register */
3147 /* Available bytes */
3148 - available_rd = buf_ptr[1] & GPSS_TCNT;
3149 + available_rd = buf_ptr[len_inc_hdr-1] & GPSS_TCNT;
3150
3151 /* Check buffer overrun or underrun errors */
3152 - if (buf_ptr[1] & GPSS_TERR)
3153 +#ifdef HH2SERIAL_SHOW_ERRORS
3154 + if (buf_ptr[len_inc_hdr-1] & GPSS_TERR)
3155 printk(KERN_INFO "hh2serial HH2 transmitter underrun!\n");
3156
3157 - if (buf_ptr[1] & GPSS_RERR)
3158 + if (buf_ptr[len_inc_hdr-1] & GPSS_RERR)
3159 printk(KERN_INFO "hh2serial HH2 receiver overrun!\n");
3160 #endif
3161
3162 + if (buf_ptr[len_inc_hdr-1] & GPSS_REMPTY)
3163 + {
3164 + /* Buffer was empty but one byte has been written after that */
3165 + hh2serial->hhRxBufferBytes = HH2SERIAL_SPI_MAX_BYTES-1;
3166 +#ifdef HH2SERIAL_ENABLE_DEBUG
3167 + printk(KERN_INFO "hh2serial HH2 rx empty!\n");
3168 +#endif
3169 + }
3170 + else
3171 + {
3172 + /* Only 8 bit of every 16 is data */
3173 + hh2serial->hhRxBufferBytes -= (len/2);
3174 + }
3175 +#endif
3176
3177 #ifdef HH2SERIAL_ENABLE_DEBUG
3178 printk(KERN_INFO "hh2serial_spi_write:%02X, %02X\n",
3179 @@ -526,9 +604,14 @@ int hh2serial_spi_write(struct hh2serial
3180
3181 *spiAvailData = available_rd;
3182
3183 -
3184 }
3185 + else
3186 + {
3187 +#ifdef HH2SERIAL_SHOW_ERRORS
3188 +printk(KERN_INFO "hh2serial spi_write, spi_sync failed: %d\n",status);
3189 +#endif
3190
3191 + }
3192
3193
3194 kfree(local_buf);
3195 @@ -616,61 +699,77 @@ static inline void hh2serial_write_circ_
3196 #ifdef HH2SERIAL_ENABLE_DEBUG
3197 printk(KERN_INFO "Bytes in circ buffer: %d\n", left);
3198 #endif
3199 - while (left) {
3200 - /* MrB Change below to 1 and word length to 16 to write 16 bit
3201 - word by word */
3202 -#ifndef HH2SERIAL_SPI_16BIT
3203 - len = (left >= HH2SERIAL_SPI_MAX_BYTES) ? HH2SERIAL_SPI_MAX_BYTES : left;
3204 -#else
3205 - len = (left >= HH2SERIAL_SPI_MAX_BYTES) ? HH2SERIAL_SPI_MAX_BYTES : left;
3206 -#endif
3207 -
3208 - memset(obuf, 0, len);
3209 - memset(ibuf, 0, len);
3210 - for (i = 0; i < len; i++) {
3211 + while (left || (rxlen > 0)) {
3212
3213 - obuf[i] = (u8)xmit->buf[xmit->tail];
3214 -
3215 - xmit->tail = (xmit->tail + 1) &
3216 - (UART_XMIT_SIZE - 1);
3217 - }
3218 -#ifndef HH2SERIAL_SPI_16BIT
3219 + if (left)
3220 + {
3221 + /* FIXME len = MIN(left , hhRxBufferBytes)
3222 + if len 0 is then only read status register and read */
3223 +
3224 + len = (left >= priv->hhRxBufferBytes) ? priv->hhRxBufferBytes : left;
3225 +
3226 +
3227 + if (len > 0)
3228 + {
3229 + memset(obuf, 0, len);
3230 + memset(ibuf, 0, len);
3231 + for (i = 0; i < len; i++) {
3232 +
3233 + obuf[i] = (u8)xmit->buf[xmit->tail];
3234 +
3235 + xmit->tail = (xmit->tail + 1) &
3236 + (UART_XMIT_SIZE - 1);
3237 + }
3238 + #ifndef HH2SERIAL_SPI_16BIT
3239 +
3240 + /* FIXME check status */
3241 + hh2serial_spi_write(priv, (u8 *)obuf,
3242 + &rxlen, len);
3243 +
3244 + #else
3245 + /* len * 2 since 16 bits instead of 8 bits */
3246 + /* FIXME check status */
3247 + hh2serial_spi_write(priv, (u8 *)obuf,
3248 + &rxlen, len*2);
3249 +
3250 + #endif
3251 + left -= len;
3252 + }
3253 + else /* Read rx len */
3254 + {
3255 + #ifdef HH2SERIAL_SHOW_ERRORS
3256 + printk(KERN_INFO "hh2serial wr buf2spi, rxBuf full?\n");
3257 + #endif
3258 + rxlen = hh2serial_spi_get_rx_len(priv);
3259
3260 - hh2serial_spi_write(priv, (u8 *)obuf,
3261 - &rxlen, len);
3262
3263 -#else
3264 - /* len * 2 since 16 bits instead of 8 bits */
3265 - hh2serial_spi_write(priv, (u8 *)obuf,
3266 - &rxlen, len*2);
3267 -
3268 -#endif
3269 - left -= len;
3270 - }
3271 + }
3272 + }
3273 #ifdef HH2SERIAL_ENABLE_DEBUG
3274 printk(KERN_INFO "hh2serial: Bytes avail to read: %d\n", rxlen);
3275 #endif
3276 /* Read if available bytes */
3277 /* FIXME: Could add a maximum read loop here */
3278 - while (rxlen > 0)
3279 - {
3280 -
3281 - len = rxlen;
3282 -#ifndef HH2SERIAL_SPI_16BIT
3283 - hh2serial_spi_read(priv, (u8 *)ibuf, &rxlen, len);
3284 -#else
3285 - hh2serial_spi_read(priv, (u8 *)ibuf, &rxlen, len*2);
3286 -#endif
3287 -
3288 - for (i = 0, j = 0; i < len; i++) {
3289 - valid_str[j++] = (u8)(ibuf[i]);
3290 - }
3291 + if (rxlen > 0)
3292 + {
3293
3294 - if (j)
3295 - hh2serial_write2tty(priv, valid_str, j);
3296 -
3297 - priv->port.icount.tx += len;
3298 - }
3299 + len = rxlen;
3300 + #ifndef HH2SERIAL_SPI_16BIT
3301 + hh2serial_spi_read(priv, (u8 *)ibuf, &rxlen, len);
3302 + #else
3303 + hh2serial_spi_read(priv, (u8 *)ibuf, &rxlen, len*2);
3304 + #endif
3305 +
3306 + for (i = 0, j = 0; i < len; i++) {
3307 + valid_str[j++] = (u8)(ibuf[i]);
3308 + }
3309 +
3310 + if (j)
3311 + hh2serial_write2tty(priv, valid_str, j);
3312 +
3313 + priv->port.icount.tx += len;
3314 + }
3315 + }
3316 }
3317 }
3318 #endif
3319 @@ -793,7 +892,7 @@ static int hh2serial_main_thread(void *_
3320 /* Read from tty send to spi */
3321 #ifdef HH2SERIAL_ENABLE_DEBUG
3322 printk(KERN_INFO "hh2serial: Read from tty send to spi\n");
3323 -#endif
3324 +#endif
3325 /* Read from tty send to spi */
3326 /* Receive data from spi send to UART */
3327
3328 @@ -1153,11 +1252,13 @@ static int hh2serial_startup(struct uart
3329 struct hh2serial_dev *priv = container_of(port, struct hh2serial_dev, port);
3330 FUNC_ENTER();
3331
3332 + /* Initialize RxBuffer to 0 */
3333 + priv->hhRxBufferBytes = 0;
3334 #ifdef HH2SERIAL_SPI_POLL
3335 priv->poll_thread = kthread_run(hh2serial_poll_thread,
3336 priv, "hh2serial_poll");
3337 if (IS_ERR(priv->poll_thread)) {
3338 - printk(KERN_INFO "hh2serial Failed to start poll thread: %ld",
3339 + printk(KERN_INFO "hh2serial Failed to start poll thread: %ld",
3340 PTR_ERR(priv->poll_thread));
3341 }
3342 #endif
Mirror of git://git.openembedded.org/openembedded-core-contrib