1 From 3dab0318bccd31f394f4a3a8561d3f062e7f6dd7 Mon Sep 17 00:00:00 2001
2 From: Sasha Levin <sashal@kernel.org>
3 Date: Tue, 1 Sep 2020 14:49:54 +0200
4 Subject: PCI: qcom: Make sure PCIe is reset before init for rev 2.1.0
6 From: Ansuel Smith <ansuelsmth@gmail.com>
8 [ Upstream commit d3d4d028afb785e52c55024d779089654f8302e7 ]
10 Qsdk U-Boot can incorrectly leave the PCIe interface in an undefined
11 state if bootm command is used instead of bootipq. This is caused by the
12 not deinit of PCIe when bootm is called. Reset the PCIe before init
13 anyway to fix this U-Boot bug.
15 Link: https://lore.kernel.org/r/20200901124955.137-1-ansuelsmth@gmail.com
16 Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
17 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
18 Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
19 Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
20 Cc: stable@vger.kernel.org # v4.19+
21 Signed-off-by: Sasha Levin <sashal@kernel.org>
23 drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
24 1 file changed, 13 insertions(+)
26 diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
27 index 374db5d59cf87..14196c0287a24 100644
28 --- a/drivers/pci/controller/dwc/pcie-qcom.c
29 +++ b/drivers/pci/controller/dwc/pcie-qcom.c
30 @@ -303,6 +303,9 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
31 clk_disable_unprepare(res->core_clk);
32 clk_disable_unprepare(res->aux_clk);
33 clk_disable_unprepare(res->ref_clk);
35 + writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL);
37 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
40 @@ -315,6 +318,16 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
44 + /* reset the PCIe interface as uboot can leave it undefined state */
45 + reset_control_assert(res->pci_reset);
46 + reset_control_assert(res->axi_reset);
47 + reset_control_assert(res->ahb_reset);
48 + reset_control_assert(res->por_reset);
49 + reset_control_assert(res->ext_reset);
50 + reset_control_assert(res->phy_reset);
52 + writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL);
54 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
56 dev_err(dev, "cannot enable regulators\n");