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1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * SC7180 SoC device tree source
4 *
5 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
6 */
7
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/phy/phy-qcom-qusb2.h>
15 #include <dt-bindings/power/qcom-aoss-qmp.h>
16 #include <dt-bindings/power/qcom-rpmpd.h>
17 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
18 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
19 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
20 #include <dt-bindings/thermal/thermal.h>
21
22 / {
23 interrupt-parent = <&intc>;
24
25 #address-cells = <2>;
26 #size-cells = <2>;
27
28 chosen { };
29
30 aliases {
31 i2c0 = &i2c0;
32 i2c1 = &i2c1;
33 i2c2 = &i2c2;
34 i2c3 = &i2c3;
35 i2c4 = &i2c4;
36 i2c5 = &i2c5;
37 i2c6 = &i2c6;
38 i2c7 = &i2c7;
39 i2c8 = &i2c8;
40 i2c9 = &i2c9;
41 i2c10 = &i2c10;
42 i2c11 = &i2c11;
43 spi0 = &spi0;
44 spi1 = &spi1;
45 spi3 = &spi3;
46 spi5 = &spi5;
47 spi6 = &spi6;
48 spi8 = &spi8;
49 spi10 = &spi10;
50 spi11 = &spi11;
51 };
52
53 clocks {
54 xo_board: xo-board {
55 compatible = "fixed-clock";
56 clock-frequency = <38400000>;
57 #clock-cells = <0>;
58 };
59
60 sleep_clk: sleep-clk {
61 compatible = "fixed-clock";
62 clock-frequency = <32764>;
63 #clock-cells = <0>;
64 };
65 };
66
67 reserved_memory: reserved-memory {
68 #address-cells = <2>;
69 #size-cells = <2>;
70 ranges;
71
72 aop_cmd_db_mem: memory@80820000 {
73 reg = <0x0 0x80820000 0x0 0x20000>;
74 compatible = "qcom,cmd-db";
75 };
76
77 smem_mem: memory@80900000 {
78 reg = <0x0 0x80900000 0x0 0x200000>;
79 no-map;
80 };
81 };
82
83 cpus {
84 #address-cells = <2>;
85 #size-cells = <0>;
86
87 CPU0: cpu@0 {
88 device_type = "cpu";
89 compatible = "arm,armv8";
90 reg = <0x0 0x0>;
91 enable-method = "psci";
92 capacity-dmips-mhz = <1024>;
93 dynamic-power-coefficient = <100>;
94 next-level-cache = <&L2_0>;
95 #cooling-cells = <2>;
96 qcom,freq-domain = <&cpufreq_hw 0>;
97 L2_0: l2-cache {
98 compatible = "cache";
99 next-level-cache = <&L3_0>;
100 L3_0: l3-cache {
101 compatible = "cache";
102 };
103 };
104 };
105
106 CPU1: cpu@100 {
107 device_type = "cpu";
108 compatible = "arm,armv8";
109 reg = <0x0 0x100>;
110 enable-method = "psci";
111 capacity-dmips-mhz = <1024>;
112 dynamic-power-coefficient = <100>;
113 next-level-cache = <&L2_100>;
114 #cooling-cells = <2>;
115 qcom,freq-domain = <&cpufreq_hw 0>;
116 L2_100: l2-cache {
117 compatible = "cache";
118 next-level-cache = <&L3_0>;
119 };
120 };
121
122 CPU2: cpu@200 {
123 device_type = "cpu";
124 compatible = "arm,armv8";
125 reg = <0x0 0x200>;
126 enable-method = "psci";
127 capacity-dmips-mhz = <1024>;
128 dynamic-power-coefficient = <100>;
129 next-level-cache = <&L2_200>;
130 #cooling-cells = <2>;
131 qcom,freq-domain = <&cpufreq_hw 0>;
132 L2_200: l2-cache {
133 compatible = "cache";
134 next-level-cache = <&L3_0>;
135 };
136 };
137
138 CPU3: cpu@300 {
139 device_type = "cpu";
140 compatible = "arm,armv8";
141 reg = <0x0 0x300>;
142 enable-method = "psci";
143 capacity-dmips-mhz = <1024>;
144 dynamic-power-coefficient = <100>;
145 next-level-cache = <&L2_300>;
146 #cooling-cells = <2>;
147 qcom,freq-domain = <&cpufreq_hw 0>;
148 L2_300: l2-cache {
149 compatible = "cache";
150 next-level-cache = <&L3_0>;
151 };
152 };
153
154 CPU4: cpu@400 {
155 device_type = "cpu";
156 compatible = "arm,armv8";
157 reg = <0x0 0x400>;
158 enable-method = "psci";
159 capacity-dmips-mhz = <1024>;
160 dynamic-power-coefficient = <100>;
161 next-level-cache = <&L2_400>;
162 #cooling-cells = <2>;
163 qcom,freq-domain = <&cpufreq_hw 0>;
164 L2_400: l2-cache {
165 compatible = "cache";
166 next-level-cache = <&L3_0>;
167 };
168 };
169
170 CPU5: cpu@500 {
171 device_type = "cpu";
172 compatible = "arm,armv8";
173 reg = <0x0 0x500>;
174 enable-method = "psci";
175 capacity-dmips-mhz = <1024>;
176 dynamic-power-coefficient = <100>;
177 next-level-cache = <&L2_500>;
178 #cooling-cells = <2>;
179 qcom,freq-domain = <&cpufreq_hw 0>;
180 L2_500: l2-cache {
181 compatible = "cache";
182 next-level-cache = <&L3_0>;
183 };
184 };
185
186 CPU6: cpu@600 {
187 device_type = "cpu";
188 compatible = "arm,armv8";
189 reg = <0x0 0x600>;
190 enable-method = "psci";
191 capacity-dmips-mhz = <1740>;
192 dynamic-power-coefficient = <405>;
193 next-level-cache = <&L2_600>;
194 #cooling-cells = <2>;
195 qcom,freq-domain = <&cpufreq_hw 1>;
196 L2_600: l2-cache {
197 compatible = "cache";
198 next-level-cache = <&L3_0>;
199 };
200 };
201
202 CPU7: cpu@700 {
203 device_type = "cpu";
204 compatible = "arm,armv8";
205 reg = <0x0 0x700>;
206 enable-method = "psci";
207 capacity-dmips-mhz = <1740>;
208 dynamic-power-coefficient = <405>;
209 next-level-cache = <&L2_700>;
210 #cooling-cells = <2>;
211 qcom,freq-domain = <&cpufreq_hw 1>;
212 L2_700: l2-cache {
213 compatible = "cache";
214 next-level-cache = <&L3_0>;
215 };
216 };
217
218 cpu-map {
219 cluster0 {
220 core0 {
221 cpu = <&CPU0>;
222 };
223
224 core1 {
225 cpu = <&CPU1>;
226 };
227
228 core2 {
229 cpu = <&CPU2>;
230 };
231
232 core3 {
233 cpu = <&CPU3>;
234 };
235
236 core4 {
237 cpu = <&CPU4>;
238 };
239
240 core5 {
241 cpu = <&CPU5>;
242 };
243
244 core6 {
245 cpu = <&CPU6>;
246 };
247
248 core7 {
249 cpu = <&CPU7>;
250 };
251 };
252 };
253 };
254
255 memory@80000000 {
256 device_type = "memory";
257 /* We expect the bootloader to fill in the size */
258 reg = <0 0x80000000 0 0>;
259 };
260
261 pmu {
262 compatible = "arm,armv8-pmuv3";
263 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
264 };
265
266 firmware {
267 scm {
268 compatible = "qcom,scm-sc7180", "qcom,scm";
269 };
270 };
271
272 tcsr_mutex: hwlock {
273 compatible = "qcom,tcsr-mutex";
274 syscon = <&tcsr_mutex_regs 0 0x1000>;
275 #hwlock-cells = <1>;
276 };
277
278 smem {
279 compatible = "qcom,smem";
280 memory-region = <&smem_mem>;
281 hwlocks = <&tcsr_mutex 3>;
282 };
283
284 smp2p-cdsp {
285 compatible = "qcom,smp2p";
286 qcom,smem = <94>, <432>;
287
288 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
289
290 mboxes = <&apss_shared 6>;
291
292 qcom,local-pid = <0>;
293 qcom,remote-pid = <5>;
294
295 cdsp_smp2p_out: master-kernel {
296 qcom,entry-name = "master-kernel";
297 #qcom,smem-state-cells = <1>;
298 };
299
300 cdsp_smp2p_in: slave-kernel {
301 qcom,entry-name = "slave-kernel";
302
303 interrupt-controller;
304 #interrupt-cells = <2>;
305 };
306 };
307
308 smp2p-lpass {
309 compatible = "qcom,smp2p";
310 qcom,smem = <443>, <429>;
311
312 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
313
314 mboxes = <&apss_shared 10>;
315
316 qcom,local-pid = <0>;
317 qcom,remote-pid = <2>;
318
319 adsp_smp2p_out: master-kernel {
320 qcom,entry-name = "master-kernel";
321 #qcom,smem-state-cells = <1>;
322 };
323
324 adsp_smp2p_in: slave-kernel {
325 qcom,entry-name = "slave-kernel";
326
327 interrupt-controller;
328 #interrupt-cells = <2>;
329 };
330 };
331
332 smp2p-mpss {
333 compatible = "qcom,smp2p";
334 qcom,smem = <435>, <428>;
335 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
336 mboxes = <&apss_shared 14>;
337 qcom,local-pid = <0>;
338 qcom,remote-pid = <1>;
339
340 modem_smp2p_out: master-kernel {
341 qcom,entry-name = "master-kernel";
342 #qcom,smem-state-cells = <1>;
343 };
344
345 modem_smp2p_in: slave-kernel {
346 qcom,entry-name = "slave-kernel";
347 interrupt-controller;
348 #interrupt-cells = <2>;
349 };
350 };
351
352 psci {
353 compatible = "arm,psci-1.0";
354 method = "smc";
355 };
356
357 soc: soc {
358 #address-cells = <2>;
359 #size-cells = <2>;
360 ranges = <0 0 0 0 0x10 0>;
361 dma-ranges = <0 0 0 0 0x10 0>;
362 compatible = "simple-bus";
363
364 gcc: clock-controller@100000 {
365 compatible = "qcom,gcc-sc7180";
366 reg = <0 0x00100000 0 0x1f0000>;
367 clocks = <&rpmhcc RPMH_CXO_CLK>,
368 <&rpmhcc RPMH_CXO_CLK_A>,
369 <&sleep_clk>;
370 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
371 #clock-cells = <1>;
372 #reset-cells = <1>;
373 #power-domain-cells = <1>;
374 };
375
376 qfprom@784000 {
377 compatible = "qcom,qfprom";
378 reg = <0 0x00784000 0 0x8ff>;
379 #address-cells = <1>;
380 #size-cells = <1>;
381
382 qusb2p_hstx_trim: hstx-trim-primary@25b {
383 reg = <0x25b 0x1>;
384 bits = <1 3>;
385 };
386 };
387
388 sdhc_1: sdhci@7c4000 {
389 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
390 reg = <0 0x7c4000 0 0x1000>,
391 <0 0x07c5000 0 0x1000>;
392 reg-names = "hc_mem", "cqhci_mem";
393
394 iommus = <&apps_smmu 0x60 0x0>;
395 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
396 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
397 interrupt-names = "hc_irq", "pwr_irq";
398
399 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
400 <&gcc GCC_SDCC1_AHB_CLK>;
401 clock-names = "core", "iface";
402
403 bus-width = <8>;
404 non-removable;
405 supports-cqe;
406
407 mmc-ddr-1_8v;
408 mmc-hs200-1_8v;
409 mmc-hs400-1_8v;
410 mmc-hs400-enhanced-strobe;
411
412 status = "disabled";
413 };
414
415 qupv3_id_0: geniqup@8c0000 {
416 compatible = "qcom,geni-se-qup";
417 reg = <0 0x008c0000 0 0x6000>;
418 clock-names = "m-ahb", "s-ahb";
419 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
420 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
421 #address-cells = <2>;
422 #size-cells = <2>;
423 ranges;
424 iommus = <&apps_smmu 0x43 0x0>;
425 status = "disabled";
426
427 i2c0: i2c@880000 {
428 compatible = "qcom,geni-i2c";
429 reg = <0 0x00880000 0 0x4000>;
430 clock-names = "se";
431 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
432 pinctrl-names = "default";
433 pinctrl-0 = <&qup_i2c0_default>;
434 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
435 #address-cells = <1>;
436 #size-cells = <0>;
437 status = "disabled";
438 };
439
440 spi0: spi@880000 {
441 compatible = "qcom,geni-spi";
442 reg = <0 0x00880000 0 0x4000>;
443 clock-names = "se";
444 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
445 pinctrl-names = "default";
446 pinctrl-0 = <&qup_spi0_default>;
447 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
448 #address-cells = <1>;
449 #size-cells = <0>;
450 status = "disabled";
451 };
452
453 uart0: serial@880000 {
454 compatible = "qcom,geni-uart";
455 reg = <0 0x00880000 0 0x4000>;
456 clock-names = "se";
457 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
458 pinctrl-names = "default";
459 pinctrl-0 = <&qup_uart0_default>;
460 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
461 status = "disabled";
462 };
463
464 i2c1: i2c@884000 {
465 compatible = "qcom,geni-i2c";
466 reg = <0 0x00884000 0 0x4000>;
467 clock-names = "se";
468 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
469 pinctrl-names = "default";
470 pinctrl-0 = <&qup_i2c1_default>;
471 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
472 #address-cells = <1>;
473 #size-cells = <0>;
474 status = "disabled";
475 };
476
477 spi1: spi@884000 {
478 compatible = "qcom,geni-spi";
479 reg = <0 0x00884000 0 0x4000>;
480 clock-names = "se";
481 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
482 pinctrl-names = "default";
483 pinctrl-0 = <&qup_spi1_default>;
484 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
485 #address-cells = <1>;
486 #size-cells = <0>;
487 status = "disabled";
488 };
489
490 uart1: serial@884000 {
491 compatible = "qcom,geni-uart";
492 reg = <0 0x00884000 0 0x4000>;
493 clock-names = "se";
494 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
495 pinctrl-names = "default";
496 pinctrl-0 = <&qup_uart1_default>;
497 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
498 status = "disabled";
499 };
500
501 i2c2: i2c@888000 {
502 compatible = "qcom,geni-i2c";
503 reg = <0 0x00888000 0 0x4000>;
504 clock-names = "se";
505 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
506 pinctrl-names = "default";
507 pinctrl-0 = <&qup_i2c2_default>;
508 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
509 #address-cells = <1>;
510 #size-cells = <0>;
511 status = "disabled";
512 };
513
514 uart2: serial@888000 {
515 compatible = "qcom,geni-uart";
516 reg = <0 0x00888000 0 0x4000>;
517 clock-names = "se";
518 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
519 pinctrl-names = "default";
520 pinctrl-0 = <&qup_uart2_default>;
521 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
522 status = "disabled";
523 };
524
525 i2c3: i2c@88c000 {
526 compatible = "qcom,geni-i2c";
527 reg = <0 0x0088c000 0 0x4000>;
528 clock-names = "se";
529 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
530 pinctrl-names = "default";
531 pinctrl-0 = <&qup_i2c3_default>;
532 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
533 #address-cells = <1>;
534 #size-cells = <0>;
535 status = "disabled";
536 };
537
538 spi3: spi@88c000 {
539 compatible = "qcom,geni-spi";
540 reg = <0 0x0088c000 0 0x4000>;
541 clock-names = "se";
542 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
543 pinctrl-names = "default";
544 pinctrl-0 = <&qup_spi3_default>;
545 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
546 #address-cells = <1>;
547 #size-cells = <0>;
548 status = "disabled";
549 };
550
551 uart3: serial@88c000 {
552 compatible = "qcom,geni-uart";
553 reg = <0 0x0088c000 0 0x4000>;
554 clock-names = "se";
555 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
556 pinctrl-names = "default";
557 pinctrl-0 = <&qup_uart3_default>;
558 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
559 status = "disabled";
560 };
561
562 i2c4: i2c@890000 {
563 compatible = "qcom,geni-i2c";
564 reg = <0 0x00890000 0 0x4000>;
565 clock-names = "se";
566 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
567 pinctrl-names = "default";
568 pinctrl-0 = <&qup_i2c4_default>;
569 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
570 #address-cells = <1>;
571 #size-cells = <0>;
572 status = "disabled";
573 };
574
575 uart4: serial@890000 {
576 compatible = "qcom,geni-uart";
577 reg = <0 0x00890000 0 0x4000>;
578 clock-names = "se";
579 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
580 pinctrl-names = "default";
581 pinctrl-0 = <&qup_uart4_default>;
582 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
583 status = "disabled";
584 };
585
586 i2c5: i2c@894000 {
587 compatible = "qcom,geni-i2c";
588 reg = <0 0x00894000 0 0x4000>;
589 clock-names = "se";
590 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
591 pinctrl-names = "default";
592 pinctrl-0 = <&qup_i2c5_default>;
593 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
594 #address-cells = <1>;
595 #size-cells = <0>;
596 status = "disabled";
597 };
598
599 spi5: spi@894000 {
600 compatible = "qcom,geni-spi";
601 reg = <0 0x00894000 0 0x4000>;
602 clock-names = "se";
603 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
604 pinctrl-names = "default";
605 pinctrl-0 = <&qup_spi5_default>;
606 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
607 #address-cells = <1>;
608 #size-cells = <0>;
609 status = "disabled";
610 };
611
612 uart5: serial@894000 {
613 compatible = "qcom,geni-uart";
614 reg = <0 0x00894000 0 0x4000>;
615 clock-names = "se";
616 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
617 pinctrl-names = "default";
618 pinctrl-0 = <&qup_uart5_default>;
619 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
620 status = "disabled";
621 };
622 };
623
624 qupv3_id_1: geniqup@ac0000 {
625 compatible = "qcom,geni-se-qup";
626 reg = <0 0x00ac0000 0 0x6000>;
627 clock-names = "m-ahb", "s-ahb";
628 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
629 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
630 #address-cells = <2>;
631 #size-cells = <2>;
632 ranges;
633 iommus = <&apps_smmu 0x4c3 0x0>;
634 status = "disabled";
635
636 i2c6: i2c@a80000 {
637 compatible = "qcom,geni-i2c";
638 reg = <0 0x00a80000 0 0x4000>;
639 clock-names = "se";
640 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
641 pinctrl-names = "default";
642 pinctrl-0 = <&qup_i2c6_default>;
643 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
644 #address-cells = <1>;
645 #size-cells = <0>;
646 status = "disabled";
647 };
648
649 spi6: spi@a80000 {
650 compatible = "qcom,geni-spi";
651 reg = <0 0x00a80000 0 0x4000>;
652 clock-names = "se";
653 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
654 pinctrl-names = "default";
655 pinctrl-0 = <&qup_spi6_default>;
656 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
657 #address-cells = <1>;
658 #size-cells = <0>;
659 status = "disabled";
660 };
661
662 uart6: serial@a80000 {
663 compatible = "qcom,geni-uart";
664 reg = <0 0x00a80000 0 0x4000>;
665 clock-names = "se";
666 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
667 pinctrl-names = "default";
668 pinctrl-0 = <&qup_uart6_default>;
669 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
670 status = "disabled";
671 };
672
673 i2c7: i2c@a84000 {
674 compatible = "qcom,geni-i2c";
675 reg = <0 0x00a84000 0 0x4000>;
676 clock-names = "se";
677 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
678 pinctrl-names = "default";
679 pinctrl-0 = <&qup_i2c7_default>;
680 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
681 #address-cells = <1>;
682 #size-cells = <0>;
683 status = "disabled";
684 };
685
686 uart7: serial@a84000 {
687 compatible = "qcom,geni-uart";
688 reg = <0 0x00a84000 0 0x4000>;
689 clock-names = "se";
690 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
691 pinctrl-names = "default";
692 pinctrl-0 = <&qup_uart7_default>;
693 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
694 status = "disabled";
695 };
696
697 i2c8: i2c@a88000 {
698 compatible = "qcom,geni-i2c";
699 reg = <0 0x00a88000 0 0x4000>;
700 clock-names = "se";
701 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
702 pinctrl-names = "default";
703 pinctrl-0 = <&qup_i2c8_default>;
704 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
705 #address-cells = <1>;
706 #size-cells = <0>;
707 status = "disabled";
708 };
709
710 spi8: spi@a88000 {
711 compatible = "qcom,geni-spi";
712 reg = <0 0x00a88000 0 0x4000>;
713 clock-names = "se";
714 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
715 pinctrl-names = "default";
716 pinctrl-0 = <&qup_spi8_default>;
717 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
718 #address-cells = <1>;
719 #size-cells = <0>;
720 status = "disabled";
721 };
722
723 uart8: serial@a88000 {
724 compatible = "qcom,geni-debug-uart";
725 reg = <0 0x00a88000 0 0x4000>;
726 clock-names = "se";
727 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
728 pinctrl-names = "default";
729 pinctrl-0 = <&qup_uart8_default>;
730 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
731 status = "disabled";
732 };
733
734 i2c9: i2c@a8c000 {
735 compatible = "qcom,geni-i2c";
736 reg = <0 0x00a8c000 0 0x4000>;
737 clock-names = "se";
738 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
739 pinctrl-names = "default";
740 pinctrl-0 = <&qup_i2c9_default>;
741 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
742 #address-cells = <1>;
743 #size-cells = <0>;
744 status = "disabled";
745 };
746
747 uart9: serial@a8c000 {
748 compatible = "qcom,geni-uart";
749 reg = <0 0x00a8c000 0 0x4000>;
750 clock-names = "se";
751 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
752 pinctrl-names = "default";
753 pinctrl-0 = <&qup_uart9_default>;
754 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
755 status = "disabled";
756 };
757
758 i2c10: i2c@a90000 {
759 compatible = "qcom,geni-i2c";
760 reg = <0 0x00a90000 0 0x4000>;
761 clock-names = "se";
762 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
763 pinctrl-names = "default";
764 pinctrl-0 = <&qup_i2c10_default>;
765 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
766 #address-cells = <1>;
767 #size-cells = <0>;
768 status = "disabled";
769 };
770
771 spi10: spi@a90000 {
772 compatible = "qcom,geni-spi";
773 reg = <0 0x00a90000 0 0x4000>;
774 clock-names = "se";
775 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
776 pinctrl-names = "default";
777 pinctrl-0 = <&qup_spi10_default>;
778 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
779 #address-cells = <1>;
780 #size-cells = <0>;
781 status = "disabled";
782 };
783
784 uart10: serial@a90000 {
785 compatible = "qcom,geni-uart";
786 reg = <0 0x00a90000 0 0x4000>;
787 clock-names = "se";
788 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
789 pinctrl-names = "default";
790 pinctrl-0 = <&qup_uart10_default>;
791 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
792 status = "disabled";
793 };
794
795 i2c11: i2c@a94000 {
796 compatible = "qcom,geni-i2c";
797 reg = <0 0x00a94000 0 0x4000>;
798 clock-names = "se";
799 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
800 pinctrl-names = "default";
801 pinctrl-0 = <&qup_i2c11_default>;
802 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
803 #address-cells = <1>;
804 #size-cells = <0>;
805 status = "disabled";
806 };
807
808 spi11: spi@a94000 {
809 compatible = "qcom,geni-spi";
810 reg = <0 0x00a94000 0 0x4000>;
811 clock-names = "se";
812 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
813 pinctrl-names = "default";
814 pinctrl-0 = <&qup_spi11_default>;
815 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
816 #address-cells = <1>;
817 #size-cells = <0>;
818 status = "disabled";
819 };
820
821 uart11: serial@a94000 {
822 compatible = "qcom,geni-uart";
823 reg = <0 0x00a94000 0 0x4000>;
824 clock-names = "se";
825 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
826 pinctrl-names = "default";
827 pinctrl-0 = <&qup_uart11_default>;
828 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
829 status = "disabled";
830 };
831 };
832
833 tcsr_mutex_regs: syscon@1f40000 {
834 compatible = "syscon";
835 reg = <0 0x01f40000 0 0x40000>;
836 };
837
838 tlmm: pinctrl@3500000 {
839 compatible = "qcom,sc7180-pinctrl";
840 reg = <0 0x03500000 0 0x300000>,
841 <0 0x03900000 0 0x300000>,
842 <0 0x03d00000 0 0x300000>;
843 reg-names = "west", "north", "south";
844 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
845 gpio-controller;
846 #gpio-cells = <2>;
847 interrupt-controller;
848 #interrupt-cells = <2>;
849 gpio-ranges = <&tlmm 0 0 120>;
850 wakeup-parent = <&pdc>;
851
852 qspi_clk: qspi-clk {
853 pinmux {
854 pins = "gpio63";
855 function = "qspi_clk";
856 };
857 };
858
859 qspi_cs0: qspi-cs0 {
860 pinmux {
861 pins = "gpio68";
862 function = "qspi_cs";
863 };
864 };
865
866 qspi_cs1: qspi-cs1 {
867 pinmux {
868 pins = "gpio72";
869 function = "qspi_cs";
870 };
871 };
872
873 qspi_data01: qspi-data01 {
874 pinmux-data {
875 pins = "gpio64", "gpio65";
876 function = "qspi_data";
877 };
878 };
879
880 qspi_data12: qspi-data12 {
881 pinmux-data {
882 pins = "gpio66", "gpio67";
883 function = "qspi_data";
884 };
885 };
886
887 qup_i2c0_default: qup-i2c0-default {
888 pinmux {
889 pins = "gpio34", "gpio35";
890 function = "qup00";
891 };
892 };
893
894 qup_i2c1_default: qup-i2c1-default {
895 pinmux {
896 pins = "gpio0", "gpio1";
897 function = "qup01";
898 };
899 };
900
901 qup_i2c2_default: qup-i2c2-default {
902 pinmux {
903 pins = "gpio15", "gpio16";
904 function = "qup02_i2c";
905 };
906 };
907
908 qup_i2c3_default: qup-i2c3-default {
909 pinmux {
910 pins = "gpio38", "gpio39";
911 function = "qup03";
912 };
913 };
914
915 qup_i2c4_default: qup-i2c4-default {
916 pinmux {
917 pins = "gpio115", "gpio116";
918 function = "qup04_i2c";
919 };
920 };
921
922 qup_i2c5_default: qup-i2c5-default {
923 pinmux {
924 pins = "gpio25", "gpio26";
925 function = "qup05";
926 };
927 };
928
929 qup_i2c6_default: qup-i2c6-default {
930 pinmux {
931 pins = "gpio59", "gpio60";
932 function = "qup10";
933 };
934 };
935
936 qup_i2c7_default: qup-i2c7-default {
937 pinmux {
938 pins = "gpio6", "gpio7";
939 function = "qup11_i2c";
940 };
941 };
942
943 qup_i2c8_default: qup-i2c8-default {
944 pinmux {
945 pins = "gpio42", "gpio43";
946 function = "qup12";
947 };
948 };
949
950 qup_i2c9_default: qup-i2c9-default {
951 pinmux {
952 pins = "gpio46", "gpio47";
953 function = "qup13_i2c";
954 };
955 };
956
957 qup_i2c10_default: qup-i2c10-default {
958 pinmux {
959 pins = "gpio86", "gpio87";
960 function = "qup14";
961 };
962 };
963
964 qup_i2c11_default: qup-i2c11-default {
965 pinmux {
966 pins = "gpio53", "gpio54";
967 function = "qup15";
968 };
969 };
970
971 qup_spi0_default: qup-spi0-default {
972 pinmux {
973 pins = "gpio34", "gpio35",
974 "gpio36", "gpio37";
975 function = "qup00";
976 };
977 };
978
979 qup_spi1_default: qup-spi1-default {
980 pinmux {
981 pins = "gpio0", "gpio1",
982 "gpio2", "gpio3";
983 function = "qup01";
984 };
985 };
986
987 qup_spi3_default: qup-spi3-default {
988 pinmux {
989 pins = "gpio38", "gpio39",
990 "gpio40", "gpio41";
991 function = "qup03";
992 };
993 };
994
995 qup_spi5_default: qup-spi5-default {
996 pinmux {
997 pins = "gpio25", "gpio26",
998 "gpio27", "gpio28";
999 function = "qup05";
1000 };
1001 };
1002
1003 qup_spi6_default: qup-spi6-default {
1004 pinmux {
1005 pins = "gpio59", "gpio60",
1006 "gpio61", "gpio62";
1007 function = "qup10";
1008 };
1009 };
1010
1011 qup_spi8_default: qup-spi8-default {
1012 pinmux {
1013 pins = "gpio42", "gpio43",
1014 "gpio44", "gpio45";
1015 function = "qup12";
1016 };
1017 };
1018
1019 qup_spi10_default: qup-spi10-default {
1020 pinmux {
1021 pins = "gpio86", "gpio87",
1022 "gpio88", "gpio89";
1023 function = "qup14";
1024 };
1025 };
1026
1027 qup_spi11_default: qup-spi11-default {
1028 pinmux {
1029 pins = "gpio53", "gpio54",
1030 "gpio55", "gpio56";
1031 function = "qup15";
1032 };
1033 };
1034
1035 qup_uart0_default: qup-uart0-default {
1036 pinmux {
1037 pins = "gpio34", "gpio35",
1038 "gpio36", "gpio37";
1039 function = "qup00";
1040 };
1041 };
1042
1043 qup_uart1_default: qup-uart1-default {
1044 pinmux {
1045 pins = "gpio0", "gpio1",
1046 "gpio2", "gpio3";
1047 function = "qup01";
1048 };
1049 };
1050
1051 qup_uart2_default: qup-uart2-default {
1052 pinmux {
1053 pins = "gpio15", "gpio16";
1054 function = "qup02_uart";
1055 };
1056 };
1057
1058 qup_uart3_default: qup-uart3-default {
1059 pinmux {
1060 pins = "gpio38", "gpio39",
1061 "gpio40", "gpio41";
1062 function = "qup03";
1063 };
1064 };
1065
1066 qup_uart4_default: qup-uart4-default {
1067 pinmux {
1068 pins = "gpio115", "gpio116";
1069 function = "qup04_uart";
1070 };
1071 };
1072
1073 qup_uart5_default: qup-uart5-default {
1074 pinmux {
1075 pins = "gpio25", "gpio26",
1076 "gpio27", "gpio28";
1077 function = "qup05";
1078 };
1079 };
1080
1081 qup_uart6_default: qup-uart6-default {
1082 pinmux {
1083 pins = "gpio59", "gpio60",
1084 "gpio61", "gpio62";
1085 function = "qup10";
1086 };
1087 };
1088
1089 qup_uart7_default: qup-uart7-default {
1090 pinmux {
1091 pins = "gpio6", "gpio7";
1092 function = "qup11_uart";
1093 };
1094 };
1095
1096 qup_uart8_default: qup-uart8-default {
1097 pinmux {
1098 pins = "gpio44", "gpio45";
1099 function = "qup12";
1100 };
1101 };
1102
1103 qup_uart9_default: qup-uart9-default {
1104 pinmux {
1105 pins = "gpio46", "gpio47";
1106 function = "qup13_uart";
1107 };
1108 };
1109
1110 qup_uart10_default: qup-uart10-default {
1111 pinmux {
1112 pins = "gpio86", "gpio87",
1113 "gpio88", "gpio89";
1114 function = "qup14";
1115 };
1116 };
1117
1118 qup_uart11_default: qup-uart11-default {
1119 pinmux {
1120 pins = "gpio53", "gpio54",
1121 "gpio55", "gpio56";
1122 function = "qup15";
1123 };
1124 };
1125
1126 sdc1_on: sdc1-on {
1127 pinconf-clk {
1128 pins = "sdc1_clk";
1129 bias-disable;
1130 drive-strength = <16>;
1131 };
1132
1133 pinconf-cmd {
1134 pins = "sdc1_cmd";
1135 bias-pull-up;
1136 drive-strength = <10>;
1137 };
1138
1139 pinconf-data {
1140 pins = "sdc1_data";
1141 bias-pull-up;
1142 drive-strength = <10>;
1143 };
1144
1145 pinconf-rclk {
1146 pins = "sdc1_rclk";
1147 bias-pull-down;
1148 };
1149 };
1150
1151 sdc1_off: sdc1-off {
1152 pinconf-clk {
1153 pins = "sdc1_clk";
1154 bias-disable;
1155 drive-strength = <2>;
1156 };
1157
1158 pinconf-cmd {
1159 pins = "sdc1_cmd";
1160 bias-pull-up;
1161 drive-strength = <2>;
1162 };
1163
1164 pinconf-data {
1165 pins = "sdc1_data";
1166 bias-pull-up;
1167 drive-strength = <2>;
1168 };
1169
1170 pinconf-rclk {
1171 pins = "sdc1_rclk";
1172 bias-pull-down;
1173 };
1174 };
1175
1176 sdc2_on: sdc2-on {
1177 pinconf-clk {
1178 pins = "sdc2_clk";
1179 bias-disable;
1180 drive-strength = <16>;
1181 };
1182
1183 pinconf-cmd {
1184 pins = "sdc2_cmd";
1185 bias-pull-up;
1186 drive-strength = <10>;
1187 };
1188
1189 pinconf-data {
1190 pins = "sdc2_data";
1191 bias-pull-up;
1192 drive-strength = <10>;
1193 };
1194
1195 pinconf-sd-cd {
1196 pins = "gpio69";
1197 bias-pull-up;
1198 drive-strength = <2>;
1199 };
1200 };
1201
1202 sdc2_off: sdc2-off {
1203 pinconf-clk {
1204 pins = "sdc2_clk";
1205 bias-disable;
1206 drive-strength = <2>;
1207 };
1208
1209 pinconf-cmd {
1210 pins = "sdc2_cmd";
1211 bias-pull-up;
1212 drive-strength = <2>;
1213 };
1214
1215 pinconf-data {
1216 pins = "sdc2_data";
1217 bias-pull-up;
1218 drive-strength = <2>;
1219 };
1220
1221 pinconf-sd-cd {
1222 pins = "gpio69";
1223 bias-disable;
1224 drive-strength = <2>;
1225 };
1226 };
1227 };
1228
1229 sdhc_2: sdhci@8804000 {
1230 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
1231 reg = <0 0x08804000 0 0x1000>;
1232 reg-names = "hc_mem";
1233
1234 iommus = <&apps_smmu 0x80 0>;
1235 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
1236 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1237 interrupt-names = "hc_irq", "pwr_irq";
1238
1239 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
1240 <&gcc GCC_SDCC2_AHB_CLK>;
1241 clock-names = "core", "iface";
1242
1243 bus-width = <4>;
1244
1245 status = "disabled";
1246 };
1247
1248 gpucc: clock-controller@5090000 {
1249 compatible = "qcom,sc7180-gpucc";
1250 reg = <0 0x05090000 0 0x9000>;
1251 clocks = <&rpmhcc RPMH_CXO_CLK>,
1252 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1253 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1254 clock-names = "bi_tcxo",
1255 "gcc_gpu_gpll0_clk_src",
1256 "gcc_gpu_gpll0_div_clk_src";
1257 #clock-cells = <1>;
1258 #reset-cells = <1>;
1259 #power-domain-cells = <1>;
1260 };
1261
1262 qspi: spi@88dc000 {
1263 compatible = "qcom,qspi-v1";
1264 reg = <0 0x088dc000 0 0x600>;
1265 #address-cells = <1>;
1266 #size-cells = <0>;
1267 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1268 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
1269 <&gcc GCC_QSPI_CORE_CLK>;
1270 clock-names = "iface", "core";
1271 status = "disabled";
1272 };
1273
1274 usb_1_hsphy: phy@88e3000 {
1275 compatible = "qcom,sc7180-qusb2-phy";
1276 reg = <0 0x088e3000 0 0x400>;
1277 status = "disabled";
1278 #phy-cells = <0>;
1279 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1280 <&rpmhcc RPMH_CXO_CLK>;
1281 clock-names = "cfg_ahb", "ref";
1282 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1283
1284 nvmem-cells = <&qusb2p_hstx_trim>;
1285 };
1286
1287 usb_1_qmpphy: phy-wrapper@88e9000 {
1288 compatible = "qcom,sc7180-qmp-usb3-phy";
1289 reg = <0 0x088e9000 0 0x18c>,
1290 <0 0x088e8000 0 0x38>;
1291 reg-names = "reg-base", "dp_com";
1292 status = "disabled";
1293 #clock-cells = <1>;
1294 #address-cells = <2>;
1295 #size-cells = <2>;
1296 ranges;
1297
1298 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1299 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1300 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
1301 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
1302 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
1303
1304 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
1305 <&gcc GCC_USB3_PHY_PRIM_BCR>;
1306 reset-names = "phy", "common";
1307
1308 usb_1_ssphy: phy@88e9200 {
1309 reg = <0 0x088e9200 0 0x128>,
1310 <0 0x088e9400 0 0x200>,
1311 <0 0x088e9c00 0 0x218>,
1312 <0 0x088e9600 0 0x128>,
1313 <0 0x088e9800 0 0x200>,
1314 <0 0x088e9a00 0 0x18>;
1315 #clock-cells = <0>;
1316 #phy-cells = <0>;
1317 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1318 clock-names = "pipe0";
1319 clock-output-names = "usb3_phy_pipe_clk_src";
1320 };
1321 };
1322
1323 system-cache-controller@9200000 {
1324 compatible = "qcom,sc7180-llcc";
1325 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
1326 reg-names = "llcc_base", "llcc_broadcast_base";
1327 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1328 };
1329
1330 usb_1: usb@a6f8800 {
1331 compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
1332 reg = <0 0x0a6f8800 0 0x400>;
1333 status = "disabled";
1334 #address-cells = <2>;
1335 #size-cells = <2>;
1336 ranges;
1337 dma-ranges;
1338
1339 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1340 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1341 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1342 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1343 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
1344 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1345 "sleep";
1346
1347 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1348 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1349 assigned-clock-rates = <19200000>, <150000000>;
1350
1351 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1352 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
1353 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
1354 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
1355 interrupt-names = "hs_phy_irq", "ss_phy_irq",
1356 "dm_hs_phy_irq", "dp_hs_phy_irq";
1357
1358 power-domains = <&gcc USB30_PRIM_GDSC>;
1359
1360 resets = <&gcc GCC_USB30_PRIM_BCR>;
1361
1362 usb_1_dwc3: dwc3@a600000 {
1363 compatible = "snps,dwc3";
1364 reg = <0 0x0a600000 0 0xe000>;
1365 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1366 iommus = <&apps_smmu 0x540 0>;
1367 snps,dis_u2_susphy_quirk;
1368 snps,dis_enblslpm_quirk;
1369 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
1370 phy-names = "usb2-phy", "usb3-phy";
1371 };
1372 };
1373
1374 videocc: clock-controller@ab00000 {
1375 compatible = "qcom,sc7180-videocc";
1376 reg = <0 0x0ab00000 0 0x10000>;
1377 clocks = <&rpmhcc RPMH_CXO_CLK>;
1378 clock-names = "bi_tcxo";
1379 #clock-cells = <1>;
1380 #reset-cells = <1>;
1381 #power-domain-cells = <1>;
1382 };
1383
1384 dispcc: clock-controller@af00000 {
1385 compatible = "qcom,sc7180-dispcc";
1386 reg = <0 0x0af00000 0 0x200000>;
1387 clocks = <&rpmhcc RPMH_CXO_CLK>,
1388 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
1389 <0>,
1390 <0>,
1391 <0>,
1392 <0>;
1393 clock-names = "bi_tcxo",
1394 "gcc_disp_gpll0_clk_src",
1395 "dsi0_phy_pll_out_byteclk",
1396 "dsi0_phy_pll_out_dsiclk",
1397 "dp_phy_pll_link_clk",
1398 "dp_phy_pll_vco_div_clk";
1399 #clock-cells = <1>;
1400 #reset-cells = <1>;
1401 #power-domain-cells = <1>;
1402 };
1403
1404 pdc: interrupt-controller@b220000 {
1405 compatible = "qcom,sc7180-pdc", "qcom,pdc";
1406 reg = <0 0x0b220000 0 0x30000>;
1407 qcom,pdc-ranges = <0 480 15>, <17 497 98>,
1408 <119 634 4>, <124 639 1>;
1409 #interrupt-cells = <2>;
1410 interrupt-parent = <&intc>;
1411 interrupt-controller;
1412 };
1413
1414 pdc_reset: reset-controller@b2e0000 {
1415 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
1416 reg = <0 0x0b2e0000 0 0x20000>;
1417 #reset-cells = <1>;
1418 };
1419
1420 tsens0: thermal-sensor@c263000 {
1421 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
1422 reg = <0 0x0c263000 0 0x1ff>, /* TM */
1423 <0 0x0c222000 0 0x1ff>; /* SROT */
1424 #qcom,sensors = <15>;
1425 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
1426 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
1427 interrupt-names = "uplow","critical";
1428 #thermal-sensor-cells = <1>;
1429 };
1430
1431 tsens1: thermal-sensor@c265000 {
1432 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
1433 reg = <0 0x0c265000 0 0x1ff>, /* TM */
1434 <0 0x0c223000 0 0x1ff>; /* SROT */
1435 #qcom,sensors = <10>;
1436 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
1437 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
1438 interrupt-names = "uplow","critical";
1439 #thermal-sensor-cells = <1>;
1440 };
1441
1442 aoss_reset: reset-controller@c2a0000 {
1443 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
1444 reg = <0 0x0c2a0000 0 0x31000>;
1445 #reset-cells = <1>;
1446 };
1447
1448 aoss_qmp: qmp@c300000 {
1449 compatible = "qcom,sc7180-aoss-qmp";
1450 reg = <0 0x0c300000 0 0x100000>;
1451 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
1452 mboxes = <&apss_shared 0>;
1453
1454 #clock-cells = <0>;
1455 #power-domain-cells = <1>;
1456 };
1457
1458 spmi_bus: spmi@c440000 {
1459 compatible = "qcom,spmi-pmic-arb";
1460 reg = <0 0x0c440000 0 0x1100>,
1461 <0 0x0c600000 0 0x2000000>,
1462 <0 0x0e600000 0 0x100000>,
1463 <0 0x0e700000 0 0xa0000>,
1464 <0 0x0c40a000 0 0x26000>;
1465 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1466 interrupt-names = "periph_irq";
1467 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1468 qcom,ee = <0>;
1469 qcom,channel = <0>;
1470 #address-cells = <1>;
1471 #size-cells = <1>;
1472 interrupt-controller;
1473 #interrupt-cells = <4>;
1474 cell-index = <0>;
1475 };
1476
1477 apps_smmu: iommu@15000000 {
1478 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
1479 reg = <0 0x15000000 0 0x100000>;
1480 #iommu-cells = <2>;
1481 #global-interrupts = <1>;
1482 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1483 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1484 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1485 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1486 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1487 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1488 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1489 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1490 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1491 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1492 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1493 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1494 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1495 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1496 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1497 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1498 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1499 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1500 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1501 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1502 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1503 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1504 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1505 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1506 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1507 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1508 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1509 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1510 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1511 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1512 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1513 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1514 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1515 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1516 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1517 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1518 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1519 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1520 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1521 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1522 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1523 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1524 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1525 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1526 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1527 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1528 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1529 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1530 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1531 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1532 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1533 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1539 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1540 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1541 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1542 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1543 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1544 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1545 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1546 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1547 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1548 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1549 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
1550 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
1551 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1552 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1553 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1554 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1555 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
1556 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
1557 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
1558 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
1559 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
1560 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
1561 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
1562 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
1563 };
1564
1565 intc: interrupt-controller@17a00000 {
1566 compatible = "arm,gic-v3";
1567 #address-cells = <2>;
1568 #size-cells = <2>;
1569 ranges;
1570 #interrupt-cells = <3>;
1571 interrupt-controller;
1572 reg = <0 0x17a00000 0 0x10000>, /* GICD */
1573 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
1574 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1575
1576 msi-controller@17a40000 {
1577 compatible = "arm,gic-v3-its";
1578 msi-controller;
1579 #msi-cells = <1>;
1580 reg = <0 0x17a40000 0 0x20000>;
1581 status = "disabled";
1582 };
1583 };
1584
1585 apss_shared: mailbox@17c00000 {
1586 compatible = "qcom,sc7180-apss-shared";
1587 reg = <0 0x17c00000 0 0x10000>;
1588 #mbox-cells = <1>;
1589 };
1590
1591 watchdog@17c10000 {
1592 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
1593 reg = <0 0x17c10000 0 0x1000>;
1594 clocks = <&sleep_clk>;
1595 };
1596
1597 timer@17c20000{
1598 #address-cells = <2>;
1599 #size-cells = <2>;
1600 ranges;
1601 compatible = "arm,armv7-timer-mem";
1602 reg = <0 0x17c20000 0 0x1000>;
1603
1604 frame@17c21000 {
1605 frame-number = <0>;
1606 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1607 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1608 reg = <0 0x17c21000 0 0x1000>,
1609 <0 0x17c22000 0 0x1000>;
1610 };
1611
1612 frame@17c23000 {
1613 frame-number = <1>;
1614 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1615 reg = <0 0x17c23000 0 0x1000>;
1616 status = "disabled";
1617 };
1618
1619 frame@17c25000 {
1620 frame-number = <2>;
1621 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1622 reg = <0 0x17c25000 0 0x1000>;
1623 status = "disabled";
1624 };
1625
1626 frame@17c27000 {
1627 frame-number = <3>;
1628 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1629 reg = <0 0x17c27000 0 0x1000>;
1630 status = "disabled";
1631 };
1632
1633 frame@17c29000 {
1634 frame-number = <4>;
1635 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1636 reg = <0 0x17c29000 0 0x1000>;
1637 status = "disabled";
1638 };
1639
1640 frame@17c2b000 {
1641 frame-number = <5>;
1642 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1643 reg = <0 0x17c2b000 0 0x1000>;
1644 status = "disabled";
1645 };
1646
1647 frame@17c2d000 {
1648 frame-number = <6>;
1649 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1650 reg = <0 0x17c2d000 0 0x1000>;
1651 status = "disabled";
1652 };
1653 };
1654
1655 apps_rsc: rsc@18200000 {
1656 compatible = "qcom,rpmh-rsc";
1657 reg = <0 0x18200000 0 0x10000>,
1658 <0 0x18210000 0 0x10000>,
1659 <0 0x18220000 0 0x10000>;
1660 reg-names = "drv-0", "drv-1", "drv-2";
1661 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1662 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1663 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1664 qcom,tcs-offset = <0xd00>;
1665 qcom,drv-id = <2>;
1666 qcom,tcs-config = <ACTIVE_TCS 2>,
1667 <SLEEP_TCS 3>,
1668 <WAKE_TCS 3>,
1669 <CONTROL_TCS 1>;
1670
1671 rpmhcc: clock-controller {
1672 compatible = "qcom,sc7180-rpmh-clk";
1673 clocks = <&xo_board>;
1674 clock-names = "xo";
1675 #clock-cells = <1>;
1676 };
1677
1678 rpmhpd: power-controller {
1679 compatible = "qcom,sc7180-rpmhpd";
1680 #power-domain-cells = <1>;
1681 operating-points-v2 = <&rpmhpd_opp_table>;
1682
1683 rpmhpd_opp_table: opp-table {
1684 compatible = "operating-points-v2";
1685
1686 rpmhpd_opp_ret: opp1 {
1687 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1688 };
1689
1690 rpmhpd_opp_min_svs: opp2 {
1691 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1692 };
1693
1694 rpmhpd_opp_low_svs: opp3 {
1695 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1696 };
1697
1698 rpmhpd_opp_svs: opp4 {
1699 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1700 };
1701
1702 rpmhpd_opp_svs_l1: opp5 {
1703 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1704 };
1705
1706 rpmhpd_opp_svs_l2: opp6 {
1707 opp-level = <224>;
1708 };
1709
1710 rpmhpd_opp_nom: opp7 {
1711 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1712 };
1713
1714 rpmhpd_opp_nom_l1: opp8 {
1715 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1716 };
1717
1718 rpmhpd_opp_nom_l2: opp9 {
1719 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1720 };
1721
1722 rpmhpd_opp_turbo: opp10 {
1723 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1724 };
1725
1726 rpmhpd_opp_turbo_l1: opp11 {
1727 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1728 };
1729 };
1730 };
1731 };
1732
1733 cpufreq_hw: cpufreq@18323000 {
1734 compatible = "qcom,cpufreq-hw";
1735 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
1736 reg-names = "freq-domain0", "freq-domain1";
1737
1738 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
1739 clock-names = "xo", "alternate";
1740
1741 #freq-domain-cells = <1>;
1742 };
1743 };
1744
1745 thermal-zones {
1746 cpu0-thermal {
1747 polling-delay-passive = <250>;
1748 polling-delay = <1000>;
1749
1750 thermal-sensors = <&tsens0 1>;
1751
1752 trips {
1753 cpu0_alert0: trip-point0 {
1754 temperature = <90000>;
1755 hysteresis = <2000>;
1756 type = "passive";
1757 };
1758
1759 cpu0_alert1: trip-point1 {
1760 temperature = <95000>;
1761 hysteresis = <2000>;
1762 type = "passive";
1763 };
1764
1765 cpu0_crit: cpu_crit {
1766 temperature = <110000>;
1767 hysteresis = <1000>;
1768 type = "critical";
1769 };
1770 };
1771
1772 cooling-maps {
1773 map0 {
1774 trip = <&cpu0_alert0>;
1775 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1776 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1777 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1778 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1779 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1780 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1781 };
1782 map1 {
1783 trip = <&cpu0_alert1>;
1784 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1785 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1786 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1787 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1788 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1789 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1790 };
1791 };
1792 };
1793
1794 cpu1-thermal {
1795 polling-delay-passive = <250>;
1796 polling-delay = <1000>;
1797
1798 thermal-sensors = <&tsens0 2>;
1799
1800 trips {
1801 cpu1_alert0: trip-point0 {
1802 temperature = <90000>;
1803 hysteresis = <2000>;
1804 type = "passive";
1805 };
1806
1807 cpu1_alert1: trip-point1 {
1808 temperature = <95000>;
1809 hysteresis = <2000>;
1810 type = "passive";
1811 };
1812
1813 cpu1_crit: cpu_crit {
1814 temperature = <110000>;
1815 hysteresis = <1000>;
1816 type = "critical";
1817 };
1818 };
1819
1820 cooling-maps {
1821 map0 {
1822 trip = <&cpu1_alert0>;
1823 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1824 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1825 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1826 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1827 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1828 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1829 };
1830 map1 {
1831 trip = <&cpu1_alert1>;
1832 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1833 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1834 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1835 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1836 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1837 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1838 };
1839 };
1840 };
1841
1842 cpu2-thermal {
1843 polling-delay-passive = <250>;
1844 polling-delay = <1000>;
1845
1846 thermal-sensors = <&tsens0 3>;
1847
1848 trips {
1849 cpu2_alert0: trip-point0 {
1850 temperature = <90000>;
1851 hysteresis = <2000>;
1852 type = "passive";
1853 };
1854
1855 cpu2_alert1: trip-point1 {
1856 temperature = <95000>;
1857 hysteresis = <2000>;
1858 type = "passive";
1859 };
1860
1861 cpu2_crit: cpu_crit {
1862 temperature = <110000>;
1863 hysteresis = <1000>;
1864 type = "critical";
1865 };
1866 };
1867
1868 cooling-maps {
1869 map0 {
1870 trip = <&cpu2_alert0>;
1871 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1872 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1873 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1874 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1875 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1876 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1877 };
1878 map1 {
1879 trip = <&cpu2_alert1>;
1880 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1881 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1882 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1883 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1884 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1885 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1886 };
1887 };
1888 };
1889
1890 cpu3-thermal {
1891 polling-delay-passive = <250>;
1892 polling-delay = <1000>;
1893
1894 thermal-sensors = <&tsens0 4>;
1895
1896 trips {
1897 cpu3_alert0: trip-point0 {
1898 temperature = <90000>;
1899 hysteresis = <2000>;
1900 type = "passive";
1901 };
1902
1903 cpu3_alert1: trip-point1 {
1904 temperature = <95000>;
1905 hysteresis = <2000>;
1906 type = "passive";
1907 };
1908
1909 cpu3_crit: cpu_crit {
1910 temperature = <110000>;
1911 hysteresis = <1000>;
1912 type = "critical";
1913 };
1914 };
1915
1916 cooling-maps {
1917 map0 {
1918 trip = <&cpu3_alert0>;
1919 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1920 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1921 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1922 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1923 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1924 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1925 };
1926 map1 {
1927 trip = <&cpu3_alert1>;
1928 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1929 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1930 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1931 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1932 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1933 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1934 };
1935 };
1936 };
1937
1938 cpu4-thermal {
1939 polling-delay-passive = <250>;
1940 polling-delay = <1000>;
1941
1942 thermal-sensors = <&tsens0 5>;
1943
1944 trips {
1945 cpu4_alert0: trip-point0 {
1946 temperature = <90000>;
1947 hysteresis = <2000>;
1948 type = "passive";
1949 };
1950
1951 cpu4_alert1: trip-point1 {
1952 temperature = <95000>;
1953 hysteresis = <2000>;
1954 type = "passive";
1955 };
1956
1957 cpu4_crit: cpu_crit {
1958 temperature = <110000>;
1959 hysteresis = <1000>;
1960 type = "critical";
1961 };
1962 };
1963
1964 cooling-maps {
1965 map0 {
1966 trip = <&cpu4_alert0>;
1967 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1968 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1969 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1970 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1971 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1972 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1973 };
1974 map1 {
1975 trip = <&cpu4_alert1>;
1976 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1977 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1978 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1979 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1980 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1981 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1982 };
1983 };
1984 };
1985
1986 cpu5-thermal {
1987 polling-delay-passive = <250>;
1988 polling-delay = <1000>;
1989
1990 thermal-sensors = <&tsens0 6>;
1991
1992 trips {
1993 cpu5_alert0: trip-point0 {
1994 temperature = <90000>;
1995 hysteresis = <2000>;
1996 type = "passive";
1997 };
1998
1999 cpu5_alert1: trip-point1 {
2000 temperature = <95000>;
2001 hysteresis = <2000>;
2002 type = "passive";
2003 };
2004
2005 cpu5_crit: cpu_crit {
2006 temperature = <110000>;
2007 hysteresis = <1000>;
2008 type = "critical";
2009 };
2010 };
2011
2012 cooling-maps {
2013 map0 {
2014 trip = <&cpu5_alert0>;
2015 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2016 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2017 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2018 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2019 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2020 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2021 };
2022 map1 {
2023 trip = <&cpu5_alert1>;
2024 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2025 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2026 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2027 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2028 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2029 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2030 };
2031 };
2032 };
2033
2034 cpu6-thermal {
2035 polling-delay-passive = <250>;
2036 polling-delay = <1000>;
2037
2038 thermal-sensors = <&tsens0 9>;
2039
2040 trips {
2041 cpu6_alert0: trip-point0 {
2042 temperature = <90000>;
2043 hysteresis = <2000>;
2044 type = "passive";
2045 };
2046
2047 cpu6_alert1: trip-point1 {
2048 temperature = <95000>;
2049 hysteresis = <2000>;
2050 type = "passive";
2051 };
2052
2053 cpu6_crit: cpu_crit {
2054 temperature = <110000>;
2055 hysteresis = <1000>;
2056 type = "critical";
2057 };
2058 };
2059
2060 cooling-maps {
2061 map0 {
2062 trip = <&cpu6_alert0>;
2063 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2064 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2065 };
2066 map1 {
2067 trip = <&cpu6_alert1>;
2068 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2069 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2070 };
2071 };
2072 };
2073
2074 cpu7-thermal {
2075 polling-delay-passive = <250>;
2076 polling-delay = <1000>;
2077
2078 thermal-sensors = <&tsens0 10>;
2079
2080 trips {
2081 cpu7_alert0: trip-point0 {
2082 temperature = <90000>;
2083 hysteresis = <2000>;
2084 type = "passive";
2085 };
2086
2087 cpu7_alert1: trip-point1 {
2088 temperature = <95000>;
2089 hysteresis = <2000>;
2090 type = "passive";
2091 };
2092
2093 cpu7_crit: cpu_crit {
2094 temperature = <110000>;
2095 hysteresis = <1000>;
2096 type = "critical";
2097 };
2098 };
2099
2100 cooling-maps {
2101 map0 {
2102 trip = <&cpu7_alert0>;
2103 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2104 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2105 };
2106 map1 {
2107 trip = <&cpu7_alert1>;
2108 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2109 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2110 };
2111 };
2112 };
2113
2114 cpu8-thermal {
2115 polling-delay-passive = <250>;
2116 polling-delay = <1000>;
2117
2118 thermal-sensors = <&tsens0 11>;
2119
2120 trips {
2121 cpu8_alert0: trip-point0 {
2122 temperature = <90000>;
2123 hysteresis = <2000>;
2124 type = "passive";
2125 };
2126
2127 cpu8_alert1: trip-point1 {
2128 temperature = <95000>;
2129 hysteresis = <2000>;
2130 type = "passive";
2131 };
2132
2133 cpu8_crit: cpu_crit {
2134 temperature = <110000>;
2135 hysteresis = <1000>;
2136 type = "critical";
2137 };
2138 };
2139
2140 cooling-maps {
2141 map0 {
2142 trip = <&cpu8_alert0>;
2143 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2144 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2145 };
2146 map1 {
2147 trip = <&cpu8_alert1>;
2148 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2149 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2150 };
2151 };
2152 };
2153
2154 cpu9-thermal {
2155 polling-delay-passive = <250>;
2156 polling-delay = <1000>;
2157
2158 thermal-sensors = <&tsens0 12>;
2159
2160 trips {
2161 cpu9_alert0: trip-point0 {
2162 temperature = <90000>;
2163 hysteresis = <2000>;
2164 type = "passive";
2165 };
2166
2167 cpu9_alert1: trip-point1 {
2168 temperature = <95000>;
2169 hysteresis = <2000>;
2170 type = "passive";
2171 };
2172
2173 cpu9_crit: cpu_crit {
2174 temperature = <110000>;
2175 hysteresis = <1000>;
2176 type = "critical";
2177 };
2178 };
2179
2180 cooling-maps {
2181 map0 {
2182 trip = <&cpu9_alert0>;
2183 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2184 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2185 };
2186 map1 {
2187 trip = <&cpu9_alert1>;
2188 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2189 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2190 };
2191 };
2192 };
2193
2194 aoss0-thermal {
2195 polling-delay-passive = <250>;
2196 polling-delay = <1000>;
2197
2198 thermal-sensors = <&tsens0 0>;
2199
2200 trips {
2201 aoss0_alert0: trip-point0 {
2202 temperature = <90000>;
2203 hysteresis = <2000>;
2204 type = "hot";
2205 };
2206 };
2207 };
2208
2209 cpuss0-thermal {
2210 polling-delay-passive = <250>;
2211 polling-delay = <1000>;
2212
2213 thermal-sensors = <&tsens0 7>;
2214
2215 trips {
2216 cpuss0_alert0: trip-point0 {
2217 temperature = <90000>;
2218 hysteresis = <2000>;
2219 type = "hot";
2220 };
2221 cpuss0_crit: cluster0_crit {
2222 temperature = <110000>;
2223 hysteresis = <2000>;
2224 type = "critical";
2225 };
2226 };
2227 };
2228
2229 cpuss1-thermal {
2230 polling-delay-passive = <250>;
2231 polling-delay = <1000>;
2232
2233 thermal-sensors = <&tsens0 8>;
2234
2235 trips {
2236 cpuss1_alert0: trip-point0 {
2237 temperature = <90000>;
2238 hysteresis = <2000>;
2239 type = "hot";
2240 };
2241 cpuss1_crit: cluster0_crit {
2242 temperature = <110000>;
2243 hysteresis = <2000>;
2244 type = "critical";
2245 };
2246 };
2247 };
2248
2249 gpuss0-thermal {
2250 polling-delay-passive = <250>;
2251 polling-delay = <1000>;
2252
2253 thermal-sensors = <&tsens0 13>;
2254
2255 trips {
2256 gpuss0_alert0: trip-point0 {
2257 temperature = <90000>;
2258 hysteresis = <2000>;
2259 type = "hot";
2260 };
2261 };
2262 };
2263
2264 gpuss1-thermal {
2265 polling-delay-passive = <250>;
2266 polling-delay = <1000>;
2267
2268 thermal-sensors = <&tsens0 14>;
2269
2270 trips {
2271 gpuss1_alert0: trip-point0 {
2272 temperature = <90000>;
2273 hysteresis = <2000>;
2274 type = "hot";
2275 };
2276 };
2277 };
2278
2279 aoss1-thermal {
2280 polling-delay-passive = <250>;
2281 polling-delay = <1000>;
2282
2283 thermal-sensors = <&tsens1 0>;
2284
2285 trips {
2286 aoss1_alert0: trip-point0 {
2287 temperature = <90000>;
2288 hysteresis = <2000>;
2289 type = "hot";
2290 };
2291 };
2292 };
2293
2294 cwlan-thermal {
2295 polling-delay-passive = <250>;
2296 polling-delay = <1000>;
2297
2298 thermal-sensors = <&tsens1 1>;
2299
2300 trips {
2301 cwlan_alert0: trip-point0 {
2302 temperature = <90000>;
2303 hysteresis = <2000>;
2304 type = "hot";
2305 };
2306 };
2307 };
2308
2309 audio-thermal {
2310 polling-delay-passive = <250>;
2311 polling-delay = <1000>;
2312
2313 thermal-sensors = <&tsens1 2>;
2314
2315 trips {
2316 audio_alert0: trip-point0 {
2317 temperature = <90000>;
2318 hysteresis = <2000>;
2319 type = "hot";
2320 };
2321 };
2322 };
2323
2324 ddr-thermal {
2325 polling-delay-passive = <250>;
2326 polling-delay = <1000>;
2327
2328 thermal-sensors = <&tsens1 3>;
2329
2330 trips {
2331 ddr_alert0: trip-point0 {
2332 temperature = <90000>;
2333 hysteresis = <2000>;
2334 type = "hot";
2335 };
2336 };
2337 };
2338
2339 q6-hvx-thermal {
2340 polling-delay-passive = <250>;
2341 polling-delay = <1000>;
2342
2343 thermal-sensors = <&tsens1 4>;
2344
2345 trips {
2346 q6_hvx_alert0: trip-point0 {
2347 temperature = <90000>;
2348 hysteresis = <2000>;
2349 type = "hot";
2350 };
2351 };
2352 };
2353
2354 camera-thermal {
2355 polling-delay-passive = <250>;
2356 polling-delay = <1000>;
2357
2358 thermal-sensors = <&tsens1 5>;
2359
2360 trips {
2361 camera_alert0: trip-point0 {
2362 temperature = <90000>;
2363 hysteresis = <2000>;
2364 type = "hot";
2365 };
2366 };
2367 };
2368
2369 mdm-core-thermal {
2370 polling-delay-passive = <250>;
2371 polling-delay = <1000>;
2372
2373 thermal-sensors = <&tsens1 6>;
2374
2375 trips {
2376 mdm_alert0: trip-point0 {
2377 temperature = <90000>;
2378 hysteresis = <2000>;
2379 type = "hot";
2380 };
2381 };
2382 };
2383
2384 mdm-dsp-thermal {
2385 polling-delay-passive = <250>;
2386 polling-delay = <1000>;
2387
2388 thermal-sensors = <&tsens1 7>;
2389
2390 trips {
2391 mdm_dsp_alert0: trip-point0 {
2392 temperature = <90000>;
2393 hysteresis = <2000>;
2394 type = "hot";
2395 };
2396 };
2397 };
2398
2399 npu-thermal {
2400 polling-delay-passive = <250>;
2401 polling-delay = <1000>;
2402
2403 thermal-sensors = <&tsens1 8>;
2404
2405 trips {
2406 npu_alert0: trip-point0 {
2407 temperature = <90000>;
2408 hysteresis = <2000>;
2409 type = "hot";
2410 };
2411 };
2412 };
2413
2414 video-thermal {
2415 polling-delay-passive = <250>;
2416 polling-delay = <1000>;
2417
2418 thermal-sensors = <&tsens1 9>;
2419
2420 trips {
2421 video_alert0: trip-point0 {
2422 temperature = <90000>;
2423 hysteresis = <2000>;
2424 type = "hot";
2425 };
2426 };
2427 };
2428 };
2429
2430 timer {
2431 compatible = "arm,armv8-timer";
2432 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
2433 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
2434 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
2435 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
2436 };
2437 };
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