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1 From d1b83761cef13adca83c97dea088e883862a721d Mon Sep 17 00:00:00 2001
2 From: Dave Stevenson <dave.stevenson@raspberrypi.com>
3 Date: Fri, 21 Jun 2024 16:59:51 +0100
4 Subject: [PATCH] arm64: dts: broadcom: Add display pipeline support to BCM2712
5
6 Adds the HVS and associated hardware blocks to support the HDMI
7 and writeback connectors on BCM2712 / Pi5.
8
9 Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
10 ---
11 .../boot/dts/broadcom/bcm2712-rpi-5-b.dts | 14 ++
12 arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 189 ++++++++++++++++++
13 2 files changed, 203 insertions(+)
14
15 --- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
16 +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
17 @@ -732,5 +732,19 @@ spi10_cs_pins: &spi10_cs_gpio1 {};
18 firmware = <&firmware>;
19 #power-domain-cells = <1>;
20 };
21 +};
22 +
23 +&hvs {
24 + clocks = <&firmware_clocks 4>, <&firmware_clocks 16>;
25 + clock-names = "core", "disp";
26 +};
27 +
28 +&hdmi0 {
29 + clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>;
30 + clock-names = "hdmi", "bvb", "audio", "cec";
31 +};
32
33 +&hdmi1 {
34 + clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;
35 + clock-names = "hdmi", "bvb", "audio", "cec";
36 };
37 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
38 +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
39 @@ -265,6 +265,172 @@
40 interrupt-controller;
41 #interrupt-cells = <3>;
42 };
43 +
44 + aon_intr: interrupt-controller@7d510600 {
45 + compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
46 + reg = <0x7d510600 0x30>;
47 + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
48 + interrupt-controller;
49 + #interrupt-cells = <1>;
50 + };
51 +
52 + pixelvalve0: pixelvalve@7c410000 {
53 + compatible = "brcm,bcm2712-pixelvalve0";
54 + reg = <0x7c410000 0x100>;
55 + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
56 + };
57 +
58 + pixelvalve1: pixelvalve@7c411000 {
59 + compatible = "brcm,bcm2712-pixelvalve1";
60 + reg = <0x7c411000 0x100>;
61 + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
62 + };
63 +
64 + mop: mop@7c500000 {
65 + compatible = "brcm,bcm2712-mop";
66 + reg = <0x7c500000 0x28>;
67 + interrupt-parent = <&disp_intr>;
68 + interrupts = <1>;
69 + };
70 +
71 + moplet: moplet@7c501000 {
72 + compatible = "brcm,bcm2712-moplet";
73 + reg = <0x7c501000 0x20>;
74 + interrupt-parent = <&disp_intr>;
75 + interrupts = <0>;
76 + };
77 +
78 + disp_intr: interrupt-controller@7c502000 {
79 + compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
80 + reg = <0x7c502000 0x30>;
81 + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
82 + interrupt-controller;
83 + #interrupt-cells = <1>;
84 + };
85 +
86 + dvp: clock@7c700000 {
87 + compatible = "brcm,brcm2711-dvp";
88 + reg = <0x7c700000 0x10>;
89 + clocks = <&clk_108MHz>;
90 + #clock-cells = <1>;
91 + #reset-cells = <1>;
92 + };
93 +
94 + ddc0: i2c@7d508200 {
95 + compatible = "brcm,brcmstb-i2c";
96 + reg = <0x7d508200 0x58>;
97 + interrupt-parent = <&bsc_irq>;
98 + interrupts = <1>;
99 + clock-frequency = <97500>;
100 + #address-cells = <1>;
101 + #size-cells = <0>;
102 + };
103 +
104 + ddc1: i2c@7d508280 {
105 + compatible = "brcm,brcmstb-i2c";
106 + reg = <0x7d508280 0x58>;
107 + interrupt-parent = <&bsc_irq>;
108 + interrupts = <2>;
109 + clock-frequency = <97500>;
110 + #address-cells = <1>;
111 + #size-cells = <0>;
112 + };
113 +
114 + bsc_irq: intc@7d508380 {
115 + compatible = "brcm,bcm7271-l2-intc";
116 + reg = <0x7d508380 0x10>;
117 + interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
118 + interrupt-controller;
119 + #interrupt-cells = <1>;
120 + };
121 +
122 + main_irq: intc@7d508400 {
123 + compatible = "brcm,bcm7271-l2-intc";
124 + reg = <0x7d508400 0x10>;
125 + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
126 + interrupt-controller;
127 + #interrupt-cells = <1>;
128 + };
129 +
130 + hdmi0: hdmi@7ef00700 {
131 + compatible = "brcm,bcm2712-hdmi0";
132 + reg = <0x7c701400 0x300>,
133 + <0x7c701000 0x200>,
134 + <0x7c701d00 0x300>,
135 + <0x7c702000 0x80>,
136 + <0x7c703800 0x200>,
137 + <0x7c704000 0x800>,
138 + <0x7c700100 0x80>,
139 + <0x7d510800 0x100>,
140 + <0x7c720000 0x100>;
141 + reg-names = "hdmi",
142 + "dvp",
143 + "phy",
144 + "rm",
145 + "packet",
146 + "metadata",
147 + "csc",
148 + "cec",
149 + "hd";
150 + resets = <&dvp 1>;
151 + interrupt-parent = <&aon_intr>;
152 + interrupts = <1>, <2>, <3>,
153 + <7>, <8>;
154 + interrupt-names = "cec-tx", "cec-rx", "cec-low",
155 + "hpd-connected", "hpd-removed";
156 + ddc = <&ddc0>;
157 + };
158 +
159 + hdmi1: hdmi@7ef05700 {
160 + compatible = "brcm,bcm2712-hdmi1";
161 + reg = <0x7c706400 0x300>,
162 + <0x7c706000 0x200>,
163 + <0x7c706d00 0x300>,
164 + <0x7c707000 0x80>,
165 + <0x7c708800 0x200>,
166 + <0x7c709000 0x800>,
167 + <0x7c700180 0x80>,
168 + <0x7d511000 0x100>,
169 + <0x7c720000 0x100>;
170 + reg-names = "hdmi",
171 + "dvp",
172 + "phy",
173 + "rm",
174 + "packet",
175 + "metadata",
176 + "csc",
177 + "cec",
178 + "hd";
179 + resets = <&dvp 2>;
180 + interrupt-parent = <&aon_intr>;
181 + interrupts = <11>, <12>, <13>,
182 + <14>, <15>;
183 + interrupt-names = "cec-tx", "cec-rx", "cec-low",
184 + "hpd-connected", "hpd-removed";
185 + ddc = <&ddc1>;
186 + };
187 + };
188 +
189 + axi: axi {
190 + compatible = "simple-bus";
191 + #address-cells = <2>;
192 + #size-cells = <2>;
193 +
194 + ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>,
195 + <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>,
196 + <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>,
197 + <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>,
198 + <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>;
199 +
200 + dma-ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>,
201 + <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>,
202 + <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>,
203 + <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>,
204 + <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>;
205 +
206 + vc4: gpu {
207 + compatible = "brcm,bcm2712-vc6";
208 + };
209 };
210
211 timer {
212 @@ -280,4 +446,27 @@
213 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) |
214 IRQ_TYPE_LEVEL_LOW)>;
215 };
216 +
217 + clk_27MHz: clk-27M {
218 + #clock-cells = <0>;
219 + compatible = "fixed-clock";
220 + clock-frequency = <27000000>;
221 + clock-output-names = "27MHz-clock";
222 + };
223 +
224 + clk_108MHz: clk-108M {
225 + #clock-cells = <0>;
226 + compatible = "fixed-clock";
227 + clock-frequency = <108000000>;
228 + clock-output-names = "108MHz-clock";
229 + };
230 +
231 + hvs: hvs@107c580000 {
232 + compatible = "brcm,bcm2712-hvs";
233 + reg = <0x10 0x7c580000 0x0 0x1a000>;
234 + interrupt-parent = <&disp_intr>;
235 + interrupts = <2>, <9>, <16>;
236 + interrupt-names = "ch0-eof", "ch1-eof", "ch2-eof";
237 + //iommus = <&iommu4>;
238 + };
239 };
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