1 From 382bd6a792836875da555fe9a2b51222b813fed1 Mon Sep 17 00:00:00 2001
2 From: Matthew Schwartz <matthew.schwartz@linux.dev>
3 Date: Mon, 20 Oct 2025 16:09:34 -0700
4 Subject: drm/amd/display: Don't program BLNDGAM_MEM_PWR_FORCE when CM low-power is disabled on DCN30
6 From: Matthew Schwartz <matthew.schwartz@linux.dev>
8 commit 382bd6a792836875da555fe9a2b51222b813fed1 upstream.
10 Before commit 33056a97ae5e ("drm/amd/display: Remove double checks for
11 `debug.enable_mem_low_power.bits.cm`"), dpp3_program_blnd_lut(NULL)
12 checked the low-power debug flag before calling
13 dpp3_power_on_blnd_lut(false).
15 After commit 33056a97ae5e ("drm/amd/display: Remove double checks for
16 `debug.enable_mem_low_power.bits.cm`"), dpp3_program_blnd_lut(NULL)
17 unconditionally calls dpp3_power_on_blnd_lut(false). The BLNDGAM power
18 helper writes BLNDGAM_MEM_PWR_FORCE when CM low-power is disabled, causing
19 immediate SRAM power toggles instead of deferring at vupdate. This can
20 disrupt atomic color/LUT sequencing during transitions between
21 direct scanout and composition within gamescope's DRM backend on
24 To fix this, leave the BLNDGAM power state unchanged when low-power is
25 disabled, matching dpp3_power_on_hdr3dlut and dpp3_power_on_shaper.
27 Fixes: 33056a97ae5e ("drm/amd/display: Remove double checks for `debug.enable_mem_low_power.bits.cm`")
28 Signed-off-by: Matthew Schwartz <matthew.schwartz@linux.dev>
29 Reviewed-by: Harry Wentland <harry.wentland@amd.com>
30 Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
31 Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
32 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
33 (cherry picked from commit 13ff4f63fcddfc84ec8632f1443936b00aa26725)
34 Cc: stable@vger.kernel.org
35 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
37 drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c | 3 ---
38 1 file changed, 3 deletions(-)
40 diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
41 index 09be2a90cc79..4f569cd8a5d6 100644
42 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
43 +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
44 @@ -578,9 +578,6 @@ static void dpp3_power_on_blnd_lut(
45 dpp_base->ctx->dc->optimized_required = true;
46 dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true;
49 - REG_SET(CM_MEM_PWR_CTRL, 0,
50 - BLNDGAM_MEM_PWR_FORCE, power_on == true ? 0 : 1);