]> git.ipfire.org Git - thirdparty/qemu.git/commit
target/riscv: Fix the mepc when sspopchk triggers the exception
authorJim Shu <jim.shu@sifive.com>
Wed, 24 Sep 2025 07:48:16 +0000 (15:48 +0800)
committerMichael Tokarev <mjt@tls.msk.ru>
Thu, 9 Oct 2025 05:05:12 +0000 (08:05 +0300)
commit1cea32f332f2f009d08307f84040c250c82f1111
treea5a511d2a633e684f4bf3bc8cb270e2b59d39aa7
parent19a3344754e10b42cef5a26b72773008e3e5bc02
target/riscv: Fix the mepc when sspopchk triggers the exception

When sspopchk is in the middle of TB and triggers the SW check
exception, it should update PC from gen_update_pc(). If not, RISC-V mepc
CSR will get wrong PC address which is still at the start of TB.

Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250924074818.230010-2-jim.shu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
(cherry picked from commit c851052a77fd79300708df2070297b5428b4be8d)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
target/riscv/insn_trans/trans_rvzicfiss.c.inc