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dt-bindings: mailbox: qcom: Document Nord CPUCP mailbox controller
authorDeepti Jaggi <deepti.jaggi@oss.qualcomm.com>
Mon, 27 Apr 2026 00:52:35 +0000 (08:52 +0800)
committerJassi Brar <jassisinghbrar@gmail.com>
Mon, 18 May 2026 18:23:52 +0000 (13:23 -0500)
commit388f16c9372d15585b594998f34542ed00fddebf
tree0df49c73efdebb178eb9a710d6f9b7be143157cctree | snapshot
parente30d8b2730a33e5e8789371e947c3529789a6070commit | diff
dt-bindings: mailbox: qcom: Document Nord CPUCP mailbox controller

Document CPUSS Control Processor (CPUCP) mailbox controller for Qualcomm
Nord SoC, which is compatible with X1E80100 CPUCP, even though it supports
more IPC channels.

Signed-off-by: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml diff | blob | blame | history
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