]> git.ipfire.org Git - thirdparty/kernel/linux.git/commit
pinctrl: renesas: rzt2h: Add pin configuration support
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thu, 19 Mar 2026 14:15:15 +0000 (14:15 +0000)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 26 Mar 2026 19:04:28 +0000 (20:04 +0100)
commit494feecd60e876a4310cdda279d918e91f930091
tree87eeec427c34f5916d3cd7f8c533f619c718cbd0
parent9efe63b74e9c30777db9815dc5d38d667576ac6f
pinctrl: renesas: rzt2h: Add pin configuration support

Add pin configuration support for the Renesas RZ/T2H SoC. The RZ/T2H SoC
allows configuring several electrical characteristics through the DRCTLm
(I/O Buffer Function Switching) registers. These registers control bias
configuration, Schmitt trigger input, output slew rate, and drive
strength.

Implement pinconf_ops to allow reading and updating these properties
through the generic pin configuration framework. The implementation
supports bias-disable, bias-pull-up, bias-pull-down,
input-schmitt-enable, slew-rate, and drive-strength-microamp.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260319141515.2053556-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/pinctrl/renesas/pinctrl-rzt2h.c