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drm/msm/a8xx: Add perfcntr flush sequence
authorRob Clark <robin.clark@oss.qualcomm.com>
Tue, 26 May 2026 14:50:46 +0000 (07:50 -0700)
committerRob Clark <robin.clark@oss.qualcomm.com>
Fri, 29 May 2026 14:07:29 +0000 (07:07 -0700)
commit5ef26a2a4b2e55b07984e17baec179b849b52bcc
tree553e9d9c51af199a0f60f82cadd9e049f1cf062ftree | snapshot
parent5eedc8c2d0b52a44cecbd12641524b3616070c0ccommit | diff
drm/msm/a8xx: Add perfcntr flush sequence

With the slice architecture, we need to flush the slice and unslice
counters to perf RAM before reading counters.

Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Reviewed-by: Anna Maniscalco <anna.maniscalco2000@gmail.com>
Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/728216/
Message-ID: <20260526145137.160554-13-robin.clark@oss.qualcomm.com>
drivers/gpu/drm/msm/adreno/a6xx_gpu.c diff | blob | blame | history
drivers/gpu/drm/msm/adreno/a6xx_gpu.h diff | blob | blame | history
drivers/gpu/drm/msm/adreno/a8xx_gpu.c diff | blob | blame | history
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