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soc: ti: k3-socinfo: Add support for AM62P variants via NVMEM
authorJudith Mendez <jm@ti.com>
Mon, 9 Feb 2026 17:23:30 +0000 (11:23 -0600)
committerNishanth Menon <nm@ti.com>
Tue, 5 May 2026 11:06:02 +0000 (06:06 -0500)
commit97cfbd30525ef0df3de0681a4ca04a80a06d4f16
tree0ccaccba65f1e963b573cdc3f0342f11ab84d646tree | snapshot
parentb0ea5175358f0872ffdc9c6073585637dc01815acommit | diff
soc: ti: k3-socinfo: Add support for AM62P variants via NVMEM

Add support for detecting AM62P silicon revisions.

On AM62P, silicon revision is discovered with GP_SW1 register instead
of JTAGID register. Use the NVMEM framework to read GP_SW1 from the
gpsw-efuse nvmem provider to determine SoC revision.

Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Link: https://patch.msgid.link/20260209172330.53623-3-jm@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
drivers/soc/ti/k3-socinfo.c diff | blob | blame | history
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