]> git.ipfire.org Git - thirdparty/kernel/linux.git/commit
drm/xe/xe3p_xpc: Add new XeCore fuse registers to VF runtime regs
authorMatt Roper <matthew.d.roper@intel.com>
Tue, 10 Feb 2026 18:25:19 +0000 (10:25 -0800)
committerMatt Roper <matthew.d.roper@intel.com>
Thu, 12 Feb 2026 19:01:41 +0000 (11:01 -0800)
commitb5b55d0932eef682b648e456df177430968e19d5
treef05f0f6f68808c48bb817cda5207e07d0332b7ea
parent6d83ef1adaae89c2b85ec486ec90397538deba1b
drm/xe/xe3p_xpc: Add new XeCore fuse registers to VF runtime regs

SRIOV VFs do not automatically have access to the XeCore fuse registers.
Add the two new registers that show up on Xe3p_XPC to the runtime
register list to grant VFs access.  Since there's a single runtime
register list for all Xe3p, this will technically also grant access on
Xe3p_LPG platforms where the registers don't exist, but that should be
harmless since even if a VF tries to read a non-existent register on
those platforms it will just get back a sensible value of 0x0.

Fixes: e8100643ff01 ("drm/xe/xe3p_xpc: XeCore mask spans four registers")
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: Ngai-Mint Kwan <ngai-mint.kwan@linux.intel.com>
Link: https://patch.msgid.link/20260210182519.206952-2-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c