]> git.ipfire.org Git - thirdparty/qemu.git/commit
hw/riscv/riscv-iommu: Fix MSI table size limit
authorAndrew Jones <ajones@ventanamicro.com>
Thu, 4 Sep 2025 13:27:24 +0000 (08:27 -0500)
committerMichael Tokarev <mjt@tls.msk.ru>
Sat, 4 Oct 2025 06:56:23 +0000 (09:56 +0300)
commitc81d81c7a192e0644d44f80332886545c041da36
tree1f165aa655527e07cd0b13616cd9a29c653ebfb3
parent409f506518847be03520f6f5b34f659d7d605e21
hw/riscv/riscv-iommu: Fix MSI table size limit

The MSI table is not limited to 4k. The only constraint the table has
is that its base address must be aligned to its size, ensuring no
offsets of the table size will overrun when added to the base address
(see "8.5. MSI page tables" of the AIA spec).

Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20250904132723.614507-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
(cherry picked from commit 4f7528295b3e6dfe1189f660fa7865ad972d82e7)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
hw/riscv/riscv-iommu.c