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Docs: iio: ad7191 Correct clock configuration
authorAmmar Mustafa <ammarmustafa34@gmail.com>
Fri, 27 Feb 2026 19:08:33 +0000 (14:08 -0500)
committerJonathan Cameron <Jonathan.Cameron@huawei.com>
Fri, 27 Mar 2026 07:31:19 +0000 (07:31 +0000)
commitd2a4ec19d2a2e54c23b5180e939994d3da4a6b91
treefafd605ff6cbc4d436abc97d996c68f31d9253ectree | snapshot
parentd185324efadc1e75acc6be2e4351ecfe8957b3a7commit | diff
Docs: iio: ad7191 Correct clock configuration

Correct the ad7191 documentation to match the datasheet:
- Fix inverted CLKSEL pin logic: device uses external clock when pin is
  inactive, and internal CMOS/crystal when high.
- Correct CMOS-compatible clock pin from MCLK2 to MCLK1.

Signed-off-by: Ammar Mustafa <ammarmustafa34@gmail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Documentation/iio/ad7191.rst diff | blob | blame | history
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