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author	Richard Henderson <richard.henderson@linaro.org>
	Sat, 21 Dec 2024 16:50:26 +0000 (16:50 +0000)
committer	Richard Henderson <richard.henderson@linaro.org>
	Tue, 24 Dec 2024 16:32:15 +0000 (08:32 -0800)
commit	e4a8e093dc74be049f4829831dce76e5edab0003
tree	20354b9913086ac3a535e06e4d28057f88710d14	tree \| snapshot
parent	59abfb444e1d9654e15f85c50d09a3366e4c1c1e	commit \| diff

accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core

Convert all targets simultaneously, as the gen_intermediate_code
function disappears from the target. While there are possible
workarounds, they're larger than simply performing the conversion.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

62 files changed:

accel/tcg/cpu-exec.c		diff \| blob \| blame \| history
accel/tcg/translate-all.c		diff \| blob \| blame \| history
include/exec/translator.h		diff \| blob \| blame \| history
include/hw/core/tcg-cpu-ops.h		diff \| blob \| blame \| history
target/alpha/cpu.c		diff \| blob \| blame \| history
target/alpha/cpu.h		diff \| blob \| blame \| history
target/alpha/translate.c		diff \| blob \| blame \| history
target/arm/cpu.c		diff \| blob \| blame \| history
target/arm/internals.h		diff \| blob \| blame \| history
target/arm/tcg/cpu-v7m.c		diff \| blob \| blame \| history
target/arm/tcg/translate.c		diff \| blob \| blame \| history
target/avr/cpu.c		diff \| blob \| blame \| history
target/avr/cpu.h		diff \| blob \| blame \| history
target/avr/translate.c		diff \| blob \| blame \| history
target/hexagon/cpu.c		diff \| blob \| blame \| history
target/hexagon/cpu.h		diff \| blob \| blame \| history
target/hexagon/translate.c		diff \| blob \| blame \| history
target/hppa/cpu.c		diff \| blob \| blame \| history
target/hppa/cpu.h		diff \| blob \| blame \| history
target/hppa/translate.c		diff \| blob \| blame \| history
target/i386/tcg/helper-tcg.h		diff \| blob \| blame \| history
target/i386/tcg/tcg-cpu.c		diff \| blob \| blame \| history
target/i386/tcg/translate.c		diff \| blob \| blame \| history
target/loongarch/cpu.c		diff \| blob \| blame \| history
target/loongarch/internals.h		diff \| blob \| blame \| history
target/loongarch/tcg/translate.c		diff \| blob \| blame \| history
target/m68k/cpu.c		diff \| blob \| blame \| history
target/m68k/cpu.h		diff \| blob \| blame \| history
target/m68k/translate.c		diff \| blob \| blame \| history
target/microblaze/cpu.c		diff \| blob \| blame \| history
target/microblaze/cpu.h		diff \| blob \| blame \| history
target/microblaze/translate.c		diff \| blob \| blame \| history
target/mips/cpu.c		diff \| blob \| blame \| history
target/mips/tcg/tcg-internal.h		diff \| blob \| blame \| history
target/mips/tcg/translate.c		diff \| blob \| blame \| history
target/openrisc/cpu.c		diff \| blob \| blame \| history
target/openrisc/cpu.h		diff \| blob \| blame \| history
target/openrisc/translate.c		diff \| blob \| blame \| history
target/ppc/cpu.h		diff \| blob \| blame \| history
target/ppc/cpu_init.c		diff \| blob \| blame \| history
target/ppc/translate.c		diff \| blob \| blame \| history
target/riscv/cpu.h		diff \| blob \| blame \| history
target/riscv/tcg/tcg-cpu.c		diff \| blob \| blame \| history
target/riscv/translate.c		diff \| blob \| blame \| history
target/rx/cpu.c		diff \| blob \| blame \| history
target/rx/cpu.h		diff \| blob \| blame \| history
target/rx/translate.c		diff \| blob \| blame \| history
target/s390x/cpu.c		diff \| blob \| blame \| history
target/s390x/s390x-internal.h		diff \| blob \| blame \| history
target/s390x/tcg/translate.c		diff \| blob \| blame \| history
target/sh4/cpu.c		diff \| blob \| blame \| history
target/sh4/cpu.h		diff \| blob \| blame \| history
target/sh4/translate.c		diff \| blob \| blame \| history
target/sparc/cpu.c		diff \| blob \| blame \| history
target/sparc/cpu.h		diff \| blob \| blame \| history
target/sparc/translate.c		diff \| blob \| blame \| history
target/tricore/cpu.c		diff \| blob \| blame \| history
target/tricore/cpu.h		diff \| blob \| blame \| history
target/tricore/translate.c		diff \| blob \| blame \| history
target/xtensa/cpu.c		diff \| blob \| blame \| history
target/xtensa/cpu.h		diff \| blob \| blame \| history
target/xtensa/translate.c		diff \| blob \| blame \| history

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